1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 119 /* re-use enc ring as unified ring */ 120 adev->vcn.inst[i].num_enc_rings = 1; 121 122 vcn_v4_0_3_set_unified_ring_funcs(adev); 123 vcn_v4_0_3_set_irq_funcs(adev); 124 vcn_v4_0_3_set_ras_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 138 { 139 struct amdgpu_vcn4_fw_shared *fw_shared; 140 141 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 142 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 143 fw_shared->sq.is_enabled = 1; 144 145 if (amdgpu_vcnfw_log) 146 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 147 148 return 0; 149 } 150 151 /** 152 * vcn_v4_0_3_sw_init - sw init for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * Load firmware and sw initialization 157 */ 158 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_device *adev = ip_block->adev; 161 struct amdgpu_ring *ring; 162 int i, r, vcn_inst; 163 164 /* VCN DEC TRAP */ 165 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 166 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 167 if (r) 168 return r; 169 170 /* VCN POISON TRAP */ 171 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 172 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 173 174 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 175 176 r = amdgpu_vcn_sw_init(adev, i); 177 if (r) 178 return r; 179 180 amdgpu_vcn_setup_ucode(adev, i); 181 182 r = amdgpu_vcn_resume(adev, i); 183 if (r) 184 return r; 185 186 vcn_inst = GET_INST(VCN, i); 187 188 ring = &adev->vcn.inst[i].ring_enc[0]; 189 ring->use_doorbell = true; 190 191 if (!amdgpu_sriov_vf(adev)) 192 ring->doorbell_index = 193 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 194 9 * vcn_inst; 195 else 196 ring->doorbell_index = 197 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 198 32 * vcn_inst; 199 200 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 201 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 202 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 203 AMDGPU_RING_PRIO_DEFAULT, 204 &adev->vcn.inst[i].sched_score); 205 if (r) 206 return r; 207 208 vcn_v4_0_3_fw_shared_init(adev, i); 209 210 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 211 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 212 } 213 214 /* TODO: Add queue reset mask when FW fully supports it */ 215 adev->vcn.supported_reset = 216 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 217 218 if (amdgpu_sriov_vf(adev)) { 219 r = amdgpu_virt_alloc_mm_table(adev); 220 if (r) 221 return r; 222 } 223 224 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 225 r = amdgpu_vcn_ras_sw_init(adev); 226 if (r) { 227 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 228 return r; 229 } 230 } 231 232 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3)); 233 if (r) 234 return r; 235 236 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 237 if (r) 238 return r; 239 240 return 0; 241 } 242 243 /** 244 * vcn_v4_0_3_sw_fini - sw fini for VCN block 245 * 246 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 247 * 248 * VCN suspend and free up sw allocation 249 */ 250 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 251 { 252 struct amdgpu_device *adev = ip_block->adev; 253 int i, r, idx; 254 255 if (drm_dev_enter(&adev->ddev, &idx)) { 256 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 257 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 258 259 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 260 fw_shared->present_flag_0 = 0; 261 fw_shared->sq.is_enabled = cpu_to_le32(false); 262 } 263 drm_dev_exit(idx); 264 } 265 266 if (amdgpu_sriov_vf(adev)) 267 amdgpu_virt_free_mm_table(adev); 268 269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 270 r = amdgpu_vcn_suspend(adev, i); 271 if (r) 272 return r; 273 } 274 275 amdgpu_vcn_sysfs_reset_mask_fini(adev); 276 277 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 278 r = amdgpu_vcn_sw_fini(adev, i); 279 if (r) 280 return r; 281 } 282 283 return 0; 284 } 285 286 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 287 { 288 int vcn_inst; 289 struct amdgpu_device *adev = vinst->adev; 290 struct amdgpu_ring *ring; 291 int inst_idx = vinst->inst; 292 293 vcn_inst = GET_INST(VCN, inst_idx); 294 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 295 if (ring->use_doorbell) { 296 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 297 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 298 adev->vcn.inst[inst_idx].aid_id); 299 300 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 301 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 302 VCN_RB1_DB_CTRL__EN_MASK); 303 304 /* Read DB_CTRL to flush the write DB_CTRL command. */ 305 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 306 } 307 308 return 0; 309 } 310 311 /** 312 * vcn_v4_0_3_hw_init - start and test VCN block 313 * 314 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 315 * 316 * Initialize the hardware, boot up the VCPU and do some testing 317 */ 318 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 319 { 320 struct amdgpu_device *adev = ip_block->adev; 321 struct amdgpu_ring *ring; 322 struct amdgpu_vcn_inst *vinst; 323 int i, r; 324 325 if (amdgpu_sriov_vf(adev)) { 326 r = vcn_v4_0_3_start_sriov(adev); 327 if (r) 328 return r; 329 330 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 331 ring = &adev->vcn.inst[i].ring_enc[0]; 332 ring->wptr = 0; 333 ring->wptr_old = 0; 334 vcn_v4_0_3_unified_ring_set_wptr(ring); 335 ring->sched.ready = true; 336 } 337 } else { 338 /* This flag is not set for VF, assumed to be disabled always */ 339 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 340 0x100) 341 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 342 343 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 344 struct amdgpu_vcn4_fw_shared *fw_shared; 345 346 ring = &adev->vcn.inst[i].ring_enc[0]; 347 vinst = &adev->vcn.inst[i]; 348 vcn_v4_0_3_hw_init_inst(vinst); 349 350 /* Re-init fw_shared when RAS fatal error occurred */ 351 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 352 if (!fw_shared->sq.is_enabled) 353 vcn_v4_0_3_fw_shared_init(adev, i); 354 355 r = amdgpu_ring_test_helper(ring); 356 if (r) 357 return r; 358 } 359 } 360 361 return r; 362 } 363 364 /** 365 * vcn_v4_0_3_hw_fini - stop the hardware block 366 * 367 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 368 * 369 * Stop the VCN block, mark ring as not ready any more 370 */ 371 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 372 { 373 struct amdgpu_device *adev = ip_block->adev; 374 int i; 375 376 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 377 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 378 379 cancel_delayed_work_sync(&vinst->idle_work); 380 381 if (vinst->cur_state != AMD_PG_STATE_GATE) 382 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 383 } 384 385 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) 386 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 387 388 return 0; 389 } 390 391 /** 392 * vcn_v4_0_3_suspend - suspend VCN block 393 * 394 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 395 * 396 * HW fini and suspend VCN block 397 */ 398 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 399 { 400 struct amdgpu_device *adev = ip_block->adev; 401 int r, i; 402 403 r = vcn_v4_0_3_hw_fini(ip_block); 404 if (r) 405 return r; 406 407 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 408 r = amdgpu_vcn_suspend(adev, i); 409 if (r) 410 return r; 411 } 412 413 return 0; 414 } 415 416 /** 417 * vcn_v4_0_3_resume - resume VCN block 418 * 419 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 420 * 421 * Resume firmware and hw init VCN block 422 */ 423 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 424 { 425 struct amdgpu_device *adev = ip_block->adev; 426 int r, i; 427 428 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 429 r = amdgpu_vcn_resume(ip_block->adev, i); 430 if (r) 431 return r; 432 } 433 434 r = vcn_v4_0_3_hw_init(ip_block); 435 436 return r; 437 } 438 439 /** 440 * vcn_v4_0_3_mc_resume - memory controller programming 441 * 442 * @vinst: VCN instance 443 * 444 * Let the VCN memory controller know it's offsets 445 */ 446 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 447 { 448 struct amdgpu_device *adev = vinst->adev; 449 int inst_idx = vinst->inst; 450 uint32_t offset, size, vcn_inst; 451 const struct common_firmware_header *hdr; 452 453 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 454 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 455 456 vcn_inst = GET_INST(VCN, inst_idx); 457 /* cache window 0: fw */ 458 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 459 WREG32_SOC15( 460 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 461 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 462 .tmr_mc_addr_lo)); 463 WREG32_SOC15( 464 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 465 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 466 .tmr_mc_addr_hi)); 467 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 468 offset = 0; 469 } else { 470 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 471 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 472 WREG32_SOC15(VCN, vcn_inst, 473 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 474 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 475 offset = size; 476 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 477 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 478 } 479 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 480 481 /* cache window 1: stack */ 482 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 483 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 484 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 485 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 486 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 487 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 488 AMDGPU_VCN_STACK_SIZE); 489 490 /* cache window 2: context */ 491 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 492 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 493 AMDGPU_VCN_STACK_SIZE)); 494 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 495 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 496 AMDGPU_VCN_STACK_SIZE)); 497 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 498 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 499 AMDGPU_VCN_CONTEXT_SIZE); 500 501 /* non-cache window */ 502 WREG32_SOC15( 503 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 504 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 505 WREG32_SOC15( 506 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 507 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 508 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 509 WREG32_SOC15( 510 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 511 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 512 } 513 514 /** 515 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 516 * 517 * @vinst: VCN instance 518 * @indirect: indirectly write sram 519 * 520 * Let the VCN memory controller know it's offsets with dpg mode 521 */ 522 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 523 bool indirect) 524 { 525 struct amdgpu_device *adev = vinst->adev; 526 int inst_idx = vinst->inst; 527 uint32_t offset, size; 528 const struct common_firmware_header *hdr; 529 530 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 531 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 532 533 /* cache window 0: fw */ 534 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 535 if (!indirect) { 536 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 537 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 538 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 539 inst_idx].tmr_mc_addr_lo), 0, indirect); 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 542 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 543 inst_idx].tmr_mc_addr_hi), 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 546 } else { 547 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 548 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 553 } 554 offset = 0; 555 } else { 556 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 557 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 558 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 561 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 562 offset = size; 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 565 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 566 } 567 568 if (!indirect) 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 571 else 572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 573 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 574 575 /* cache window 1: stack */ 576 if (!indirect) { 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 579 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 582 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 585 } else { 586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 587 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 591 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 592 } 593 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 594 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 595 596 /* cache window 2: context */ 597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 598 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 599 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 600 AMDGPU_VCN_STACK_SIZE), 0, indirect); 601 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 602 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 603 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 604 AMDGPU_VCN_STACK_SIZE), 0, indirect); 605 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 606 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 607 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 608 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 609 610 /* non-cache window */ 611 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 612 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 613 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 614 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 615 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 616 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 617 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 618 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 621 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 622 623 /* VCN global tiling registers */ 624 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 625 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 626 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 627 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 628 } 629 630 /** 631 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 632 * 633 * @vinst: VCN instance 634 * 635 * Disable clock gating for VCN block 636 */ 637 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 638 { 639 struct amdgpu_device *adev = vinst->adev; 640 int inst_idx = vinst->inst; 641 uint32_t data; 642 int vcn_inst; 643 644 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 645 return; 646 647 vcn_inst = GET_INST(VCN, inst_idx); 648 649 /* VCN disable CGC */ 650 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 651 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 652 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 653 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 654 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 655 656 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 657 data &= ~(UVD_CGC_GATE__SYS_MASK 658 | UVD_CGC_GATE__MPEG2_MASK 659 | UVD_CGC_GATE__REGS_MASK 660 | UVD_CGC_GATE__RBC_MASK 661 | UVD_CGC_GATE__LMI_MC_MASK 662 | UVD_CGC_GATE__LMI_UMC_MASK 663 | UVD_CGC_GATE__MPC_MASK 664 | UVD_CGC_GATE__LBSI_MASK 665 | UVD_CGC_GATE__LRBBM_MASK 666 | UVD_CGC_GATE__WCB_MASK 667 | UVD_CGC_GATE__VCPU_MASK 668 | UVD_CGC_GATE__MMSCH_MASK); 669 670 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 671 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 672 673 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 674 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 675 | UVD_CGC_CTRL__MPEG2_MODE_MASK 676 | UVD_CGC_CTRL__REGS_MODE_MASK 677 | UVD_CGC_CTRL__RBC_MODE_MASK 678 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 679 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 680 | UVD_CGC_CTRL__MPC_MODE_MASK 681 | UVD_CGC_CTRL__LBSI_MODE_MASK 682 | UVD_CGC_CTRL__LRBBM_MODE_MASK 683 | UVD_CGC_CTRL__WCB_MODE_MASK 684 | UVD_CGC_CTRL__VCPU_MODE_MASK 685 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 686 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 687 688 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 689 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 690 | UVD_SUVD_CGC_GATE__SIT_MASK 691 | UVD_SUVD_CGC_GATE__SMP_MASK 692 | UVD_SUVD_CGC_GATE__SCM_MASK 693 | UVD_SUVD_CGC_GATE__SDB_MASK 694 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 695 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 696 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 697 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 698 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 699 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 700 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 701 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 702 | UVD_SUVD_CGC_GATE__ENT_MASK 703 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 704 | UVD_SUVD_CGC_GATE__SITE_MASK 705 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 706 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 707 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 708 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 709 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 710 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 711 712 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 713 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 714 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 715 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 716 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 717 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 718 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 721 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 722 } 723 724 /** 725 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 726 * 727 * @vinst: VCN instance 728 * @sram_sel: sram select 729 * @indirect: indirectly write sram 730 * 731 * Disable clock gating for VCN block with dpg mode 732 */ 733 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 734 uint8_t sram_sel, 735 uint8_t indirect) 736 { 737 struct amdgpu_device *adev = vinst->adev; 738 int inst_idx = vinst->inst; 739 uint32_t reg_data = 0; 740 741 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 742 return; 743 744 /* enable sw clock gating control */ 745 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 746 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 747 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 748 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 749 UVD_CGC_CTRL__MPEG2_MODE_MASK | 750 UVD_CGC_CTRL__REGS_MODE_MASK | 751 UVD_CGC_CTRL__RBC_MODE_MASK | 752 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 753 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 754 UVD_CGC_CTRL__IDCT_MODE_MASK | 755 UVD_CGC_CTRL__MPRD_MODE_MASK | 756 UVD_CGC_CTRL__MPC_MODE_MASK | 757 UVD_CGC_CTRL__LBSI_MODE_MASK | 758 UVD_CGC_CTRL__LRBBM_MODE_MASK | 759 UVD_CGC_CTRL__WCB_MODE_MASK | 760 UVD_CGC_CTRL__VCPU_MODE_MASK); 761 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 762 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 763 764 /* turn off clock gating */ 765 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 766 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 767 768 /* turn on SUVD clock gating */ 769 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 770 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 771 772 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 773 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 774 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 775 } 776 777 /** 778 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 779 * 780 * @vinst: VCN instance 781 * 782 * Enable clock gating for VCN block 783 */ 784 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 785 { 786 struct amdgpu_device *adev = vinst->adev; 787 int inst_idx = vinst->inst; 788 uint32_t data; 789 int vcn_inst; 790 791 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 792 return; 793 794 vcn_inst = GET_INST(VCN, inst_idx); 795 796 /* enable VCN CGC */ 797 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 798 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 799 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 800 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 801 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 802 803 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 804 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 805 | UVD_CGC_CTRL__MPEG2_MODE_MASK 806 | UVD_CGC_CTRL__REGS_MODE_MASK 807 | UVD_CGC_CTRL__RBC_MODE_MASK 808 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 809 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 810 | UVD_CGC_CTRL__MPC_MODE_MASK 811 | UVD_CGC_CTRL__LBSI_MODE_MASK 812 | UVD_CGC_CTRL__LRBBM_MODE_MASK 813 | UVD_CGC_CTRL__WCB_MODE_MASK 814 | UVD_CGC_CTRL__VCPU_MODE_MASK); 815 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 816 817 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 818 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 826 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 827 } 828 829 /** 830 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 831 * 832 * @vinst: VCN instance 833 * @indirect: indirectly write sram 834 * 835 * Start VCN block with dpg mode 836 */ 837 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 838 bool indirect) 839 { 840 struct amdgpu_device *adev = vinst->adev; 841 int inst_idx = vinst->inst; 842 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 843 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 844 struct amdgpu_ring *ring; 845 int vcn_inst, ret; 846 uint32_t tmp; 847 848 vcn_inst = GET_INST(VCN, inst_idx); 849 /* disable register anti-hang mechanism */ 850 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 851 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 852 /* enable dynamic power gating mode */ 853 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 854 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 855 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 856 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 857 858 if (indirect) { 859 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 860 inst_idx, adev->vcn.inst[inst_idx].aid_id); 861 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 862 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 863 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 864 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 865 adev->vcn.inst[inst_idx].aid_id, 0, true); 866 } 867 868 /* enable clock gating */ 869 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 870 871 /* enable VCPU clock */ 872 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 873 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 874 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 875 876 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 877 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 878 879 /* disable master interrupt */ 880 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 881 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 882 883 /* setup regUVD_LMI_CTRL */ 884 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 885 UVD_LMI_CTRL__REQ_MODE_MASK | 886 UVD_LMI_CTRL__CRC_RESET_MASK | 887 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 888 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 889 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 890 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 891 0x00100000L); 892 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 893 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 894 895 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 896 VCN, 0, regUVD_MPC_CNTL), 897 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 898 899 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 900 VCN, 0, regUVD_MPC_SET_MUXA0), 901 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 902 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 903 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 904 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 905 906 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 907 VCN, 0, regUVD_MPC_SET_MUXB0), 908 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 909 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 910 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 911 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 912 913 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 914 VCN, 0, regUVD_MPC_SET_MUX), 915 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 916 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 917 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 918 919 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 920 921 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 922 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 923 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 924 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 925 926 /* enable LMI MC and UMC channels */ 927 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 928 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 929 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 930 931 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 932 933 /* enable master interrupt */ 934 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 935 VCN, 0, regUVD_MASTINT_EN), 936 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 937 938 if (indirect) { 939 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 940 if (ret) { 941 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 942 return ret; 943 } 944 } 945 946 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 947 948 /* program the RB_BASE for ring buffer */ 949 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 950 lower_32_bits(ring->gpu_addr)); 951 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 952 upper_32_bits(ring->gpu_addr)); 953 954 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 955 ring->ring_size / sizeof(uint32_t)); 956 957 /* resetting ring, fw should not check RB ring */ 958 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 959 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 960 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 961 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 962 963 /* Initialize the ring buffer's read and write pointers */ 964 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 965 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 966 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 967 968 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 969 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 970 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 971 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 972 973 /*resetting done, fw can check RB ring */ 974 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 975 976 /* Keeping one read-back to ensure all register writes are done, 977 * otherwise it may introduce race conditions. 978 */ 979 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 980 981 return 0; 982 } 983 984 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 985 { 986 int i, vcn_inst; 987 struct amdgpu_ring *ring_enc; 988 uint64_t cache_addr; 989 uint64_t rb_enc_addr; 990 uint64_t ctx_addr; 991 uint32_t param, resp, expected; 992 uint32_t offset, cache_size; 993 uint32_t tmp, timeout; 994 995 struct amdgpu_mm_table *table = &adev->virt.mm_table; 996 uint32_t *table_loc; 997 uint32_t table_size; 998 uint32_t size, size_dw; 999 uint32_t init_status; 1000 uint32_t enabled_vcn; 1001 1002 struct mmsch_v4_0_cmd_direct_write 1003 direct_wt = { {0} }; 1004 struct mmsch_v4_0_cmd_direct_read_modify_write 1005 direct_rd_mod_wt = { {0} }; 1006 struct mmsch_v4_0_cmd_end end = { {0} }; 1007 struct mmsch_v4_0_3_init_header header; 1008 1009 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1010 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1011 1012 direct_wt.cmd_header.command_type = 1013 MMSCH_COMMAND__DIRECT_REG_WRITE; 1014 direct_rd_mod_wt.cmd_header.command_type = 1015 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1016 end.cmd_header.command_type = MMSCH_COMMAND__END; 1017 1018 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1019 vcn_inst = GET_INST(VCN, i); 1020 1021 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1022 1023 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1024 header.version = MMSCH_VERSION; 1025 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1026 1027 table_loc = (uint32_t *)table->cpu_addr; 1028 table_loc += header.total_size; 1029 1030 table_size = 0; 1031 1032 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1033 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1034 1035 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1036 1037 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1038 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1039 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1040 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1041 1042 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1043 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1044 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1045 1046 offset = 0; 1047 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1048 regUVD_VCPU_CACHE_OFFSET0), 0); 1049 } else { 1050 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1051 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1052 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1053 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1054 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1055 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1056 offset = cache_size; 1057 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1058 regUVD_VCPU_CACHE_OFFSET0), 1059 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1060 } 1061 1062 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1063 regUVD_VCPU_CACHE_SIZE0), 1064 cache_size); 1065 1066 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1067 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1068 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1069 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1070 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1071 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1072 regUVD_VCPU_CACHE_OFFSET1), 0); 1073 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1074 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1075 1076 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1077 AMDGPU_VCN_STACK_SIZE; 1078 1079 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1080 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1081 1082 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1083 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1084 1085 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1086 regUVD_VCPU_CACHE_OFFSET2), 0); 1087 1088 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1089 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1090 1091 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1092 rb_setup = &fw_shared->rb_setup; 1093 1094 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1095 ring_enc->wptr = 0; 1096 rb_enc_addr = ring_enc->gpu_addr; 1097 1098 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1099 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1100 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1101 rb_setup->rb_size = ring_enc->ring_size / 4; 1102 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1103 1104 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1105 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1106 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1107 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1108 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1109 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1110 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1111 regUVD_VCPU_NONCACHE_SIZE0), 1112 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1113 MMSCH_V4_0_INSERT_END(); 1114 1115 header.vcn0.init_status = 0; 1116 header.vcn0.table_offset = header.total_size; 1117 header.vcn0.table_size = table_size; 1118 header.total_size += table_size; 1119 1120 /* Send init table to mmsch */ 1121 size = sizeof(struct mmsch_v4_0_3_init_header); 1122 table_loc = (uint32_t *)table->cpu_addr; 1123 memcpy((void *)table_loc, &header, size); 1124 1125 ctx_addr = table->gpu_addr; 1126 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1127 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1128 1129 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1130 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1131 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1132 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1133 1134 size = header.total_size; 1135 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1136 1137 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1138 1139 param = 0x00000001; 1140 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1141 tmp = 0; 1142 timeout = 1000; 1143 resp = 0; 1144 expected = MMSCH_VF_MAILBOX_RESP__OK; 1145 while (resp != expected) { 1146 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1147 if (resp != 0) 1148 break; 1149 1150 udelay(10); 1151 tmp = tmp + 10; 1152 if (tmp >= timeout) { 1153 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1154 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1155 "(expected=0x%08x, readback=0x%08x)\n", 1156 tmp, expected, resp); 1157 return -EBUSY; 1158 } 1159 } 1160 1161 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1162 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1163 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1164 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1165 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1166 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1167 } 1168 } 1169 1170 return 0; 1171 } 1172 1173 /** 1174 * vcn_v4_0_3_start - VCN start 1175 * 1176 * @vinst: VCN instance 1177 * 1178 * Start VCN block 1179 */ 1180 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1181 { 1182 struct amdgpu_device *adev = vinst->adev; 1183 int i = vinst->inst; 1184 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1185 struct amdgpu_ring *ring; 1186 int j, k, r, vcn_inst; 1187 uint32_t tmp; 1188 1189 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1190 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1191 1192 vcn_inst = GET_INST(VCN, i); 1193 /* set VCN status busy */ 1194 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1195 UVD_STATUS__UVD_BUSY; 1196 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1197 1198 /* SW clock gating */ 1199 vcn_v4_0_3_disable_clock_gating(vinst); 1200 1201 /* enable VCPU clock */ 1202 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1203 UVD_VCPU_CNTL__CLK_EN_MASK, 1204 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1205 1206 /* disable master interrupt */ 1207 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1208 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1209 1210 /* enable LMI MC and UMC channels */ 1211 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1212 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1213 1214 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1215 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1216 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1217 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1218 1219 /* setup regUVD_LMI_CTRL */ 1220 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1221 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1222 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1223 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1224 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1225 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1226 1227 /* setup regUVD_MPC_CNTL */ 1228 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1229 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1230 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1231 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1232 1233 /* setup UVD_MPC_SET_MUXA0 */ 1234 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1235 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1236 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1237 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1238 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1239 1240 /* setup UVD_MPC_SET_MUXB0 */ 1241 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1242 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1243 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1244 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1245 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1246 1247 /* setup UVD_MPC_SET_MUX */ 1248 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1249 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1250 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1251 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1252 1253 vcn_v4_0_3_mc_resume(vinst); 1254 1255 /* VCN global tiling registers */ 1256 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1257 adev->gfx.config.gb_addr_config); 1258 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1259 adev->gfx.config.gb_addr_config); 1260 1261 /* unblock VCPU register access */ 1262 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1263 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1264 1265 /* release VCPU reset to boot */ 1266 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1267 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1268 1269 for (j = 0; j < 10; ++j) { 1270 uint32_t status; 1271 1272 for (k = 0; k < 100; ++k) { 1273 status = RREG32_SOC15(VCN, vcn_inst, 1274 regUVD_STATUS); 1275 if (status & 2) 1276 break; 1277 mdelay(10); 1278 } 1279 r = 0; 1280 if (status & 2) 1281 break; 1282 1283 DRM_DEV_ERROR(adev->dev, 1284 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1285 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1286 regUVD_VCPU_CNTL), 1287 UVD_VCPU_CNTL__BLK_RST_MASK, 1288 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1289 mdelay(10); 1290 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1291 regUVD_VCPU_CNTL), 1292 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1293 1294 mdelay(10); 1295 r = -1; 1296 } 1297 1298 if (r) { 1299 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1300 return r; 1301 } 1302 1303 /* enable master interrupt */ 1304 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1305 UVD_MASTINT_EN__VCPU_EN_MASK, 1306 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1307 1308 /* clear the busy bit of VCN_STATUS */ 1309 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1310 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1311 1312 ring = &adev->vcn.inst[i].ring_enc[0]; 1313 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1314 1315 /* program the RB_BASE for ring buffer */ 1316 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1317 lower_32_bits(ring->gpu_addr)); 1318 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1319 upper_32_bits(ring->gpu_addr)); 1320 1321 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1322 ring->ring_size / sizeof(uint32_t)); 1323 1324 /* resetting ring, fw should not check RB ring */ 1325 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1326 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1327 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1328 1329 /* Initialize the ring buffer's read and write pointers */ 1330 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1331 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1332 1333 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1334 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1335 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1336 1337 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1338 fw_shared->sq.queue_mode &= 1339 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1340 1341 return 0; 1342 } 1343 1344 /** 1345 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1346 * 1347 * @vinst: VCN instance 1348 * 1349 * Stop VCN block with dpg mode 1350 */ 1351 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1352 { 1353 struct amdgpu_device *adev = vinst->adev; 1354 int inst_idx = vinst->inst; 1355 uint32_t tmp; 1356 int vcn_inst; 1357 1358 vcn_inst = GET_INST(VCN, inst_idx); 1359 1360 /* Wait for power status to be 1 */ 1361 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1362 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1363 1364 /* wait for read ptr to be equal to write ptr */ 1365 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1366 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1367 1368 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1369 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1370 1371 /* disable dynamic power gating mode */ 1372 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1373 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1374 1375 /* Keeping one read-back to ensure all register writes are done, 1376 * otherwise it may introduce race conditions. 1377 */ 1378 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1379 1380 return 0; 1381 } 1382 1383 /** 1384 * vcn_v4_0_3_stop - VCN stop 1385 * 1386 * @vinst: VCN instance 1387 * 1388 * Stop VCN block 1389 */ 1390 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1391 { 1392 struct amdgpu_device *adev = vinst->adev; 1393 int i = vinst->inst; 1394 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1395 int r = 0, vcn_inst; 1396 uint32_t tmp; 1397 1398 vcn_inst = GET_INST(VCN, i); 1399 1400 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1401 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1402 1403 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1404 vcn_v4_0_3_stop_dpg_mode(vinst); 1405 goto Done; 1406 } 1407 1408 /* wait for vcn idle */ 1409 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1410 UVD_STATUS__IDLE, 0x7); 1411 if (r) 1412 goto Done; 1413 1414 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1415 UVD_LMI_STATUS__READ_CLEAN_MASK | 1416 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1417 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1418 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1419 tmp); 1420 if (r) 1421 goto Done; 1422 1423 /* stall UMC channel */ 1424 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1425 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1426 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1427 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1428 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1429 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1430 tmp); 1431 if (r) 1432 goto Done; 1433 1434 /* Unblock VCPU Register access */ 1435 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1436 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1437 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1438 1439 /* release VCPU reset to boot */ 1440 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1441 UVD_VCPU_CNTL__BLK_RST_MASK, 1442 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1443 1444 /* disable VCPU clock */ 1445 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1446 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1447 1448 /* reset LMI UMC/LMI/VCPU */ 1449 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1450 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1451 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1452 1453 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1454 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1455 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1456 1457 /* clear VCN status */ 1458 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1459 1460 /* apply HW clock gating */ 1461 vcn_v4_0_3_enable_clock_gating(vinst); 1462 1463 /* Keeping one read-back to ensure all register writes are done, 1464 * otherwise it may introduce race conditions. 1465 */ 1466 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1467 1468 Done: 1469 return 0; 1470 } 1471 1472 /** 1473 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1474 * 1475 * @vinst: VCN instance 1476 * @new_state: pause state 1477 * 1478 * Pause dpg mode for VCN block 1479 */ 1480 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1481 struct dpg_pause_state *new_state) 1482 { 1483 1484 return 0; 1485 } 1486 1487 /** 1488 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1489 * 1490 * @ring: amdgpu_ring pointer 1491 * 1492 * Returns the current hardware unified read pointer 1493 */ 1494 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1495 { 1496 struct amdgpu_device *adev = ring->adev; 1497 1498 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1499 DRM_ERROR("wrong ring id is identified in %s", __func__); 1500 1501 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1502 } 1503 1504 /** 1505 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1506 * 1507 * @ring: amdgpu_ring pointer 1508 * 1509 * Returns the current hardware unified write pointer 1510 */ 1511 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1512 { 1513 struct amdgpu_device *adev = ring->adev; 1514 1515 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1516 DRM_ERROR("wrong ring id is identified in %s", __func__); 1517 1518 if (ring->use_doorbell) 1519 return *ring->wptr_cpu_addr; 1520 else 1521 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1522 regUVD_RB_WPTR); 1523 } 1524 1525 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1526 uint32_t val, uint32_t mask) 1527 { 1528 /* Use normalized offsets when required */ 1529 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1530 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1531 1532 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1533 amdgpu_ring_write(ring, reg << 2); 1534 amdgpu_ring_write(ring, mask); 1535 amdgpu_ring_write(ring, val); 1536 } 1537 1538 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1539 uint32_t val) 1540 { 1541 /* Use normalized offsets when required */ 1542 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1543 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1544 1545 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1546 amdgpu_ring_write(ring, reg << 2); 1547 amdgpu_ring_write(ring, val); 1548 } 1549 1550 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1551 unsigned int vmid, uint64_t pd_addr) 1552 { 1553 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1554 1555 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1556 1557 /* wait for reg writes */ 1558 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1559 vmid * hub->ctx_addr_distance, 1560 lower_32_bits(pd_addr), 0xffffffff); 1561 } 1562 1563 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1564 { 1565 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1566 * This is a workaround to avoid any HDP flush through VCN ring. 1567 */ 1568 } 1569 1570 /** 1571 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1572 * 1573 * @ring: amdgpu_ring pointer 1574 * 1575 * Commits the enc write pointer to the hardware 1576 */ 1577 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1578 { 1579 struct amdgpu_device *adev = ring->adev; 1580 1581 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1582 DRM_ERROR("wrong ring id is identified in %s", __func__); 1583 1584 if (ring->use_doorbell) { 1585 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1586 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1587 } else { 1588 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1589 lower_32_bits(ring->wptr)); 1590 } 1591 } 1592 1593 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, 1594 unsigned int vmid, 1595 struct amdgpu_fence *timedout_fence) 1596 { 1597 int r = 0; 1598 int vcn_inst; 1599 struct amdgpu_device *adev = ring->adev; 1600 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1601 1602 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1603 1604 vcn_inst = GET_INST(VCN, ring->me); 1605 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1606 1607 if (r) { 1608 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1609 return r; 1610 } 1611 1612 /* This flag is not set for VF, assumed to be disabled always */ 1613 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1614 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1615 vcn_v4_0_3_hw_init_inst(vinst); 1616 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1617 1618 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1619 } 1620 1621 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1622 .type = AMDGPU_RING_TYPE_VCN_ENC, 1623 .align_mask = 0x3f, 1624 .nop = VCN_ENC_CMD_NO_OP, 1625 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1626 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1627 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1628 .emit_frame_size = 1629 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1630 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1631 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1632 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1633 1, /* vcn_v2_0_enc_ring_insert_end */ 1634 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1635 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1636 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1637 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1638 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1639 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1640 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1641 .insert_nop = amdgpu_ring_insert_nop, 1642 .insert_end = vcn_v2_0_enc_ring_insert_end, 1643 .pad_ib = amdgpu_ring_generic_pad_ib, 1644 .begin_use = amdgpu_vcn_ring_begin_use, 1645 .end_use = amdgpu_vcn_ring_end_use, 1646 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1647 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1648 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1649 .reset = vcn_v4_0_3_ring_reset, 1650 }; 1651 1652 /** 1653 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1654 * 1655 * @adev: amdgpu_device pointer 1656 * 1657 * Set unified ring functions 1658 */ 1659 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1660 { 1661 int i, vcn_inst; 1662 1663 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1664 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1665 adev->vcn.inst[i].ring_enc[0].me = i; 1666 vcn_inst = GET_INST(VCN, i); 1667 adev->vcn.inst[i].aid_id = 1668 vcn_inst / adev->vcn.num_inst_per_aid; 1669 } 1670 } 1671 1672 /** 1673 * vcn_v4_0_3_is_idle - check VCN block is idle 1674 * 1675 * @ip_block: Pointer to the amdgpu_ip_block structure 1676 * 1677 * Check whether VCN block is idle 1678 */ 1679 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1680 { 1681 struct amdgpu_device *adev = ip_block->adev; 1682 int i, ret = 1; 1683 1684 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1685 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1686 UVD_STATUS__IDLE); 1687 } 1688 1689 return ret; 1690 } 1691 1692 /** 1693 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1694 * 1695 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1696 * 1697 * Wait for VCN block idle 1698 */ 1699 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1700 { 1701 struct amdgpu_device *adev = ip_block->adev; 1702 int i, ret = 0; 1703 1704 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1705 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1706 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1707 if (ret) 1708 return ret; 1709 } 1710 1711 return ret; 1712 } 1713 1714 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1715 * 1716 * @ip_block: amdgpu_ip_block pointer 1717 * @state: clock gating state 1718 * 1719 * Set VCN block clockgating state 1720 */ 1721 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1722 enum amd_clockgating_state state) 1723 { 1724 struct amdgpu_device *adev = ip_block->adev; 1725 bool enable = state == AMD_CG_STATE_GATE; 1726 int i; 1727 1728 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1729 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1730 1731 if (enable) { 1732 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1733 regUVD_STATUS) != UVD_STATUS__IDLE) 1734 return -EBUSY; 1735 vcn_v4_0_3_enable_clock_gating(vinst); 1736 } else { 1737 vcn_v4_0_3_disable_clock_gating(vinst); 1738 } 1739 } 1740 return 0; 1741 } 1742 1743 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1744 enum amd_powergating_state state) 1745 { 1746 struct amdgpu_device *adev = vinst->adev; 1747 int ret = 0; 1748 1749 /* for SRIOV, guest should not control VCN Power-gating 1750 * MMSCH FW should control Power-gating and clock-gating 1751 * guest should avoid touching CGC and PG 1752 */ 1753 if (amdgpu_sriov_vf(adev)) { 1754 vinst->cur_state = AMD_PG_STATE_UNGATE; 1755 return 0; 1756 } 1757 1758 if (state == vinst->cur_state) 1759 return 0; 1760 1761 if (state == AMD_PG_STATE_GATE) 1762 ret = vcn_v4_0_3_stop(vinst); 1763 else 1764 ret = vcn_v4_0_3_start(vinst); 1765 1766 if (!ret) 1767 vinst->cur_state = state; 1768 1769 return ret; 1770 } 1771 1772 /** 1773 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1774 * 1775 * @adev: amdgpu_device pointer 1776 * @source: interrupt sources 1777 * @type: interrupt types 1778 * @state: interrupt states 1779 * 1780 * Set VCN block interrupt state 1781 */ 1782 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1783 struct amdgpu_irq_src *source, 1784 unsigned int type, 1785 enum amdgpu_interrupt_state state) 1786 { 1787 return 0; 1788 } 1789 1790 /** 1791 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1792 * 1793 * @adev: amdgpu_device pointer 1794 * @source: interrupt sources 1795 * @entry: interrupt entry from clients and sources 1796 * 1797 * Process VCN block interrupt 1798 */ 1799 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1800 struct amdgpu_irq_src *source, 1801 struct amdgpu_iv_entry *entry) 1802 { 1803 uint32_t i, inst; 1804 1805 i = node_id_to_phys_map[entry->node_id]; 1806 1807 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1808 1809 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1810 if (adev->vcn.inst[inst].aid_id == i) 1811 break; 1812 1813 if (inst >= adev->vcn.num_vcn_inst) { 1814 dev_WARN_ONCE(adev->dev, 1, 1815 "Interrupt received for unknown VCN instance %d", 1816 entry->node_id); 1817 return 0; 1818 } 1819 1820 switch (entry->src_id) { 1821 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1822 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1823 break; 1824 default: 1825 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1826 entry->src_id, entry->src_data[0]); 1827 break; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1834 struct amdgpu_irq_src *source, 1835 unsigned int type, 1836 enum amdgpu_interrupt_state state) 1837 { 1838 return 0; 1839 } 1840 1841 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1842 .set = vcn_v4_0_3_set_interrupt_state, 1843 .process = vcn_v4_0_3_process_interrupt, 1844 }; 1845 1846 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = { 1847 .set = vcn_v4_0_3_set_ras_interrupt_state, 1848 .process = amdgpu_vcn_process_poison_irq, 1849 }; 1850 1851 /** 1852 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1853 * 1854 * @adev: amdgpu_device pointer 1855 * 1856 * Set VCN block interrupt irq functions 1857 */ 1858 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1859 { 1860 int i; 1861 1862 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1863 adev->vcn.inst->irq.num_types++; 1864 } 1865 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1866 1867 adev->vcn.inst->ras_poison_irq.num_types = 1; 1868 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; 1869 } 1870 1871 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1872 .name = "vcn_v4_0_3", 1873 .early_init = vcn_v4_0_3_early_init, 1874 .sw_init = vcn_v4_0_3_sw_init, 1875 .sw_fini = vcn_v4_0_3_sw_fini, 1876 .hw_init = vcn_v4_0_3_hw_init, 1877 .hw_fini = vcn_v4_0_3_hw_fini, 1878 .suspend = vcn_v4_0_3_suspend, 1879 .resume = vcn_v4_0_3_resume, 1880 .is_idle = vcn_v4_0_3_is_idle, 1881 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1882 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1883 .set_powergating_state = vcn_set_powergating_state, 1884 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1885 .print_ip_state = amdgpu_vcn_print_ip_state, 1886 }; 1887 1888 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1889 .type = AMD_IP_BLOCK_TYPE_VCN, 1890 .major = 4, 1891 .minor = 0, 1892 .rev = 3, 1893 .funcs = &vcn_v4_0_3_ip_funcs, 1894 }; 1895 1896 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1897 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1898 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1899 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1900 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1901 }; 1902 1903 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1904 uint32_t vcn_inst, 1905 void *ras_err_status) 1906 { 1907 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1908 1909 /* vcn v4_0_3 only support query uncorrectable errors */ 1910 amdgpu_ras_inst_query_ras_error_count(adev, 1911 vcn_v4_0_3_ue_reg_list, 1912 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1913 NULL, 0, GET_INST(VCN, vcn_inst), 1914 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1915 &err_data->ue_count); 1916 } 1917 1918 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1919 void *ras_err_status) 1920 { 1921 uint32_t i; 1922 1923 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1924 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1925 return; 1926 } 1927 1928 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1929 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1930 } 1931 1932 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1933 uint32_t vcn_inst) 1934 { 1935 amdgpu_ras_inst_reset_ras_error_count(adev, 1936 vcn_v4_0_3_ue_reg_list, 1937 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1938 GET_INST(VCN, vcn_inst)); 1939 } 1940 1941 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1942 { 1943 uint32_t i; 1944 1945 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1946 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1947 return; 1948 } 1949 1950 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1951 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1952 } 1953 1954 static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1955 uint32_t instance, uint32_t sub_block) 1956 { 1957 uint32_t poison_stat = 0, reg_value = 0; 1958 1959 switch (sub_block) { 1960 case AMDGPU_VCN_V4_0_3_VCPU_VCODEC: 1961 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1962 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1963 break; 1964 default: 1965 break; 1966 } 1967 1968 if (poison_stat) 1969 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1970 instance, sub_block); 1971 1972 return poison_stat; 1973 } 1974 1975 static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev) 1976 { 1977 uint32_t inst, sub; 1978 uint32_t poison_stat = 0; 1979 1980 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1981 for (sub = 0; sub < AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++) 1982 poison_stat += 1983 vcn_v4_0_3_query_poison_by_instance(adev, inst, sub); 1984 1985 return !!poison_stat; 1986 } 1987 1988 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1989 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1990 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1991 .query_poison_status = vcn_v4_0_3_query_poison_status, 1992 }; 1993 1994 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1995 enum aca_smu_type type, void *data) 1996 { 1997 struct aca_bank_info info; 1998 u64 misc0; 1999 int ret; 2000 2001 ret = aca_bank_info_decode(bank, &info); 2002 if (ret) 2003 return ret; 2004 2005 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2006 switch (type) { 2007 case ACA_SMU_TYPE_UE: 2008 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2009 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2010 1ULL); 2011 break; 2012 case ACA_SMU_TYPE_CE: 2013 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2014 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2015 ACA_REG__MISC0__ERRCNT(misc0)); 2016 break; 2017 default: 2018 return -EINVAL; 2019 } 2020 2021 return ret; 2022 } 2023 2024 /* reference to smu driver if header file */ 2025 static int vcn_v4_0_3_err_codes[] = { 2026 14, 15, /* VCN */ 2027 }; 2028 2029 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2030 enum aca_smu_type type, void *data) 2031 { 2032 u32 instlo; 2033 2034 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2035 instlo &= GENMASK(31, 1); 2036 2037 if (instlo != mmSMNAID_AID0_MCA_SMU) 2038 return false; 2039 2040 if (aca_bank_check_error_codes(handle->adev, bank, 2041 vcn_v4_0_3_err_codes, 2042 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 2043 return false; 2044 2045 return true; 2046 } 2047 2048 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2049 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2050 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2051 }; 2052 2053 static const struct aca_info vcn_v4_0_3_aca_info = { 2054 .hwip = ACA_HWIP_TYPE_SMU, 2055 .mask = ACA_ERROR_UE_MASK, 2056 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2057 }; 2058 2059 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2060 { 2061 int r; 2062 2063 r = amdgpu_ras_block_late_init(adev, ras_block); 2064 if (r) 2065 return r; 2066 2067 if (amdgpu_ras_is_supported(adev, ras_block->block) && 2068 adev->vcn.inst->ras_poison_irq.funcs) { 2069 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 2070 if (r) 2071 goto late_fini; 2072 } 2073 2074 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2075 &vcn_v4_0_3_aca_info, NULL); 2076 if (r) 2077 goto late_fini; 2078 2079 return 0; 2080 2081 late_fini: 2082 amdgpu_ras_block_late_fini(adev, ras_block); 2083 2084 return r; 2085 } 2086 2087 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2088 .ras_block = { 2089 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2090 .ras_late_init = vcn_v4_0_3_ras_late_init, 2091 }, 2092 }; 2093 2094 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2095 { 2096 adev->vcn.ras = &vcn_v4_0_3_ras; 2097 } 2098 2099 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2100 int inst_idx, bool indirect) 2101 { 2102 uint32_t tmp; 2103 2104 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2105 return; 2106 2107 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2108 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2109 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2110 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2111 WREG32_SOC15_DPG_MODE(inst_idx, 2112 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2113 tmp, 0, indirect); 2114 2115 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2116 WREG32_SOC15_DPG_MODE(inst_idx, 2117 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2118 tmp, 0, indirect); 2119 2120 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2121 WREG32_SOC15_DPG_MODE(inst_idx, 2122 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2123 tmp, 0, indirect); 2124 } 2125