1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 switch (amdgpu_user_queue) { 119 case -1: 120 case 0: 121 default: 122 adev->vcn.disable_kq = false; 123 adev->vcn.disable_uq = true; 124 break; 125 case 2: 126 adev->vcn.disable_kq = true; 127 adev->vcn.disable_uq = true; 128 break; 129 } 130 131 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 132 /* re-use enc ring as unified ring */ 133 adev->vcn.inst[i].num_enc_rings = 1; 134 135 vcn_v4_0_3_set_unified_ring_funcs(adev); 136 vcn_v4_0_3_set_irq_funcs(adev); 137 vcn_v4_0_3_set_ras_funcs(adev); 138 139 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 140 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 141 142 r = amdgpu_vcn_early_init(adev, i); 143 if (r) 144 return r; 145 } 146 147 return 0; 148 } 149 150 static bool vcn_v4_0_3_is_psp_fw_reset_supported(struct amdgpu_device *adev) 151 { 152 uint32_t fw_ver = adev->psp.sos.fw_version; 153 uint32_t pgm = (fw_ver >> 8) & 0xFF; 154 155 /* 156 * FWDEV-159155: PSP SOS FW must be >= 0x0036015f for program 0x01 157 * before enabling VCN per-queue reset. 158 */ 159 if (pgm == 1) 160 return fw_ver >= 0x0036015f; 161 162 return true; 163 } 164 165 static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) 166 { 167 struct amdgpu_device *adev = ip_block->adev; 168 169 adev->vcn.supported_reset = 170 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 171 172 if (amdgpu_dpm_reset_vcn_is_supported(adev) && 173 vcn_v4_0_3_is_psp_fw_reset_supported(adev) && 174 !amdgpu_sriov_vf(adev)) 175 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 176 177 return 0; 178 } 179 180 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 181 { 182 struct amdgpu_vcn4_fw_shared *fw_shared; 183 184 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 185 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 186 fw_shared->sq.is_enabled = 1; 187 188 if (amdgpu_vcnfw_log) 189 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 190 191 return 0; 192 } 193 194 /** 195 * vcn_v4_0_3_sw_init - sw init for VCN block 196 * 197 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 198 * 199 * Load firmware and sw initialization 200 */ 201 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 202 { 203 struct amdgpu_device *adev = ip_block->adev; 204 struct amdgpu_ring *ring; 205 int i, r, vcn_inst; 206 207 /* VCN DEC TRAP */ 208 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 209 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 210 if (r) 211 return r; 212 213 /* VCN POISON TRAP */ 214 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 215 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 216 217 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 218 219 r = amdgpu_vcn_sw_init(adev, i); 220 if (r) 221 return r; 222 223 amdgpu_vcn_setup_ucode(adev, i); 224 225 r = amdgpu_vcn_resume(adev, i); 226 if (r) 227 return r; 228 229 vcn_inst = GET_INST(VCN, i); 230 231 ring = &adev->vcn.inst[i].ring_enc[0]; 232 ring->use_doorbell = true; 233 if (adev->vcn.disable_kq) { 234 ring->no_scheduler = true; 235 ring->no_user_submission = true; 236 } 237 238 if (!amdgpu_sriov_vf(adev)) 239 ring->doorbell_index = 240 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 241 9 * vcn_inst; 242 else 243 ring->doorbell_index = 244 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 245 32 * vcn_inst; 246 247 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 248 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 249 250 /* There are no per-instance irq source IDs on 4.0.3, the IH 251 * packets use a separate field to differentiate instances. 252 */ 253 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[0].irq, 0, 254 AMDGPU_RING_PRIO_DEFAULT, 255 &adev->vcn.inst[i].sched_score); 256 if (r) 257 return r; 258 259 vcn_v4_0_3_fw_shared_init(adev, i); 260 261 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 262 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 263 } 264 265 if (amdgpu_sriov_vf(adev)) { 266 r = amdgpu_virt_alloc_mm_table(adev); 267 if (r) 268 return r; 269 } 270 271 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 272 r = amdgpu_vcn_ras_sw_init(adev); 273 if (r) { 274 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 275 return r; 276 } 277 } 278 279 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3)); 280 if (r) 281 return r; 282 283 return amdgpu_vcn_sysfs_reset_mask_init(adev); 284 } 285 286 /** 287 * vcn_v4_0_3_sw_fini - sw fini for VCN block 288 * 289 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 290 * 291 * VCN suspend and free up sw allocation 292 */ 293 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 294 { 295 struct amdgpu_device *adev = ip_block->adev; 296 int i, r, idx; 297 298 if (drm_dev_enter(&adev->ddev, &idx)) { 299 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 300 struct amdgpu_vcn4_fw_shared *fw_shared; 301 302 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 303 fw_shared->present_flag_0 = 0; 304 fw_shared->sq.is_enabled = cpu_to_le32(false); 305 } 306 drm_dev_exit(idx); 307 } 308 309 if (amdgpu_sriov_vf(adev)) 310 amdgpu_virt_free_mm_table(adev); 311 312 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 313 r = amdgpu_vcn_suspend(adev, i); 314 if (r) 315 return r; 316 } 317 318 amdgpu_vcn_sysfs_reset_mask_fini(adev); 319 320 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 321 amdgpu_vcn_sw_fini(adev, i); 322 323 return 0; 324 } 325 326 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 327 { 328 int vcn_inst; 329 struct amdgpu_device *adev = vinst->adev; 330 struct amdgpu_ring *ring; 331 int inst_idx = vinst->inst; 332 333 vcn_inst = GET_INST(VCN, inst_idx); 334 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 335 if (ring->use_doorbell) { 336 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 337 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 338 adev->vcn.inst[inst_idx].aid_id); 339 340 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 341 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 342 VCN_RB1_DB_CTRL__EN_MASK); 343 344 /* Read DB_CTRL to flush the write DB_CTRL command. */ 345 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 346 } 347 348 return 0; 349 } 350 351 /** 352 * vcn_v4_0_3_hw_init - start and test VCN block 353 * 354 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 355 * 356 * Initialize the hardware, boot up the VCPU and do some testing 357 */ 358 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 359 { 360 struct amdgpu_device *adev = ip_block->adev; 361 struct amdgpu_ring *ring; 362 struct amdgpu_vcn_inst *vinst; 363 int i, r; 364 365 if (amdgpu_sriov_vf(adev)) { 366 r = vcn_v4_0_3_start_sriov(adev); 367 if (r) 368 return r; 369 370 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 371 ring = &adev->vcn.inst[i].ring_enc[0]; 372 ring->wptr = 0; 373 ring->wptr_old = 0; 374 vcn_v4_0_3_unified_ring_set_wptr(ring); 375 ring->sched.ready = true; 376 } 377 } else { 378 /* This flag is not set for VF, assumed to be disabled always */ 379 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 380 0x100) 381 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 382 383 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 384 struct amdgpu_vcn4_fw_shared *fw_shared; 385 386 ring = &adev->vcn.inst[i].ring_enc[0]; 387 vinst = &adev->vcn.inst[i]; 388 vcn_v4_0_3_hw_init_inst(vinst); 389 390 /* Re-init fw_shared when RAS fatal error occurred */ 391 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 392 if (!fw_shared->sq.is_enabled) 393 vcn_v4_0_3_fw_shared_init(adev, i); 394 395 r = amdgpu_ring_test_helper(ring); 396 if (r) 397 return r; 398 } 399 } 400 401 return r; 402 } 403 404 /** 405 * vcn_v4_0_3_hw_fini - stop the hardware block 406 * 407 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 408 * 409 * Stop the VCN block, mark ring as not ready any more 410 */ 411 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 412 { 413 struct amdgpu_device *adev = ip_block->adev; 414 int i; 415 416 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 417 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 418 419 cancel_delayed_work_sync(&vinst->idle_work); 420 421 if (vinst->cur_state != AMD_PG_STATE_GATE) 422 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 423 } 424 425 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) 426 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 427 428 return 0; 429 } 430 431 /** 432 * vcn_v4_0_3_suspend - suspend VCN block 433 * 434 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 435 * 436 * HW fini and suspend VCN block 437 */ 438 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 439 { 440 struct amdgpu_device *adev = ip_block->adev; 441 int r, i; 442 443 r = vcn_v4_0_3_hw_fini(ip_block); 444 if (r) 445 return r; 446 447 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 448 r = amdgpu_vcn_suspend(adev, i); 449 if (r) 450 return r; 451 } 452 453 return 0; 454 } 455 456 /** 457 * vcn_v4_0_3_resume - resume VCN block 458 * 459 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 460 * 461 * Resume firmware and hw init VCN block 462 */ 463 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 464 { 465 struct amdgpu_device *adev = ip_block->adev; 466 int r, i; 467 468 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 469 r = amdgpu_vcn_resume(ip_block->adev, i); 470 if (r) 471 return r; 472 } 473 474 r = vcn_v4_0_3_hw_init(ip_block); 475 476 return r; 477 } 478 479 /** 480 * vcn_v4_0_3_mc_resume - memory controller programming 481 * 482 * @vinst: VCN instance 483 * 484 * Let the VCN memory controller know it's offsets 485 */ 486 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 487 { 488 struct amdgpu_device *adev = vinst->adev; 489 int inst_idx = vinst->inst; 490 uint32_t offset, size, vcn_inst; 491 const struct common_firmware_header *hdr; 492 493 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 494 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 495 496 vcn_inst = GET_INST(VCN, inst_idx); 497 /* cache window 0: fw */ 498 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 499 WREG32_SOC15( 500 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 501 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 502 .tmr_mc_addr_lo)); 503 WREG32_SOC15( 504 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 505 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 506 .tmr_mc_addr_hi)); 507 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 508 offset = 0; 509 } else { 510 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 511 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 512 WREG32_SOC15(VCN, vcn_inst, 513 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 514 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 515 offset = size; 516 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 517 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 518 } 519 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 520 521 /* cache window 1: stack */ 522 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 523 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 524 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 525 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 526 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 527 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 528 AMDGPU_VCN_STACK_SIZE); 529 530 /* cache window 2: context */ 531 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 532 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 533 AMDGPU_VCN_STACK_SIZE)); 534 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 535 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 536 AMDGPU_VCN_STACK_SIZE)); 537 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 538 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 539 AMDGPU_VCN_CONTEXT_SIZE); 540 541 /* non-cache window */ 542 WREG32_SOC15( 543 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 544 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 545 WREG32_SOC15( 546 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 547 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 548 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 549 WREG32_SOC15( 550 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 551 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 552 } 553 554 /** 555 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 556 * 557 * @vinst: VCN instance 558 * @indirect: indirectly write sram 559 * 560 * Let the VCN memory controller know it's offsets with dpg mode 561 */ 562 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 563 bool indirect) 564 { 565 struct amdgpu_device *adev = vinst->adev; 566 int inst_idx = vinst->inst; 567 uint32_t offset, size; 568 const struct common_firmware_header *hdr; 569 570 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 571 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 572 573 /* cache window 0: fw */ 574 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 575 if (!indirect) { 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 578 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 579 inst_idx].tmr_mc_addr_lo), 0, indirect); 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 582 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 583 inst_idx].tmr_mc_addr_hi), 0, indirect); 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 586 } else { 587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 588 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 590 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 593 } 594 offset = 0; 595 } else { 596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 597 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 598 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 600 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 601 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 602 offset = size; 603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 604 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 605 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 606 } 607 608 if (!indirect) 609 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 610 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 611 else 612 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 613 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 614 615 /* cache window 1: stack */ 616 if (!indirect) { 617 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 618 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 619 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 620 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 621 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 622 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 623 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 624 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 625 } else { 626 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 627 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 629 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 630 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 631 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 632 } 633 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 634 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 635 636 /* cache window 2: context */ 637 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 638 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 639 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 640 AMDGPU_VCN_STACK_SIZE), 0, indirect); 641 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 642 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 643 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 644 AMDGPU_VCN_STACK_SIZE), 0, indirect); 645 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 646 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 647 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 648 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 649 650 /* non-cache window */ 651 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 652 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 653 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 654 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 655 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 656 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 657 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 658 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 659 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 660 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 661 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 662 663 /* VCN global tiling registers */ 664 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 665 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 666 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 667 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 668 } 669 670 /** 671 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 672 * 673 * @vinst: VCN instance 674 * 675 * Disable clock gating for VCN block 676 */ 677 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 678 { 679 struct amdgpu_device *adev = vinst->adev; 680 int inst_idx = vinst->inst; 681 uint32_t data; 682 int vcn_inst; 683 684 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 685 return; 686 687 vcn_inst = GET_INST(VCN, inst_idx); 688 689 /* VCN disable CGC */ 690 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 691 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 692 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 693 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 694 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 695 696 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 697 data &= ~(UVD_CGC_GATE__SYS_MASK 698 | UVD_CGC_GATE__MPEG2_MASK 699 | UVD_CGC_GATE__REGS_MASK 700 | UVD_CGC_GATE__RBC_MASK 701 | UVD_CGC_GATE__LMI_MC_MASK 702 | UVD_CGC_GATE__LMI_UMC_MASK 703 | UVD_CGC_GATE__MPC_MASK 704 | UVD_CGC_GATE__LBSI_MASK 705 | UVD_CGC_GATE__LRBBM_MASK 706 | UVD_CGC_GATE__WCB_MASK 707 | UVD_CGC_GATE__VCPU_MASK 708 | UVD_CGC_GATE__MMSCH_MASK); 709 710 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 711 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 712 713 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 714 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 715 | UVD_CGC_CTRL__MPEG2_MODE_MASK 716 | UVD_CGC_CTRL__REGS_MODE_MASK 717 | UVD_CGC_CTRL__RBC_MODE_MASK 718 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 719 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 720 | UVD_CGC_CTRL__MPC_MODE_MASK 721 | UVD_CGC_CTRL__LBSI_MODE_MASK 722 | UVD_CGC_CTRL__LRBBM_MODE_MASK 723 | UVD_CGC_CTRL__WCB_MODE_MASK 724 | UVD_CGC_CTRL__VCPU_MODE_MASK 725 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 726 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 727 728 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 729 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 730 | UVD_SUVD_CGC_GATE__SIT_MASK 731 | UVD_SUVD_CGC_GATE__SMP_MASK 732 | UVD_SUVD_CGC_GATE__SCM_MASK 733 | UVD_SUVD_CGC_GATE__SDB_MASK 734 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 735 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 736 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 737 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 738 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 739 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 740 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 741 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 742 | UVD_SUVD_CGC_GATE__ENT_MASK 743 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 744 | UVD_SUVD_CGC_GATE__SITE_MASK 745 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 746 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 747 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 748 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 749 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 750 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 751 752 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 753 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 754 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 755 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 756 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 761 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 762 } 763 764 /** 765 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 766 * 767 * @vinst: VCN instance 768 * @sram_sel: sram select 769 * @indirect: indirectly write sram 770 * 771 * Disable clock gating for VCN block with dpg mode 772 */ 773 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 774 uint8_t sram_sel, 775 uint8_t indirect) 776 { 777 struct amdgpu_device *adev = vinst->adev; 778 int inst_idx = vinst->inst; 779 uint32_t reg_data = 0; 780 781 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 782 return; 783 784 /* enable sw clock gating control */ 785 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 786 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 787 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 788 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 789 UVD_CGC_CTRL__MPEG2_MODE_MASK | 790 UVD_CGC_CTRL__REGS_MODE_MASK | 791 UVD_CGC_CTRL__RBC_MODE_MASK | 792 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 793 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 794 UVD_CGC_CTRL__IDCT_MODE_MASK | 795 UVD_CGC_CTRL__MPRD_MODE_MASK | 796 UVD_CGC_CTRL__MPC_MODE_MASK | 797 UVD_CGC_CTRL__LBSI_MODE_MASK | 798 UVD_CGC_CTRL__LRBBM_MODE_MASK | 799 UVD_CGC_CTRL__WCB_MODE_MASK | 800 UVD_CGC_CTRL__VCPU_MODE_MASK); 801 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 802 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 803 804 /* turn off clock gating */ 805 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 806 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 807 808 /* turn on SUVD clock gating */ 809 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 810 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 811 812 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 813 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 814 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 815 } 816 817 /** 818 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 819 * 820 * @vinst: VCN instance 821 * 822 * Enable clock gating for VCN block 823 */ 824 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 825 { 826 struct amdgpu_device *adev = vinst->adev; 827 int inst_idx = vinst->inst; 828 uint32_t data; 829 int vcn_inst; 830 831 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 832 return; 833 834 vcn_inst = GET_INST(VCN, inst_idx); 835 836 /* enable VCN CGC */ 837 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 838 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 839 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 840 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 841 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 842 843 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 844 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 845 | UVD_CGC_CTRL__MPEG2_MODE_MASK 846 | UVD_CGC_CTRL__REGS_MODE_MASK 847 | UVD_CGC_CTRL__RBC_MODE_MASK 848 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 849 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 850 | UVD_CGC_CTRL__MPC_MODE_MASK 851 | UVD_CGC_CTRL__LBSI_MODE_MASK 852 | UVD_CGC_CTRL__LRBBM_MODE_MASK 853 | UVD_CGC_CTRL__WCB_MODE_MASK 854 | UVD_CGC_CTRL__VCPU_MODE_MASK); 855 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 856 857 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 858 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 859 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 860 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 861 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 862 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 863 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 864 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 865 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 866 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 867 } 868 869 /** 870 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 871 * 872 * @vinst: VCN instance 873 * @indirect: indirectly write sram 874 * 875 * Start VCN block with dpg mode 876 */ 877 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 878 bool indirect) 879 { 880 struct amdgpu_device *adev = vinst->adev; 881 int inst_idx = vinst->inst; 882 struct amdgpu_vcn4_fw_shared *fw_shared = 883 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 884 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; 885 struct amdgpu_ring *ring; 886 int vcn_inst, ret; 887 uint32_t tmp; 888 889 vcn_inst = GET_INST(VCN, inst_idx); 890 /* disable register anti-hang mechanism */ 891 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 892 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 893 /* enable dynamic power gating mode */ 894 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 895 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 896 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 897 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 898 899 if (indirect) { 900 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 901 inst_idx, adev->vcn.inst[inst_idx].aid_id); 902 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 903 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 904 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 905 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 906 adev->vcn.inst[inst_idx].aid_id, 0, true); 907 } 908 909 /* enable clock gating */ 910 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 911 912 /* enable VCPU clock */ 913 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 914 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 915 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 916 917 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 918 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 919 920 /* disable master interrupt */ 921 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 922 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 923 924 /* setup regUVD_LMI_CTRL */ 925 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 926 UVD_LMI_CTRL__REQ_MODE_MASK | 927 UVD_LMI_CTRL__CRC_RESET_MASK | 928 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 929 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 930 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 931 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 932 0x00100000L); 933 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 934 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 935 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, 0, regUVD_MPC_CNTL), 938 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 939 940 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 941 VCN, 0, regUVD_MPC_SET_MUXA0), 942 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 943 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 944 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 945 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 946 947 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 948 VCN, 0, regUVD_MPC_SET_MUXB0), 949 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 950 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 951 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 952 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 953 954 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 955 VCN, 0, regUVD_MPC_SET_MUX), 956 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 957 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 958 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 959 960 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 961 962 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 963 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 966 967 /* enable LMI MC and UMC channels */ 968 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 969 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 970 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 971 972 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 973 974 /* enable master interrupt */ 975 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 976 VCN, 0, regUVD_MASTINT_EN), 977 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 978 979 if (indirect) { 980 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 981 if (ret) { 982 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 983 return ret; 984 } 985 } 986 987 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 988 989 /* Pause dpg */ 990 vcn_v4_0_3_pause_dpg_mode(vinst, &state); 991 992 /* program the RB_BASE for ring buffer */ 993 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 994 lower_32_bits(ring->gpu_addr)); 995 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 996 upper_32_bits(ring->gpu_addr)); 997 998 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 999 ring->ring_size / sizeof(uint32_t)); 1000 1001 /* resetting ring, fw should not check RB ring */ 1002 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1003 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1004 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1005 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1006 1007 /* Initialize the ring buffer's read and write pointers */ 1008 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1009 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1010 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1011 1012 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1013 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1014 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1015 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1016 1017 /*resetting done, fw can check RB ring */ 1018 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1019 1020 /* Keeping one read-back to ensure all register writes are done, 1021 * otherwise it may introduce race conditions. 1022 */ 1023 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1024 1025 return 0; 1026 } 1027 1028 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 1029 { 1030 int i, vcn_inst; 1031 struct amdgpu_ring *ring_enc; 1032 uint64_t cache_addr; 1033 uint64_t rb_enc_addr; 1034 uint64_t ctx_addr; 1035 uint32_t param, resp, expected; 1036 uint32_t offset, cache_size; 1037 uint32_t tmp, timeout; 1038 1039 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1040 uint32_t *table_loc; 1041 uint32_t table_size; 1042 uint32_t size, size_dw; 1043 uint32_t init_status; 1044 uint32_t enabled_vcn; 1045 1046 struct mmsch_v4_0_cmd_direct_write 1047 direct_wt = { {0} }; 1048 struct mmsch_v4_0_cmd_direct_read_modify_write 1049 direct_rd_mod_wt = { {0} }; 1050 struct mmsch_v4_0_cmd_end end = { {0} }; 1051 struct mmsch_v4_0_3_init_header header; 1052 1053 struct amdgpu_vcn4_fw_shared *fw_shared; 1054 struct amdgpu_fw_shared_rb_setup *rb_setup; 1055 1056 direct_wt.cmd_header.command_type = 1057 MMSCH_COMMAND__DIRECT_REG_WRITE; 1058 direct_rd_mod_wt.cmd_header.command_type = 1059 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1060 end.cmd_header.command_type = MMSCH_COMMAND__END; 1061 1062 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1063 vcn_inst = GET_INST(VCN, i); 1064 1065 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1066 1067 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1068 header.version = MMSCH_VERSION; 1069 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1070 1071 table_loc = (uint32_t *)table->cpu_addr; 1072 table_loc += header.total_size; 1073 1074 table_size = 0; 1075 1076 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1077 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1078 1079 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1080 1081 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1082 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1083 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1084 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1085 1086 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1087 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1088 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1089 1090 offset = 0; 1091 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1092 regUVD_VCPU_CACHE_OFFSET0), 0); 1093 } else { 1094 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1095 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1096 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1097 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1098 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1099 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1100 offset = cache_size; 1101 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1102 regUVD_VCPU_CACHE_OFFSET0), 1103 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1104 } 1105 1106 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1107 regUVD_VCPU_CACHE_SIZE0), 1108 cache_size); 1109 1110 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1111 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1112 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1113 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1114 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1115 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1116 regUVD_VCPU_CACHE_OFFSET1), 0); 1117 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1118 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1119 1120 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1121 AMDGPU_VCN_STACK_SIZE; 1122 1123 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1124 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1125 1126 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1127 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1128 1129 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1130 regUVD_VCPU_CACHE_OFFSET2), 0); 1131 1132 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1133 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1134 1135 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1136 rb_setup = &fw_shared->rb_setup; 1137 1138 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1139 ring_enc->wptr = 0; 1140 rb_enc_addr = ring_enc->gpu_addr; 1141 1142 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1143 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1144 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1145 rb_setup->rb_size = ring_enc->ring_size / 4; 1146 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1147 1148 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1149 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1150 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1151 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1152 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1153 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1154 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1155 regUVD_VCPU_NONCACHE_SIZE0), 1156 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1157 MMSCH_V4_0_INSERT_END(); 1158 1159 header.vcn0.init_status = 0; 1160 header.vcn0.table_offset = header.total_size; 1161 header.vcn0.table_size = table_size; 1162 header.total_size += table_size; 1163 1164 /* Send init table to mmsch */ 1165 size = sizeof(struct mmsch_v4_0_3_init_header); 1166 table_loc = (uint32_t *)table->cpu_addr; 1167 memcpy((void *)table_loc, &header, size); 1168 1169 ctx_addr = table->gpu_addr; 1170 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1171 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1172 1173 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1174 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1175 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1176 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1177 1178 size = header.total_size; 1179 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1180 1181 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1182 1183 param = 0x00000001; 1184 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1185 tmp = 0; 1186 timeout = 1000; 1187 resp = 0; 1188 expected = MMSCH_VF_MAILBOX_RESP__OK; 1189 while (resp != expected) { 1190 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1191 if (resp != 0) 1192 break; 1193 1194 udelay(10); 1195 tmp = tmp + 10; 1196 if (tmp >= timeout) { 1197 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1198 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1199 "(expected=0x%08x, readback=0x%08x)\n", 1200 tmp, expected, resp); 1201 return -EBUSY; 1202 } 1203 } 1204 1205 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1206 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1207 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1208 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1209 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1210 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1211 } 1212 } 1213 1214 return 0; 1215 } 1216 1217 /** 1218 * vcn_v4_0_3_start - VCN start 1219 * 1220 * @vinst: VCN instance 1221 * 1222 * Start VCN block 1223 */ 1224 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1225 { 1226 struct amdgpu_device *adev = vinst->adev; 1227 int i = vinst->inst; 1228 struct amdgpu_vcn4_fw_shared *fw_shared; 1229 struct amdgpu_ring *ring; 1230 int j, k, r, vcn_inst; 1231 uint32_t tmp; 1232 1233 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1234 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1235 1236 vcn_inst = GET_INST(VCN, i); 1237 /* set VCN status busy */ 1238 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1239 UVD_STATUS__UVD_BUSY; 1240 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1241 1242 /* SW clock gating */ 1243 vcn_v4_0_3_disable_clock_gating(vinst); 1244 1245 /* enable VCPU clock */ 1246 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1247 UVD_VCPU_CNTL__CLK_EN_MASK, 1248 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1249 1250 /* disable master interrupt */ 1251 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1252 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1253 1254 /* enable LMI MC and UMC channels */ 1255 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1256 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1257 1258 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1259 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1260 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1261 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1262 1263 /* setup regUVD_LMI_CTRL */ 1264 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1265 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1266 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1267 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1268 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1269 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1270 1271 /* setup regUVD_MPC_CNTL */ 1272 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1273 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1274 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1275 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1276 1277 /* setup UVD_MPC_SET_MUXA0 */ 1278 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1279 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1280 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1281 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1282 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1283 1284 /* setup UVD_MPC_SET_MUXB0 */ 1285 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1286 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1287 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1288 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1289 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1290 1291 /* setup UVD_MPC_SET_MUX */ 1292 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1293 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1294 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1295 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1296 1297 vcn_v4_0_3_mc_resume(vinst); 1298 1299 /* VCN global tiling registers */ 1300 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1301 adev->gfx.config.gb_addr_config); 1302 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1303 adev->gfx.config.gb_addr_config); 1304 1305 /* unblock VCPU register access */ 1306 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1307 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1308 1309 /* release VCPU reset to boot */ 1310 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1311 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1312 1313 for (j = 0; j < 10; ++j) { 1314 uint32_t status; 1315 1316 for (k = 0; k < 100; ++k) { 1317 status = RREG32_SOC15(VCN, vcn_inst, 1318 regUVD_STATUS); 1319 if (status & 2) 1320 break; 1321 mdelay(10); 1322 } 1323 r = 0; 1324 if (status & 2) 1325 break; 1326 1327 DRM_DEV_ERROR(adev->dev, 1328 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1329 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1330 regUVD_VCPU_CNTL), 1331 UVD_VCPU_CNTL__BLK_RST_MASK, 1332 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1333 mdelay(10); 1334 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1335 regUVD_VCPU_CNTL), 1336 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1337 1338 mdelay(10); 1339 r = -1; 1340 } 1341 1342 if (r) { 1343 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1344 return r; 1345 } 1346 1347 /* enable master interrupt */ 1348 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1349 UVD_MASTINT_EN__VCPU_EN_MASK, 1350 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1351 1352 /* clear the busy bit of VCN_STATUS */ 1353 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1354 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1355 1356 ring = &adev->vcn.inst[i].ring_enc[0]; 1357 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1358 1359 /* program the RB_BASE for ring buffer */ 1360 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1361 lower_32_bits(ring->gpu_addr)); 1362 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1363 upper_32_bits(ring->gpu_addr)); 1364 1365 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1366 ring->ring_size / sizeof(uint32_t)); 1367 1368 /* resetting ring, fw should not check RB ring */ 1369 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1370 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1371 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1372 1373 /* Initialize the ring buffer's read and write pointers */ 1374 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1375 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1376 1377 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1378 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1379 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1380 1381 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1382 fw_shared->sq.queue_mode &= 1383 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1384 1385 return 0; 1386 } 1387 1388 /** 1389 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1390 * 1391 * @vinst: VCN instance 1392 * 1393 * Stop VCN block with dpg mode 1394 */ 1395 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1396 { 1397 struct amdgpu_device *adev = vinst->adev; 1398 int inst_idx = vinst->inst; 1399 uint32_t tmp; 1400 int vcn_inst; 1401 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1402 1403 vcn_inst = GET_INST(VCN, inst_idx); 1404 1405 /* Unpause dpg */ 1406 vcn_v4_0_3_pause_dpg_mode(vinst, &state); 1407 1408 /* Wait for power status to be 1 */ 1409 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1410 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1411 1412 /* wait for read ptr to be equal to write ptr */ 1413 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1414 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1415 1416 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1417 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1418 1419 /* disable dynamic power gating mode */ 1420 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1421 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1422 1423 /* Keeping one read-back to ensure all register writes are done, 1424 * otherwise it may introduce race conditions. 1425 */ 1426 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1427 1428 return 0; 1429 } 1430 1431 /** 1432 * vcn_v4_0_3_stop - VCN stop 1433 * 1434 * @vinst: VCN instance 1435 * 1436 * Stop VCN block 1437 */ 1438 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1439 { 1440 struct amdgpu_device *adev = vinst->adev; 1441 int i = vinst->inst; 1442 struct amdgpu_vcn4_fw_shared *fw_shared; 1443 int r = 0, vcn_inst; 1444 uint32_t tmp; 1445 1446 vcn_inst = GET_INST(VCN, i); 1447 1448 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1449 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1450 1451 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1452 vcn_v4_0_3_stop_dpg_mode(vinst); 1453 goto Done; 1454 } 1455 1456 /* wait for vcn idle */ 1457 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1458 UVD_STATUS__IDLE, 0x7); 1459 if (r) 1460 goto Done; 1461 1462 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1463 UVD_LMI_STATUS__READ_CLEAN_MASK | 1464 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1465 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1466 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1467 tmp); 1468 if (r) 1469 goto Done; 1470 1471 /* stall UMC channel */ 1472 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1473 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1474 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1475 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1476 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1477 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1478 tmp); 1479 if (r) 1480 goto Done; 1481 1482 /* Unblock VCPU Register access */ 1483 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1484 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1485 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1486 1487 /* release VCPU reset to boot */ 1488 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1489 UVD_VCPU_CNTL__BLK_RST_MASK, 1490 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1491 1492 /* disable VCPU clock */ 1493 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1494 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1495 1496 /* reset LMI UMC/LMI/VCPU */ 1497 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1498 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1499 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1500 1501 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1502 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1503 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1504 1505 /* clear VCN status */ 1506 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1507 1508 /* apply HW clock gating */ 1509 vcn_v4_0_3_enable_clock_gating(vinst); 1510 1511 /* Keeping one read-back to ensure all register writes are done, 1512 * otherwise it may introduce race conditions. 1513 */ 1514 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1515 1516 Done: 1517 return 0; 1518 } 1519 1520 /** 1521 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1522 * 1523 * @vinst: VCN instance 1524 * @new_state: pause state 1525 * 1526 * Pause dpg mode for VCN block 1527 */ 1528 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1529 struct dpg_pause_state *new_state) 1530 { 1531 struct amdgpu_device *adev = vinst->adev; 1532 int inst_idx = vinst->inst; 1533 uint32_t reg_data = 0; 1534 int ret_code; 1535 1536 /* pause/unpause if state is changed */ 1537 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1538 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1539 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1540 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1541 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1542 1543 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1544 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1545 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1546 1547 if (!ret_code) { 1548 /* pause DPG */ 1549 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1550 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1551 1552 /* wait for ACK */ 1553 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1554 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1555 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1556 } 1557 } else { 1558 /* unpause dpg, no need to wait */ 1559 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1560 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1561 } 1562 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1563 } 1564 1565 return 0; 1566 } 1567 1568 /** 1569 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1570 * 1571 * @ring: amdgpu_ring pointer 1572 * 1573 * Returns the current hardware unified read pointer 1574 */ 1575 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1576 { 1577 struct amdgpu_device *adev = ring->adev; 1578 1579 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1580 DRM_ERROR("wrong ring id is identified in %s", __func__); 1581 1582 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1583 } 1584 1585 /** 1586 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1587 * 1588 * @ring: amdgpu_ring pointer 1589 * 1590 * Returns the current hardware unified write pointer 1591 */ 1592 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1593 { 1594 struct amdgpu_device *adev = ring->adev; 1595 1596 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1597 DRM_ERROR("wrong ring id is identified in %s", __func__); 1598 1599 if (ring->use_doorbell) 1600 return *ring->wptr_cpu_addr; 1601 else 1602 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1603 regUVD_RB_WPTR); 1604 } 1605 1606 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1607 uint32_t val, uint32_t mask) 1608 { 1609 /* Use normalized offsets when required */ 1610 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1611 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1612 1613 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1614 amdgpu_ring_write(ring, reg << 2); 1615 amdgpu_ring_write(ring, mask); 1616 amdgpu_ring_write(ring, val); 1617 } 1618 1619 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1620 uint32_t val) 1621 { 1622 /* Use normalized offsets when required */ 1623 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1624 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1625 1626 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1627 amdgpu_ring_write(ring, reg << 2); 1628 amdgpu_ring_write(ring, val); 1629 } 1630 1631 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1632 unsigned int vmid, uint64_t pd_addr) 1633 { 1634 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1635 1636 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1637 1638 /* wait for reg writes */ 1639 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1640 vmid * hub->ctx_addr_distance, 1641 lower_32_bits(pd_addr), 0xffffffff); 1642 } 1643 1644 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1645 { 1646 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1647 * This is a workaround to avoid any HDP flush through VCN ring. 1648 */ 1649 } 1650 1651 /** 1652 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1653 * 1654 * @ring: amdgpu_ring pointer 1655 * 1656 * Commits the enc write pointer to the hardware 1657 */ 1658 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1659 { 1660 struct amdgpu_device *adev = ring->adev; 1661 1662 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1663 DRM_ERROR("wrong ring id is identified in %s", __func__); 1664 1665 if (ring->use_doorbell) { 1666 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1667 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1668 } else { 1669 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1670 lower_32_bits(ring->wptr)); 1671 } 1672 } 1673 1674 static int vcn_v4_0_3_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst) 1675 { 1676 struct amdgpu_ring *ring; 1677 uint32_t wait_seq = 0; 1678 int i; 1679 1680 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { 1681 ring = &adev->jpeg.inst[inst].ring_dec[i]; 1682 1683 drm_sched_wqueue_stop(&ring->sched); 1684 /* Get the last emitted fence sequence */ 1685 wait_seq = atomic_read(&ring->fence_drv.last_seq); 1686 if (wait_seq) 1687 continue; 1688 1689 /* if Jobs are still pending after timeout, 1690 * We'll handle them in the bottom helper 1691 */ 1692 amdgpu_fence_wait_polling(ring, wait_seq, adev->video_timeout); 1693 } 1694 1695 return 0; 1696 } 1697 1698 static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst) 1699 { 1700 struct amdgpu_ring *ring; 1701 int i, r = 0; 1702 1703 for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { 1704 ring = &adev->jpeg.inst[inst].ring_dec[i]; 1705 /* Force completion of any remaining jobs */ 1706 amdgpu_fence_driver_force_completion(ring, NULL); 1707 1708 if (ring->use_doorbell) 1709 WREG32_SOC15_OFFSET( 1710 VCN, GET_INST(VCN, inst), 1711 regVCN_JPEG_DB_CTRL, 1712 (ring->pipe ? (ring->pipe - 0x15) : 0), 1713 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | 1714 VCN_JPEG_DB_CTRL__EN_MASK); 1715 1716 r = amdgpu_ring_test_helper(ring); 1717 if (r) 1718 return r; 1719 1720 drm_sched_wqueue_start(&ring->sched); 1721 1722 DRM_DEV_DEBUG(adev->dev, "JPEG ring %d (inst %d) restored and sched restarted\n", 1723 i, inst); 1724 } 1725 return 0; 1726 } 1727 1728 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, 1729 unsigned int vmid, 1730 struct amdgpu_fence *timedout_fence) 1731 { 1732 int r = 0; 1733 int vcn_inst; 1734 struct amdgpu_device *adev = ring->adev; 1735 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1736 bool pg_state = false; 1737 1738 /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ 1739 mutex_lock(&vinst->engine_reset_mutex); 1740 mutex_lock(&adev->jpeg.jpeg_pg_lock); 1741 /* Ensure JPEG is powered on during reset if currently gated */ 1742 if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) { 1743 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, 1744 AMD_PG_STATE_UNGATE); 1745 pg_state = true; 1746 } 1747 1748 vcn_v4_0_3_reset_jpeg_pre_helper(adev, ring->me); 1749 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1750 1751 vcn_inst = GET_INST(VCN, ring->me); 1752 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1753 1754 if (r) { 1755 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1756 /* Restore JPEG power gating state if it was originally gated */ 1757 if (pg_state) 1758 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, 1759 AMD_PG_STATE_GATE); 1760 mutex_unlock(&adev->jpeg.jpeg_pg_lock); 1761 goto unlock; 1762 } 1763 1764 /* This flag is not set for VF, assumed to be disabled always */ 1765 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1766 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1767 vcn_v4_0_3_hw_init_inst(vinst); 1768 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1769 1770 r = amdgpu_ring_reset_helper_end(ring, timedout_fence); 1771 if (r) { 1772 if (pg_state) 1773 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, 1774 AMD_PG_STATE_GATE); 1775 mutex_unlock(&adev->jpeg.jpeg_pg_lock); 1776 goto unlock; 1777 } 1778 1779 if (pg_state) 1780 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, 1781 AMD_PG_STATE_GATE); 1782 mutex_unlock(&adev->jpeg.jpeg_pg_lock); 1783 r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); 1784 1785 unlock: 1786 mutex_unlock(&vinst->engine_reset_mutex); 1787 1788 return r; 1789 } 1790 1791 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1792 .type = AMDGPU_RING_TYPE_VCN_ENC, 1793 .align_mask = 0x3f, 1794 .nop = VCN_ENC_CMD_NO_OP, 1795 .no_user_fence = true, 1796 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1797 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1798 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1799 .emit_frame_size = 1800 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1801 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1802 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1803 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1804 1, /* vcn_v2_0_enc_ring_insert_end */ 1805 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1806 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1807 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1808 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1809 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1810 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1811 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1812 .insert_nop = amdgpu_ring_insert_nop, 1813 .insert_end = vcn_v2_0_enc_ring_insert_end, 1814 .pad_ib = amdgpu_ring_generic_pad_ib, 1815 .begin_use = amdgpu_vcn_ring_begin_use, 1816 .end_use = amdgpu_vcn_ring_end_use, 1817 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1818 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1819 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1820 .reset = vcn_v4_0_3_ring_reset, 1821 }; 1822 1823 /** 1824 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1825 * 1826 * @adev: amdgpu_device pointer 1827 * 1828 * Set unified ring functions 1829 */ 1830 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1831 { 1832 int i, vcn_inst; 1833 1834 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1835 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1836 adev->vcn.inst[i].ring_enc[0].me = i; 1837 vcn_inst = GET_INST(VCN, i); 1838 adev->vcn.inst[i].aid_id = 1839 vcn_inst / adev->vcn.num_inst_per_aid; 1840 } 1841 } 1842 1843 /** 1844 * vcn_v4_0_3_is_idle - check VCN block is idle 1845 * 1846 * @ip_block: Pointer to the amdgpu_ip_block structure 1847 * 1848 * Check whether VCN block is idle 1849 */ 1850 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1851 { 1852 struct amdgpu_device *adev = ip_block->adev; 1853 int i, ret = 1; 1854 1855 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1856 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1857 UVD_STATUS__IDLE); 1858 } 1859 1860 return ret; 1861 } 1862 1863 /** 1864 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1865 * 1866 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1867 * 1868 * Wait for VCN block idle 1869 */ 1870 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1871 { 1872 struct amdgpu_device *adev = ip_block->adev; 1873 int i, ret = 0; 1874 1875 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1876 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1877 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1878 if (ret) 1879 return ret; 1880 } 1881 1882 return ret; 1883 } 1884 1885 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1886 * 1887 * @ip_block: amdgpu_ip_block pointer 1888 * @state: clock gating state 1889 * 1890 * Set VCN block clockgating state 1891 */ 1892 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1893 enum amd_clockgating_state state) 1894 { 1895 struct amdgpu_device *adev = ip_block->adev; 1896 bool enable = state == AMD_CG_STATE_GATE; 1897 int i; 1898 1899 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1900 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1901 1902 if (enable) { 1903 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1904 regUVD_STATUS) != UVD_STATUS__IDLE) 1905 return -EBUSY; 1906 vcn_v4_0_3_enable_clock_gating(vinst); 1907 } else { 1908 vcn_v4_0_3_disable_clock_gating(vinst); 1909 } 1910 } 1911 return 0; 1912 } 1913 1914 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1915 enum amd_powergating_state state) 1916 { 1917 struct amdgpu_device *adev = vinst->adev; 1918 int ret = 0; 1919 1920 /* for SRIOV, guest should not control VCN Power-gating 1921 * MMSCH FW should control Power-gating and clock-gating 1922 * guest should avoid touching CGC and PG 1923 */ 1924 if (amdgpu_sriov_vf(adev)) { 1925 vinst->cur_state = AMD_PG_STATE_UNGATE; 1926 return 0; 1927 } 1928 1929 if (state == vinst->cur_state) 1930 return 0; 1931 1932 if (state == AMD_PG_STATE_GATE) 1933 ret = vcn_v4_0_3_stop(vinst); 1934 else 1935 ret = vcn_v4_0_3_start(vinst); 1936 1937 if (!ret) 1938 vinst->cur_state = state; 1939 1940 return ret; 1941 } 1942 1943 /** 1944 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1945 * 1946 * @adev: amdgpu_device pointer 1947 * @source: interrupt sources 1948 * @type: interrupt types 1949 * @state: interrupt states 1950 * 1951 * Set VCN block interrupt state 1952 */ 1953 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1954 struct amdgpu_irq_src *source, 1955 unsigned int type, 1956 enum amdgpu_interrupt_state state) 1957 { 1958 return 0; 1959 } 1960 1961 /** 1962 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1963 * 1964 * @adev: amdgpu_device pointer 1965 * @source: interrupt sources 1966 * @entry: interrupt entry from clients and sources 1967 * 1968 * Process VCN block interrupt 1969 */ 1970 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1971 struct amdgpu_irq_src *source, 1972 struct amdgpu_iv_entry *entry) 1973 { 1974 uint32_t i, inst; 1975 1976 i = node_id_to_phys_map[entry->node_id]; 1977 1978 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1979 1980 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1981 if (adev->vcn.inst[inst].aid_id == i) 1982 break; 1983 1984 if (inst >= adev->vcn.num_vcn_inst) { 1985 dev_WARN_ONCE(adev->dev, 1, 1986 "Interrupt received for unknown VCN instance %d", 1987 entry->node_id); 1988 return 0; 1989 } 1990 1991 switch (entry->src_id) { 1992 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1993 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1994 break; 1995 default: 1996 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1997 entry->src_id, entry->src_data[0]); 1998 break; 1999 } 2000 2001 return 0; 2002 } 2003 2004 static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 2005 struct amdgpu_irq_src *source, 2006 unsigned int type, 2007 enum amdgpu_interrupt_state state) 2008 { 2009 return 0; 2010 } 2011 2012 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 2013 .set = vcn_v4_0_3_set_interrupt_state, 2014 .process = vcn_v4_0_3_process_interrupt, 2015 }; 2016 2017 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = { 2018 .set = vcn_v4_0_3_set_ras_interrupt_state, 2019 .process = amdgpu_vcn_process_poison_irq, 2020 }; 2021 2022 /** 2023 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 2024 * 2025 * @adev: amdgpu_device pointer 2026 * 2027 * Set VCN block interrupt irq functions 2028 */ 2029 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 2030 { 2031 int i; 2032 2033 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2034 adev->vcn.inst->irq.num_types++; 2035 } 2036 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 2037 2038 adev->vcn.inst->ras_poison_irq.num_types = 1; 2039 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; 2040 } 2041 2042 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 2043 .name = "vcn_v4_0_3", 2044 .early_init = vcn_v4_0_3_early_init, 2045 .late_init = vcn_v4_0_3_late_init, 2046 .sw_init = vcn_v4_0_3_sw_init, 2047 .sw_fini = vcn_v4_0_3_sw_fini, 2048 .hw_init = vcn_v4_0_3_hw_init, 2049 .hw_fini = vcn_v4_0_3_hw_fini, 2050 .suspend = vcn_v4_0_3_suspend, 2051 .resume = vcn_v4_0_3_resume, 2052 .is_idle = vcn_v4_0_3_is_idle, 2053 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 2054 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 2055 .set_powergating_state = vcn_set_powergating_state, 2056 .dump_ip_state = amdgpu_vcn_dump_ip_state, 2057 .print_ip_state = amdgpu_vcn_print_ip_state, 2058 }; 2059 2060 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 2061 .type = AMD_IP_BLOCK_TYPE_VCN, 2062 .major = 4, 2063 .minor = 0, 2064 .rev = 3, 2065 .funcs = &vcn_v4_0_3_ip_funcs, 2066 }; 2067 2068 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 2069 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 2070 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 2071 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 2072 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 2073 }; 2074 2075 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 2076 uint32_t vcn_inst, 2077 void *ras_err_status) 2078 { 2079 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 2080 2081 /* vcn v4_0_3 only support query uncorrectable errors */ 2082 amdgpu_ras_inst_query_ras_error_count(adev, 2083 vcn_v4_0_3_ue_reg_list, 2084 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 2085 NULL, 0, GET_INST(VCN, vcn_inst), 2086 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 2087 &err_data->ue_count); 2088 } 2089 2090 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 2091 void *ras_err_status) 2092 { 2093 uint32_t i; 2094 2095 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 2096 dev_warn(adev->dev, "VCN RAS is not supported\n"); 2097 return; 2098 } 2099 2100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2101 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 2102 } 2103 2104 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 2105 uint32_t vcn_inst) 2106 { 2107 amdgpu_ras_inst_reset_ras_error_count(adev, 2108 vcn_v4_0_3_ue_reg_list, 2109 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 2110 GET_INST(VCN, vcn_inst)); 2111 } 2112 2113 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 2114 { 2115 uint32_t i; 2116 2117 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 2118 dev_warn(adev->dev, "VCN RAS is not supported\n"); 2119 return; 2120 } 2121 2122 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 2123 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 2124 } 2125 2126 static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 2127 uint32_t instance, uint32_t sub_block) 2128 { 2129 uint32_t poison_stat = 0, reg_value = 0; 2130 2131 switch (sub_block) { 2132 case AMDGPU_VCN_V4_0_3_VCPU_VCODEC: 2133 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2134 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2135 break; 2136 default: 2137 break; 2138 } 2139 2140 if (poison_stat) 2141 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2142 instance, sub_block); 2143 2144 return poison_stat; 2145 } 2146 2147 static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev) 2148 { 2149 uint32_t inst, sub; 2150 uint32_t poison_stat = 0; 2151 2152 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2153 for (sub = 0; sub < AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++) 2154 poison_stat += 2155 vcn_v4_0_3_query_poison_by_instance(adev, inst, sub); 2156 2157 return !!poison_stat; 2158 } 2159 2160 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 2161 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 2162 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 2163 .query_poison_status = vcn_v4_0_3_query_poison_status, 2164 }; 2165 2166 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2167 { 2168 int r; 2169 2170 r = amdgpu_ras_block_late_init(adev, ras_block); 2171 if (r) 2172 return r; 2173 2174 if (amdgpu_ras_is_supported(adev, ras_block->block) && 2175 adev->vcn.inst->ras_poison_irq.funcs) { 2176 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 2177 if (r) 2178 goto late_fini; 2179 } 2180 2181 return 0; 2182 2183 late_fini: 2184 amdgpu_ras_block_late_fini(adev, ras_block); 2185 2186 return r; 2187 } 2188 2189 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2190 .ras_block = { 2191 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2192 .ras_late_init = vcn_v4_0_3_ras_late_init, 2193 }, 2194 }; 2195 2196 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2197 { 2198 adev->vcn.ras = &vcn_v4_0_3_ras; 2199 } 2200 2201 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2202 int inst_idx, bool indirect) 2203 { 2204 uint32_t tmp; 2205 2206 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2207 return; 2208 2209 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2210 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2211 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2212 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2213 WREG32_SOC15_DPG_MODE(inst_idx, 2214 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2215 tmp, 0, indirect); 2216 2217 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2218 WREG32_SOC15_DPG_MODE(inst_idx, 2219 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2220 tmp, 0, indirect); 2221 2222 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2223 WREG32_SOC15_DPG_MODE(inst_idx, 2224 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2225 tmp, 0, indirect); 2226 } 2227