1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 119 /* re-use enc ring as unified ring */ 120 adev->vcn.inst[i].num_enc_rings = 1; 121 122 vcn_v4_0_3_set_unified_ring_funcs(adev); 123 vcn_v4_0_3_set_irq_funcs(adev); 124 vcn_v4_0_3_set_ras_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 138 { 139 struct amdgpu_vcn4_fw_shared *fw_shared; 140 141 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 142 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 143 fw_shared->sq.is_enabled = 1; 144 145 if (amdgpu_vcnfw_log) 146 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 147 148 return 0; 149 } 150 151 /** 152 * vcn_v4_0_3_sw_init - sw init for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * Load firmware and sw initialization 157 */ 158 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_device *adev = ip_block->adev; 161 struct amdgpu_ring *ring; 162 int i, r, vcn_inst; 163 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 164 uint32_t *ptr; 165 166 /* VCN DEC TRAP */ 167 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 168 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 169 if (r) 170 return r; 171 172 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 173 174 r = amdgpu_vcn_sw_init(adev, i); 175 if (r) 176 return r; 177 178 amdgpu_vcn_setup_ucode(adev, i); 179 180 r = amdgpu_vcn_resume(adev, i); 181 if (r) 182 return r; 183 184 vcn_inst = GET_INST(VCN, i); 185 186 ring = &adev->vcn.inst[i].ring_enc[0]; 187 ring->use_doorbell = true; 188 189 if (!amdgpu_sriov_vf(adev)) 190 ring->doorbell_index = 191 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 192 9 * vcn_inst; 193 else 194 ring->doorbell_index = 195 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 196 32 * vcn_inst; 197 198 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 199 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 200 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 201 AMDGPU_RING_PRIO_DEFAULT, 202 &adev->vcn.inst[i].sched_score); 203 if (r) 204 return r; 205 206 vcn_v4_0_3_fw_shared_init(adev, i); 207 208 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 209 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 210 } 211 212 /* TODO: Add queue reset mask when FW fully supports it */ 213 adev->vcn.supported_reset = 214 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 215 216 if (amdgpu_sriov_vf(adev)) { 217 r = amdgpu_virt_alloc_mm_table(adev); 218 if (r) 219 return r; 220 } 221 222 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 223 r = amdgpu_vcn_ras_sw_init(adev); 224 if (r) { 225 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 226 return r; 227 } 228 } 229 230 /* Allocate memory for VCN IP Dump buffer */ 231 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 232 if (!ptr) { 233 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 234 adev->vcn.ip_dump = NULL; 235 } else { 236 adev->vcn.ip_dump = ptr; 237 } 238 239 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 240 if (r) 241 return r; 242 243 return 0; 244 } 245 246 /** 247 * vcn_v4_0_3_sw_fini - sw fini for VCN block 248 * 249 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 254 { 255 struct amdgpu_device *adev = ip_block->adev; 256 int i, r, idx; 257 258 if (drm_dev_enter(&adev->ddev, &idx)) { 259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 260 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 261 262 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 263 fw_shared->present_flag_0 = 0; 264 fw_shared->sq.is_enabled = cpu_to_le32(false); 265 } 266 drm_dev_exit(idx); 267 } 268 269 if (amdgpu_sriov_vf(adev)) 270 amdgpu_virt_free_mm_table(adev); 271 272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 273 r = amdgpu_vcn_suspend(adev, i); 274 if (r) 275 return r; 276 } 277 278 amdgpu_vcn_sysfs_reset_mask_fini(adev); 279 280 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 281 r = amdgpu_vcn_sw_fini(adev, i); 282 if (r) 283 return r; 284 } 285 286 kfree(adev->vcn.ip_dump); 287 288 return 0; 289 } 290 291 /** 292 * vcn_v4_0_3_hw_init - start and test VCN block 293 * 294 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 295 * 296 * Initialize the hardware, boot up the VCPU and do some testing 297 */ 298 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 299 { 300 struct amdgpu_device *adev = ip_block->adev; 301 struct amdgpu_ring *ring; 302 int i, r, vcn_inst; 303 304 if (amdgpu_sriov_vf(adev)) { 305 r = vcn_v4_0_3_start_sriov(adev); 306 if (r) 307 return r; 308 309 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 310 ring = &adev->vcn.inst[i].ring_enc[0]; 311 ring->wptr = 0; 312 ring->wptr_old = 0; 313 vcn_v4_0_3_unified_ring_set_wptr(ring); 314 ring->sched.ready = true; 315 } 316 } else { 317 /* This flag is not set for VF, assumed to be disabled always */ 318 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 319 0x100) 320 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 321 322 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 323 struct amdgpu_vcn4_fw_shared *fw_shared; 324 325 vcn_inst = GET_INST(VCN, i); 326 ring = &adev->vcn.inst[i].ring_enc[0]; 327 328 if (ring->use_doorbell) { 329 adev->nbio.funcs->vcn_doorbell_range( 330 adev, ring->use_doorbell, 331 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 332 9 * vcn_inst, 333 adev->vcn.inst[i].aid_id); 334 335 WREG32_SOC15( 336 VCN, GET_INST(VCN, ring->me), 337 regVCN_RB1_DB_CTRL, 338 ring->doorbell_index 339 << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 340 VCN_RB1_DB_CTRL__EN_MASK); 341 342 /* Read DB_CTRL to flush the write DB_CTRL command. */ 343 RREG32_SOC15( 344 VCN, GET_INST(VCN, ring->me), 345 regVCN_RB1_DB_CTRL); 346 } 347 348 /* Re-init fw_shared when RAS fatal error occurred */ 349 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 350 if (!fw_shared->sq.is_enabled) 351 vcn_v4_0_3_fw_shared_init(adev, i); 352 353 r = amdgpu_ring_test_helper(ring); 354 if (r) 355 return r; 356 } 357 } 358 359 return r; 360 } 361 362 /** 363 * vcn_v4_0_3_hw_fini - stop the hardware block 364 * 365 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 366 * 367 * Stop the VCN block, mark ring as not ready any more 368 */ 369 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 370 { 371 struct amdgpu_device *adev = ip_block->adev; 372 int i; 373 374 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 375 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 376 377 cancel_delayed_work_sync(&vinst->idle_work); 378 379 if (vinst->cur_state != AMD_PG_STATE_GATE) 380 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 381 } 382 383 return 0; 384 } 385 386 /** 387 * vcn_v4_0_3_suspend - suspend VCN block 388 * 389 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 390 * 391 * HW fini and suspend VCN block 392 */ 393 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 394 { 395 struct amdgpu_device *adev = ip_block->adev; 396 int r, i; 397 398 r = vcn_v4_0_3_hw_fini(ip_block); 399 if (r) 400 return r; 401 402 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 403 r = amdgpu_vcn_suspend(adev, i); 404 if (r) 405 return r; 406 } 407 408 return 0; 409 } 410 411 /** 412 * vcn_v4_0_3_resume - resume VCN block 413 * 414 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 415 * 416 * Resume firmware and hw init VCN block 417 */ 418 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 419 { 420 struct amdgpu_device *adev = ip_block->adev; 421 int r, i; 422 423 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 424 r = amdgpu_vcn_resume(ip_block->adev, i); 425 if (r) 426 return r; 427 } 428 429 r = vcn_v4_0_3_hw_init(ip_block); 430 431 return r; 432 } 433 434 /** 435 * vcn_v4_0_3_mc_resume - memory controller programming 436 * 437 * @vinst: VCN instance 438 * 439 * Let the VCN memory controller know it's offsets 440 */ 441 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 442 { 443 struct amdgpu_device *adev = vinst->adev; 444 int inst_idx = vinst->inst; 445 uint32_t offset, size, vcn_inst; 446 const struct common_firmware_header *hdr; 447 448 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 449 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 450 451 vcn_inst = GET_INST(VCN, inst_idx); 452 /* cache window 0: fw */ 453 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 454 WREG32_SOC15( 455 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 456 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 457 .tmr_mc_addr_lo)); 458 WREG32_SOC15( 459 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 461 .tmr_mc_addr_hi)); 462 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 463 offset = 0; 464 } else { 465 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 467 WREG32_SOC15(VCN, vcn_inst, 468 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 470 offset = size; 471 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 472 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 473 } 474 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 475 476 /* cache window 1: stack */ 477 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 478 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 479 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 480 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 481 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 482 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 483 AMDGPU_VCN_STACK_SIZE); 484 485 /* cache window 2: context */ 486 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 487 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 488 AMDGPU_VCN_STACK_SIZE)); 489 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 490 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 491 AMDGPU_VCN_STACK_SIZE)); 492 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 493 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 494 AMDGPU_VCN_CONTEXT_SIZE); 495 496 /* non-cache window */ 497 WREG32_SOC15( 498 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 499 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 500 WREG32_SOC15( 501 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 502 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 503 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 504 WREG32_SOC15( 505 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 506 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 507 } 508 509 /** 510 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 511 * 512 * @vinst: VCN instance 513 * @indirect: indirectly write sram 514 * 515 * Let the VCN memory controller know it's offsets with dpg mode 516 */ 517 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 518 bool indirect) 519 { 520 struct amdgpu_device *adev = vinst->adev; 521 int inst_idx = vinst->inst; 522 uint32_t offset, size; 523 const struct common_firmware_header *hdr; 524 525 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 526 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 527 528 /* cache window 0: fw */ 529 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 530 if (!indirect) { 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 533 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 534 inst_idx].tmr_mc_addr_lo), 0, indirect); 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 537 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 538 inst_idx].tmr_mc_addr_hi), 0, indirect); 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 541 } else { 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 548 } 549 offset = 0; 550 } else { 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 553 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 554 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 555 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 556 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 557 offset = size; 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 560 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 561 } 562 563 if (!indirect) 564 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 565 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 566 else 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 568 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 569 570 /* cache window 1: stack */ 571 if (!indirect) { 572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 573 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 574 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 576 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 577 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 578 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 579 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 580 } else { 581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 582 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 587 } 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 590 591 /* cache window 2: context */ 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 594 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 595 AMDGPU_VCN_STACK_SIZE), 0, indirect); 596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 597 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 598 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 599 AMDGPU_VCN_STACK_SIZE), 0, indirect); 600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 601 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 602 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 603 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 604 605 /* non-cache window */ 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 607 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 608 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 609 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 610 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 611 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 612 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 613 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 614 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 615 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 616 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 617 618 /* VCN global tiling registers */ 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 621 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 622 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 623 } 624 625 /** 626 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 627 * 628 * @vinst: VCN instance 629 * 630 * Disable clock gating for VCN block 631 */ 632 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 633 { 634 struct amdgpu_device *adev = vinst->adev; 635 int inst_idx = vinst->inst; 636 uint32_t data; 637 int vcn_inst; 638 639 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 640 return; 641 642 vcn_inst = GET_INST(VCN, inst_idx); 643 644 /* VCN disable CGC */ 645 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 646 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 647 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 648 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 649 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 650 651 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 652 data &= ~(UVD_CGC_GATE__SYS_MASK 653 | UVD_CGC_GATE__MPEG2_MASK 654 | UVD_CGC_GATE__REGS_MASK 655 | UVD_CGC_GATE__RBC_MASK 656 | UVD_CGC_GATE__LMI_MC_MASK 657 | UVD_CGC_GATE__LMI_UMC_MASK 658 | UVD_CGC_GATE__MPC_MASK 659 | UVD_CGC_GATE__LBSI_MASK 660 | UVD_CGC_GATE__LRBBM_MASK 661 | UVD_CGC_GATE__WCB_MASK 662 | UVD_CGC_GATE__VCPU_MASK 663 | UVD_CGC_GATE__MMSCH_MASK); 664 665 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 666 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 667 668 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 669 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 670 | UVD_CGC_CTRL__MPEG2_MODE_MASK 671 | UVD_CGC_CTRL__REGS_MODE_MASK 672 | UVD_CGC_CTRL__RBC_MODE_MASK 673 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 674 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 675 | UVD_CGC_CTRL__MPC_MODE_MASK 676 | UVD_CGC_CTRL__LBSI_MODE_MASK 677 | UVD_CGC_CTRL__LRBBM_MODE_MASK 678 | UVD_CGC_CTRL__WCB_MODE_MASK 679 | UVD_CGC_CTRL__VCPU_MODE_MASK 680 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 681 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 682 683 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 684 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 685 | UVD_SUVD_CGC_GATE__SIT_MASK 686 | UVD_SUVD_CGC_GATE__SMP_MASK 687 | UVD_SUVD_CGC_GATE__SCM_MASK 688 | UVD_SUVD_CGC_GATE__SDB_MASK 689 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 690 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 691 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 692 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 693 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 694 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 695 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 696 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 697 | UVD_SUVD_CGC_GATE__ENT_MASK 698 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 699 | UVD_SUVD_CGC_GATE__SITE_MASK 700 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 701 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 702 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 703 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 704 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 705 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 706 707 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 708 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 709 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 710 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 711 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 712 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 713 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 714 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 715 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 716 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 717 } 718 719 /** 720 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 721 * 722 * @vinst: VCN instance 723 * @sram_sel: sram select 724 * @indirect: indirectly write sram 725 * 726 * Disable clock gating for VCN block with dpg mode 727 */ 728 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 729 uint8_t sram_sel, 730 uint8_t indirect) 731 { 732 struct amdgpu_device *adev = vinst->adev; 733 int inst_idx = vinst->inst; 734 uint32_t reg_data = 0; 735 736 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 737 return; 738 739 /* enable sw clock gating control */ 740 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 741 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 742 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 743 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 744 UVD_CGC_CTRL__MPEG2_MODE_MASK | 745 UVD_CGC_CTRL__REGS_MODE_MASK | 746 UVD_CGC_CTRL__RBC_MODE_MASK | 747 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 748 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 749 UVD_CGC_CTRL__IDCT_MODE_MASK | 750 UVD_CGC_CTRL__MPRD_MODE_MASK | 751 UVD_CGC_CTRL__MPC_MODE_MASK | 752 UVD_CGC_CTRL__LBSI_MODE_MASK | 753 UVD_CGC_CTRL__LRBBM_MODE_MASK | 754 UVD_CGC_CTRL__WCB_MODE_MASK | 755 UVD_CGC_CTRL__VCPU_MODE_MASK); 756 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 757 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 758 759 /* turn off clock gating */ 760 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 761 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 762 763 /* turn on SUVD clock gating */ 764 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 765 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 766 767 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 768 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 769 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 770 } 771 772 /** 773 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 774 * 775 * @vinst: VCN instance 776 * 777 * Enable clock gating for VCN block 778 */ 779 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 780 { 781 struct amdgpu_device *adev = vinst->adev; 782 int inst_idx = vinst->inst; 783 uint32_t data; 784 int vcn_inst; 785 786 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 787 return; 788 789 vcn_inst = GET_INST(VCN, inst_idx); 790 791 /* enable VCN CGC */ 792 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 793 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 794 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 795 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 796 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 797 798 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 799 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 800 | UVD_CGC_CTRL__MPEG2_MODE_MASK 801 | UVD_CGC_CTRL__REGS_MODE_MASK 802 | UVD_CGC_CTRL__RBC_MODE_MASK 803 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 804 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 805 | UVD_CGC_CTRL__MPC_MODE_MASK 806 | UVD_CGC_CTRL__LBSI_MODE_MASK 807 | UVD_CGC_CTRL__LRBBM_MODE_MASK 808 | UVD_CGC_CTRL__WCB_MODE_MASK 809 | UVD_CGC_CTRL__VCPU_MODE_MASK); 810 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 811 812 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 813 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 821 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 822 } 823 824 /** 825 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 826 * 827 * @vinst: VCN instance 828 * @indirect: indirectly write sram 829 * 830 * Start VCN block with dpg mode 831 */ 832 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 833 bool indirect) 834 { 835 struct amdgpu_device *adev = vinst->adev; 836 int inst_idx = vinst->inst; 837 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 838 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 839 struct amdgpu_ring *ring; 840 int vcn_inst; 841 uint32_t tmp; 842 843 vcn_inst = GET_INST(VCN, inst_idx); 844 /* disable register anti-hang mechanism */ 845 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 846 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 847 /* enable dynamic power gating mode */ 848 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 849 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 850 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 851 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 852 853 if (indirect) { 854 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 855 inst_idx, adev->vcn.inst[inst_idx].aid_id); 856 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 857 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 858 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 859 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 860 adev->vcn.inst[inst_idx].aid_id, 0, true); 861 } 862 863 /* enable clock gating */ 864 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 865 866 /* enable VCPU clock */ 867 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 868 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 869 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 870 871 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 872 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 873 874 /* disable master interrupt */ 875 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 876 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 877 878 /* setup regUVD_LMI_CTRL */ 879 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 880 UVD_LMI_CTRL__REQ_MODE_MASK | 881 UVD_LMI_CTRL__CRC_RESET_MASK | 882 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 883 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 884 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 885 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 886 0x00100000L); 887 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 888 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 889 890 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 891 VCN, 0, regUVD_MPC_CNTL), 892 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 893 894 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 895 VCN, 0, regUVD_MPC_SET_MUXA0), 896 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 897 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 898 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 899 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 900 901 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 902 VCN, 0, regUVD_MPC_SET_MUXB0), 903 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 904 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 905 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 906 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 907 908 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 909 VCN, 0, regUVD_MPC_SET_MUX), 910 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 911 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 912 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 913 914 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 915 916 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 917 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 918 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 919 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 920 921 /* enable LMI MC and UMC channels */ 922 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 923 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 924 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 925 926 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 927 928 /* enable master interrupt */ 929 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 930 VCN, 0, regUVD_MASTINT_EN), 931 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 932 933 if (indirect) 934 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 935 936 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 937 938 /* program the RB_BASE for ring buffer */ 939 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 940 lower_32_bits(ring->gpu_addr)); 941 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 942 upper_32_bits(ring->gpu_addr)); 943 944 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 945 ring->ring_size / sizeof(uint32_t)); 946 947 /* resetting ring, fw should not check RB ring */ 948 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 949 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 950 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 951 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 952 953 /* Initialize the ring buffer's read and write pointers */ 954 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 955 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 956 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 957 958 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 959 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 960 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 961 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 962 963 /*resetting done, fw can check RB ring */ 964 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 965 966 return 0; 967 } 968 969 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 970 { 971 int i, vcn_inst; 972 struct amdgpu_ring *ring_enc; 973 uint64_t cache_addr; 974 uint64_t rb_enc_addr; 975 uint64_t ctx_addr; 976 uint32_t param, resp, expected; 977 uint32_t offset, cache_size; 978 uint32_t tmp, timeout; 979 980 struct amdgpu_mm_table *table = &adev->virt.mm_table; 981 uint32_t *table_loc; 982 uint32_t table_size; 983 uint32_t size, size_dw; 984 uint32_t init_status; 985 uint32_t enabled_vcn; 986 987 struct mmsch_v4_0_cmd_direct_write 988 direct_wt = { {0} }; 989 struct mmsch_v4_0_cmd_direct_read_modify_write 990 direct_rd_mod_wt = { {0} }; 991 struct mmsch_v4_0_cmd_end end = { {0} }; 992 struct mmsch_v4_0_3_init_header header; 993 994 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 995 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 996 997 direct_wt.cmd_header.command_type = 998 MMSCH_COMMAND__DIRECT_REG_WRITE; 999 direct_rd_mod_wt.cmd_header.command_type = 1000 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1001 end.cmd_header.command_type = MMSCH_COMMAND__END; 1002 1003 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1004 vcn_inst = GET_INST(VCN, i); 1005 1006 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1007 1008 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1009 header.version = MMSCH_VERSION; 1010 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1011 1012 table_loc = (uint32_t *)table->cpu_addr; 1013 table_loc += header.total_size; 1014 1015 table_size = 0; 1016 1017 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1018 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1019 1020 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1021 1022 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1023 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1024 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1025 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1026 1027 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1028 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1029 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1030 1031 offset = 0; 1032 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1033 regUVD_VCPU_CACHE_OFFSET0), 0); 1034 } else { 1035 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1036 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1037 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1038 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1039 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1040 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1041 offset = cache_size; 1042 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1043 regUVD_VCPU_CACHE_OFFSET0), 1044 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1045 } 1046 1047 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1048 regUVD_VCPU_CACHE_SIZE0), 1049 cache_size); 1050 1051 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1052 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1053 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1054 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1055 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1056 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1057 regUVD_VCPU_CACHE_OFFSET1), 0); 1058 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1059 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1060 1061 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1062 AMDGPU_VCN_STACK_SIZE; 1063 1064 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1065 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1066 1067 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1068 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1069 1070 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1071 regUVD_VCPU_CACHE_OFFSET2), 0); 1072 1073 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1074 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1075 1076 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1077 rb_setup = &fw_shared->rb_setup; 1078 1079 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1080 ring_enc->wptr = 0; 1081 rb_enc_addr = ring_enc->gpu_addr; 1082 1083 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1084 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1085 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1086 rb_setup->rb_size = ring_enc->ring_size / 4; 1087 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1088 1089 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1090 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1091 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1092 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1093 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1094 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1095 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1096 regUVD_VCPU_NONCACHE_SIZE0), 1097 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1098 MMSCH_V4_0_INSERT_END(); 1099 1100 header.vcn0.init_status = 0; 1101 header.vcn0.table_offset = header.total_size; 1102 header.vcn0.table_size = table_size; 1103 header.total_size += table_size; 1104 1105 /* Send init table to mmsch */ 1106 size = sizeof(struct mmsch_v4_0_3_init_header); 1107 table_loc = (uint32_t *)table->cpu_addr; 1108 memcpy((void *)table_loc, &header, size); 1109 1110 ctx_addr = table->gpu_addr; 1111 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1112 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1113 1114 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1115 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1116 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1117 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1118 1119 size = header.total_size; 1120 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1121 1122 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1123 1124 param = 0x00000001; 1125 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1126 tmp = 0; 1127 timeout = 1000; 1128 resp = 0; 1129 expected = MMSCH_VF_MAILBOX_RESP__OK; 1130 while (resp != expected) { 1131 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1132 if (resp != 0) 1133 break; 1134 1135 udelay(10); 1136 tmp = tmp + 10; 1137 if (tmp >= timeout) { 1138 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1139 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1140 "(expected=0x%08x, readback=0x%08x)\n", 1141 tmp, expected, resp); 1142 return -EBUSY; 1143 } 1144 } 1145 1146 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1147 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1148 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1149 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1150 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1151 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1152 } 1153 } 1154 1155 return 0; 1156 } 1157 1158 /** 1159 * vcn_v4_0_3_start - VCN start 1160 * 1161 * @vinst: VCN instance 1162 * 1163 * Start VCN block 1164 */ 1165 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1166 { 1167 struct amdgpu_device *adev = vinst->adev; 1168 int i = vinst->inst; 1169 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1170 struct amdgpu_ring *ring; 1171 int j, k, r, vcn_inst; 1172 uint32_t tmp; 1173 1174 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1175 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1176 1177 vcn_inst = GET_INST(VCN, i); 1178 /* set VCN status busy */ 1179 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1180 UVD_STATUS__UVD_BUSY; 1181 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1182 1183 /* SW clock gating */ 1184 vcn_v4_0_3_disable_clock_gating(vinst); 1185 1186 /* enable VCPU clock */ 1187 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1188 UVD_VCPU_CNTL__CLK_EN_MASK, 1189 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1190 1191 /* disable master interrupt */ 1192 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1193 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1194 1195 /* enable LMI MC and UMC channels */ 1196 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1197 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1198 1199 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1200 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1201 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1202 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1203 1204 /* setup regUVD_LMI_CTRL */ 1205 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1206 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1207 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1208 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1209 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1210 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1211 1212 /* setup regUVD_MPC_CNTL */ 1213 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1214 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1215 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1216 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1217 1218 /* setup UVD_MPC_SET_MUXA0 */ 1219 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1220 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1221 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1222 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1223 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1224 1225 /* setup UVD_MPC_SET_MUXB0 */ 1226 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1227 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1228 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1229 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1230 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1231 1232 /* setup UVD_MPC_SET_MUX */ 1233 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1234 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1235 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1236 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1237 1238 vcn_v4_0_3_mc_resume(vinst); 1239 1240 /* VCN global tiling registers */ 1241 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1242 adev->gfx.config.gb_addr_config); 1243 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1244 adev->gfx.config.gb_addr_config); 1245 1246 /* unblock VCPU register access */ 1247 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1248 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1249 1250 /* release VCPU reset to boot */ 1251 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1252 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1253 1254 for (j = 0; j < 10; ++j) { 1255 uint32_t status; 1256 1257 for (k = 0; k < 100; ++k) { 1258 status = RREG32_SOC15(VCN, vcn_inst, 1259 regUVD_STATUS); 1260 if (status & 2) 1261 break; 1262 mdelay(10); 1263 } 1264 r = 0; 1265 if (status & 2) 1266 break; 1267 1268 DRM_DEV_ERROR(adev->dev, 1269 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1270 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1271 regUVD_VCPU_CNTL), 1272 UVD_VCPU_CNTL__BLK_RST_MASK, 1273 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1274 mdelay(10); 1275 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1276 regUVD_VCPU_CNTL), 1277 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1278 1279 mdelay(10); 1280 r = -1; 1281 } 1282 1283 if (r) { 1284 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1285 return r; 1286 } 1287 1288 /* enable master interrupt */ 1289 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1290 UVD_MASTINT_EN__VCPU_EN_MASK, 1291 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1292 1293 /* clear the busy bit of VCN_STATUS */ 1294 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1295 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1296 1297 ring = &adev->vcn.inst[i].ring_enc[0]; 1298 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1299 1300 /* program the RB_BASE for ring buffer */ 1301 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1302 lower_32_bits(ring->gpu_addr)); 1303 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1304 upper_32_bits(ring->gpu_addr)); 1305 1306 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1307 ring->ring_size / sizeof(uint32_t)); 1308 1309 /* resetting ring, fw should not check RB ring */ 1310 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1311 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1312 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1313 1314 /* Initialize the ring buffer's read and write pointers */ 1315 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1316 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1317 1318 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1319 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1320 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1321 1322 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1323 fw_shared->sq.queue_mode &= 1324 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1325 1326 return 0; 1327 } 1328 1329 /** 1330 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1331 * 1332 * @vinst: VCN instance 1333 * 1334 * Stop VCN block with dpg mode 1335 */ 1336 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1337 { 1338 struct amdgpu_device *adev = vinst->adev; 1339 int inst_idx = vinst->inst; 1340 uint32_t tmp; 1341 int vcn_inst; 1342 1343 vcn_inst = GET_INST(VCN, inst_idx); 1344 1345 /* Wait for power status to be 1 */ 1346 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1347 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1348 1349 /* wait for read ptr to be equal to write ptr */ 1350 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1351 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1352 1353 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1354 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1355 1356 /* disable dynamic power gating mode */ 1357 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1358 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1359 return 0; 1360 } 1361 1362 /** 1363 * vcn_v4_0_3_stop - VCN stop 1364 * 1365 * @vinst: VCN instance 1366 * 1367 * Stop VCN block 1368 */ 1369 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1370 { 1371 struct amdgpu_device *adev = vinst->adev; 1372 int i = vinst->inst; 1373 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1374 int r = 0, vcn_inst; 1375 uint32_t tmp; 1376 1377 vcn_inst = GET_INST(VCN, i); 1378 1379 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1380 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1381 1382 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1383 vcn_v4_0_3_stop_dpg_mode(vinst); 1384 goto Done; 1385 } 1386 1387 /* wait for vcn idle */ 1388 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1389 UVD_STATUS__IDLE, 0x7); 1390 if (r) 1391 goto Done; 1392 1393 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1394 UVD_LMI_STATUS__READ_CLEAN_MASK | 1395 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1396 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1397 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1398 tmp); 1399 if (r) 1400 goto Done; 1401 1402 /* stall UMC channel */ 1403 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1404 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1405 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1406 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1407 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1408 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1409 tmp); 1410 if (r) 1411 goto Done; 1412 1413 /* Unblock VCPU Register access */ 1414 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1415 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1416 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1417 1418 /* release VCPU reset to boot */ 1419 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1420 UVD_VCPU_CNTL__BLK_RST_MASK, 1421 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1422 1423 /* disable VCPU clock */ 1424 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1425 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1426 1427 /* reset LMI UMC/LMI/VCPU */ 1428 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1429 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1430 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1431 1432 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1433 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1434 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1435 1436 /* clear VCN status */ 1437 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1438 1439 /* apply HW clock gating */ 1440 vcn_v4_0_3_enable_clock_gating(vinst); 1441 1442 Done: 1443 return 0; 1444 } 1445 1446 /** 1447 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1448 * 1449 * @vinst: VCN instance 1450 * @new_state: pause state 1451 * 1452 * Pause dpg mode for VCN block 1453 */ 1454 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1455 struct dpg_pause_state *new_state) 1456 { 1457 1458 return 0; 1459 } 1460 1461 /** 1462 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1463 * 1464 * @ring: amdgpu_ring pointer 1465 * 1466 * Returns the current hardware unified read pointer 1467 */ 1468 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1469 { 1470 struct amdgpu_device *adev = ring->adev; 1471 1472 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1473 DRM_ERROR("wrong ring id is identified in %s", __func__); 1474 1475 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1476 } 1477 1478 /** 1479 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1480 * 1481 * @ring: amdgpu_ring pointer 1482 * 1483 * Returns the current hardware unified write pointer 1484 */ 1485 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1486 { 1487 struct amdgpu_device *adev = ring->adev; 1488 1489 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1490 DRM_ERROR("wrong ring id is identified in %s", __func__); 1491 1492 if (ring->use_doorbell) 1493 return *ring->wptr_cpu_addr; 1494 else 1495 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1496 regUVD_RB_WPTR); 1497 } 1498 1499 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1500 uint32_t val, uint32_t mask) 1501 { 1502 /* Use normalized offsets when required */ 1503 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1504 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1505 1506 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1507 amdgpu_ring_write(ring, reg << 2); 1508 amdgpu_ring_write(ring, mask); 1509 amdgpu_ring_write(ring, val); 1510 } 1511 1512 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1513 uint32_t val) 1514 { 1515 /* Use normalized offsets when required */ 1516 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1517 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1518 1519 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1520 amdgpu_ring_write(ring, reg << 2); 1521 amdgpu_ring_write(ring, val); 1522 } 1523 1524 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1525 unsigned int vmid, uint64_t pd_addr) 1526 { 1527 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1528 1529 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1530 1531 /* wait for reg writes */ 1532 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1533 vmid * hub->ctx_addr_distance, 1534 lower_32_bits(pd_addr), 0xffffffff); 1535 } 1536 1537 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1538 { 1539 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1540 * This is a workaround to avoid any HDP flush through VCN ring. 1541 */ 1542 } 1543 1544 /** 1545 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1546 * 1547 * @ring: amdgpu_ring pointer 1548 * 1549 * Commits the enc write pointer to the hardware 1550 */ 1551 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1552 { 1553 struct amdgpu_device *adev = ring->adev; 1554 1555 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1556 DRM_ERROR("wrong ring id is identified in %s", __func__); 1557 1558 if (ring->use_doorbell) { 1559 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1560 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1561 } else { 1562 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1563 lower_32_bits(ring->wptr)); 1564 } 1565 } 1566 1567 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1568 .type = AMDGPU_RING_TYPE_VCN_ENC, 1569 .align_mask = 0x3f, 1570 .nop = VCN_ENC_CMD_NO_OP, 1571 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1572 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1573 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1574 .emit_frame_size = 1575 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1576 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1577 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1578 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1579 1, /* vcn_v2_0_enc_ring_insert_end */ 1580 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1581 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1582 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1583 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1584 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1585 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1586 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1587 .insert_nop = amdgpu_ring_insert_nop, 1588 .insert_end = vcn_v2_0_enc_ring_insert_end, 1589 .pad_ib = amdgpu_ring_generic_pad_ib, 1590 .begin_use = amdgpu_vcn_ring_begin_use, 1591 .end_use = amdgpu_vcn_ring_end_use, 1592 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1593 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1594 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1595 }; 1596 1597 /** 1598 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1599 * 1600 * @adev: amdgpu_device pointer 1601 * 1602 * Set unified ring functions 1603 */ 1604 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1605 { 1606 int i, vcn_inst; 1607 1608 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1609 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1610 adev->vcn.inst[i].ring_enc[0].me = i; 1611 vcn_inst = GET_INST(VCN, i); 1612 adev->vcn.inst[i].aid_id = 1613 vcn_inst / adev->vcn.num_inst_per_aid; 1614 } 1615 } 1616 1617 /** 1618 * vcn_v4_0_3_is_idle - check VCN block is idle 1619 * 1620 * @ip_block: Pointer to the amdgpu_ip_block structure 1621 * 1622 * Check whether VCN block is idle 1623 */ 1624 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1625 { 1626 struct amdgpu_device *adev = ip_block->adev; 1627 int i, ret = 1; 1628 1629 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1630 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1631 UVD_STATUS__IDLE); 1632 } 1633 1634 return ret; 1635 } 1636 1637 /** 1638 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1639 * 1640 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1641 * 1642 * Wait for VCN block idle 1643 */ 1644 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1645 { 1646 struct amdgpu_device *adev = ip_block->adev; 1647 int i, ret = 0; 1648 1649 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1650 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1651 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1652 if (ret) 1653 return ret; 1654 } 1655 1656 return ret; 1657 } 1658 1659 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1660 * 1661 * @ip_block: amdgpu_ip_block pointer 1662 * @state: clock gating state 1663 * 1664 * Set VCN block clockgating state 1665 */ 1666 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1667 enum amd_clockgating_state state) 1668 { 1669 struct amdgpu_device *adev = ip_block->adev; 1670 bool enable = state == AMD_CG_STATE_GATE; 1671 int i; 1672 1673 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1674 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1675 1676 if (enable) { 1677 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1678 regUVD_STATUS) != UVD_STATUS__IDLE) 1679 return -EBUSY; 1680 vcn_v4_0_3_enable_clock_gating(vinst); 1681 } else { 1682 vcn_v4_0_3_disable_clock_gating(vinst); 1683 } 1684 } 1685 return 0; 1686 } 1687 1688 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1689 enum amd_powergating_state state) 1690 { 1691 struct amdgpu_device *adev = vinst->adev; 1692 int ret = 0; 1693 1694 /* for SRIOV, guest should not control VCN Power-gating 1695 * MMSCH FW should control Power-gating and clock-gating 1696 * guest should avoid touching CGC and PG 1697 */ 1698 if (amdgpu_sriov_vf(adev)) { 1699 vinst->cur_state = AMD_PG_STATE_UNGATE; 1700 return 0; 1701 } 1702 1703 if (state == vinst->cur_state) 1704 return 0; 1705 1706 if (state == AMD_PG_STATE_GATE) 1707 ret = vcn_v4_0_3_stop(vinst); 1708 else 1709 ret = vcn_v4_0_3_start(vinst); 1710 1711 if (!ret) 1712 vinst->cur_state = state; 1713 1714 return ret; 1715 } 1716 1717 /** 1718 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1719 * 1720 * @adev: amdgpu_device pointer 1721 * @source: interrupt sources 1722 * @type: interrupt types 1723 * @state: interrupt states 1724 * 1725 * Set VCN block interrupt state 1726 */ 1727 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1728 struct amdgpu_irq_src *source, 1729 unsigned int type, 1730 enum amdgpu_interrupt_state state) 1731 { 1732 return 0; 1733 } 1734 1735 /** 1736 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1737 * 1738 * @adev: amdgpu_device pointer 1739 * @source: interrupt sources 1740 * @entry: interrupt entry from clients and sources 1741 * 1742 * Process VCN block interrupt 1743 */ 1744 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1745 struct amdgpu_irq_src *source, 1746 struct amdgpu_iv_entry *entry) 1747 { 1748 uint32_t i, inst; 1749 1750 i = node_id_to_phys_map[entry->node_id]; 1751 1752 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1753 1754 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1755 if (adev->vcn.inst[inst].aid_id == i) 1756 break; 1757 1758 if (inst >= adev->vcn.num_vcn_inst) { 1759 dev_WARN_ONCE(adev->dev, 1, 1760 "Interrupt received for unknown VCN instance %d", 1761 entry->node_id); 1762 return 0; 1763 } 1764 1765 switch (entry->src_id) { 1766 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1767 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1768 break; 1769 default: 1770 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1771 entry->src_id, entry->src_data[0]); 1772 break; 1773 } 1774 1775 return 0; 1776 } 1777 1778 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1779 .set = vcn_v4_0_3_set_interrupt_state, 1780 .process = vcn_v4_0_3_process_interrupt, 1781 }; 1782 1783 /** 1784 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1785 * 1786 * @adev: amdgpu_device pointer 1787 * 1788 * Set VCN block interrupt irq functions 1789 */ 1790 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1791 { 1792 int i; 1793 1794 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1795 adev->vcn.inst->irq.num_types++; 1796 } 1797 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1798 } 1799 1800 static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1801 { 1802 struct amdgpu_device *adev = ip_block->adev; 1803 int i, j; 1804 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1805 uint32_t inst_off, is_powered; 1806 1807 if (!adev->vcn.ip_dump) 1808 return; 1809 1810 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1811 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1812 if (adev->vcn.harvest_config & (1 << i)) { 1813 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1814 continue; 1815 } 1816 1817 inst_off = i * reg_count; 1818 is_powered = (adev->vcn.ip_dump[inst_off] & 1819 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1820 1821 if (is_powered) { 1822 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1823 for (j = 0; j < reg_count; j++) 1824 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, 1825 adev->vcn.ip_dump[inst_off + j]); 1826 } else { 1827 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1828 } 1829 } 1830 } 1831 1832 static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) 1833 { 1834 struct amdgpu_device *adev = ip_block->adev; 1835 int i, j; 1836 bool is_powered; 1837 uint32_t inst_off, inst_id; 1838 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); 1839 1840 if (!adev->vcn.ip_dump) 1841 return; 1842 1843 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1844 if (adev->vcn.harvest_config & (1 << i)) 1845 continue; 1846 1847 inst_id = GET_INST(VCN, i); 1848 inst_off = i * reg_count; 1849 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1850 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); 1851 is_powered = (adev->vcn.ip_dump[inst_off] & 1852 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1853 1854 if (is_powered) 1855 for (j = 1; j < reg_count; j++) 1856 adev->vcn.ip_dump[inst_off + j] = 1857 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], 1858 inst_id)); 1859 } 1860 } 1861 1862 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1863 .name = "vcn_v4_0_3", 1864 .early_init = vcn_v4_0_3_early_init, 1865 .sw_init = vcn_v4_0_3_sw_init, 1866 .sw_fini = vcn_v4_0_3_sw_fini, 1867 .hw_init = vcn_v4_0_3_hw_init, 1868 .hw_fini = vcn_v4_0_3_hw_fini, 1869 .suspend = vcn_v4_0_3_suspend, 1870 .resume = vcn_v4_0_3_resume, 1871 .is_idle = vcn_v4_0_3_is_idle, 1872 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1873 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1874 .set_powergating_state = vcn_set_powergating_state, 1875 .dump_ip_state = vcn_v4_0_3_dump_ip_state, 1876 .print_ip_state = vcn_v4_0_3_print_ip_state, 1877 }; 1878 1879 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1880 .type = AMD_IP_BLOCK_TYPE_VCN, 1881 .major = 4, 1882 .minor = 0, 1883 .rev = 3, 1884 .funcs = &vcn_v4_0_3_ip_funcs, 1885 }; 1886 1887 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1888 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1889 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1890 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1891 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1892 }; 1893 1894 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1895 uint32_t vcn_inst, 1896 void *ras_err_status) 1897 { 1898 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1899 1900 /* vcn v4_0_3 only support query uncorrectable errors */ 1901 amdgpu_ras_inst_query_ras_error_count(adev, 1902 vcn_v4_0_3_ue_reg_list, 1903 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1904 NULL, 0, GET_INST(VCN, vcn_inst), 1905 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1906 &err_data->ue_count); 1907 } 1908 1909 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1910 void *ras_err_status) 1911 { 1912 uint32_t i; 1913 1914 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1915 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1916 return; 1917 } 1918 1919 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1920 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1921 } 1922 1923 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1924 uint32_t vcn_inst) 1925 { 1926 amdgpu_ras_inst_reset_ras_error_count(adev, 1927 vcn_v4_0_3_ue_reg_list, 1928 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1929 GET_INST(VCN, vcn_inst)); 1930 } 1931 1932 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1933 { 1934 uint32_t i; 1935 1936 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1937 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1938 return; 1939 } 1940 1941 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1942 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1943 } 1944 1945 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1946 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1947 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1948 }; 1949 1950 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1951 enum aca_smu_type type, void *data) 1952 { 1953 struct aca_bank_info info; 1954 u64 misc0; 1955 int ret; 1956 1957 ret = aca_bank_info_decode(bank, &info); 1958 if (ret) 1959 return ret; 1960 1961 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 1962 switch (type) { 1963 case ACA_SMU_TYPE_UE: 1964 bank->aca_err_type = ACA_ERROR_TYPE_UE; 1965 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 1966 1ULL); 1967 break; 1968 case ACA_SMU_TYPE_CE: 1969 bank->aca_err_type = ACA_ERROR_TYPE_CE; 1970 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1971 ACA_REG__MISC0__ERRCNT(misc0)); 1972 break; 1973 default: 1974 return -EINVAL; 1975 } 1976 1977 return ret; 1978 } 1979 1980 /* reference to smu driver if header file */ 1981 static int vcn_v4_0_3_err_codes[] = { 1982 14, 15, /* VCN */ 1983 }; 1984 1985 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 1986 enum aca_smu_type type, void *data) 1987 { 1988 u32 instlo; 1989 1990 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 1991 instlo &= GENMASK(31, 1); 1992 1993 if (instlo != mmSMNAID_AID0_MCA_SMU) 1994 return false; 1995 1996 if (aca_bank_check_error_codes(handle->adev, bank, 1997 vcn_v4_0_3_err_codes, 1998 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 1999 return false; 2000 2001 return true; 2002 } 2003 2004 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2005 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2006 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2007 }; 2008 2009 static const struct aca_info vcn_v4_0_3_aca_info = { 2010 .hwip = ACA_HWIP_TYPE_SMU, 2011 .mask = ACA_ERROR_UE_MASK, 2012 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2013 }; 2014 2015 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2016 { 2017 int r; 2018 2019 r = amdgpu_ras_block_late_init(adev, ras_block); 2020 if (r) 2021 return r; 2022 2023 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2024 &vcn_v4_0_3_aca_info, NULL); 2025 if (r) 2026 goto late_fini; 2027 2028 return 0; 2029 2030 late_fini: 2031 amdgpu_ras_block_late_fini(adev, ras_block); 2032 2033 return r; 2034 } 2035 2036 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2037 .ras_block = { 2038 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2039 .ras_late_init = vcn_v4_0_3_ras_late_init, 2040 }, 2041 }; 2042 2043 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2044 { 2045 adev->vcn.ras = &vcn_v4_0_3_ras; 2046 } 2047 2048 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2049 int inst_idx, bool indirect) 2050 { 2051 uint32_t tmp; 2052 2053 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2054 return; 2055 2056 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2057 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2058 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2059 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2060 WREG32_SOC15_DPG_MODE(inst_idx, 2061 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2062 tmp, 0, indirect); 2063 2064 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2065 WREG32_SOC15_DPG_MODE(inst_idx, 2066 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2067 tmp, 0, indirect); 2068 2069 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2070 WREG32_SOC15_DPG_MODE(inst_idx, 2071 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2072 tmp, 0, indirect); 2073 } 2074