1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_hw_ip.h" 33 #include "vcn_v2_0.h" 34 #include "vcn_v4_0_3.h" 35 #include "mmsch_v4_0_3.h" 36 37 #include "vcn/vcn_4_0_3_offset.h" 38 #include "vcn/vcn_4_0_3_sh_mask.h" 39 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 40 41 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 42 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 43 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 44 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 45 46 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 47 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 48 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 49 50 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { 51 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 53 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 54 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 55 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 84 }; 85 86 #define NORMALIZE_VCN_REG_OFFSET(offset) \ 87 (offset & 0x1FFFF) 88 89 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev); 90 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev); 91 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev); 92 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 93 enum amd_powergating_state state); 94 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 95 struct dpg_pause_state *new_state); 96 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring); 97 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 99 int inst_idx, bool indirect); 100 101 static inline bool vcn_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) 102 { 103 return (adev->vcn.caps & AMDGPU_VCN_CAPS(RRMT_ENABLED)) == 0; 104 } 105 106 /** 107 * vcn_v4_0_3_early_init - set function pointers 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 */ 113 static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) 114 { 115 struct amdgpu_device *adev = ip_block->adev; 116 int i, r; 117 118 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) 119 /* re-use enc ring as unified ring */ 120 adev->vcn.inst[i].num_enc_rings = 1; 121 122 vcn_v4_0_3_set_unified_ring_funcs(adev); 123 vcn_v4_0_3_set_irq_funcs(adev); 124 vcn_v4_0_3_set_ras_funcs(adev); 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 127 adev->vcn.inst[i].set_pg_state = vcn_v4_0_3_set_pg_state; 128 129 r = amdgpu_vcn_early_init(adev, i); 130 if (r) 131 return r; 132 } 133 134 return 0; 135 } 136 137 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 138 { 139 struct amdgpu_vcn4_fw_shared *fw_shared; 140 141 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 142 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 143 fw_shared->sq.is_enabled = 1; 144 145 if (amdgpu_vcnfw_log) 146 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 147 148 return 0; 149 } 150 151 /** 152 * vcn_v4_0_3_sw_init - sw init for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * Load firmware and sw initialization 157 */ 158 static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_device *adev = ip_block->adev; 161 struct amdgpu_ring *ring; 162 int i, r, vcn_inst; 163 164 /* VCN DEC TRAP */ 165 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 166 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); 167 if (r) 168 return r; 169 170 /* VCN POISON TRAP */ 171 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 172 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst->ras_poison_irq); 173 174 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 175 176 r = amdgpu_vcn_sw_init(adev, i); 177 if (r) 178 return r; 179 180 amdgpu_vcn_setup_ucode(adev, i); 181 182 r = amdgpu_vcn_resume(adev, i); 183 if (r) 184 return r; 185 186 vcn_inst = GET_INST(VCN, i); 187 188 ring = &adev->vcn.inst[i].ring_enc[0]; 189 ring->use_doorbell = true; 190 191 if (!amdgpu_sriov_vf(adev)) 192 ring->doorbell_index = 193 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 194 9 * vcn_inst; 195 else 196 ring->doorbell_index = 197 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 198 32 * vcn_inst; 199 200 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); 201 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); 202 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 203 AMDGPU_RING_PRIO_DEFAULT, 204 &adev->vcn.inst[i].sched_score); 205 if (r) 206 return r; 207 208 vcn_v4_0_3_fw_shared_init(adev, i); 209 210 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 211 adev->vcn.inst[i].pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode; 212 } 213 214 /* TODO: Add queue reset mask when FW fully supports it */ 215 adev->vcn.supported_reset = 216 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 217 218 if (amdgpu_sriov_vf(adev)) { 219 r = amdgpu_virt_alloc_mm_table(adev); 220 if (r) 221 return r; 222 } 223 224 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 225 r = amdgpu_vcn_ras_sw_init(adev); 226 if (r) { 227 dev_err(adev->dev, "Failed to initialize vcn ras block!\n"); 228 return r; 229 } 230 } 231 232 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3)); 233 if (r) 234 return r; 235 236 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 237 if (r) 238 return r; 239 240 return 0; 241 } 242 243 /** 244 * vcn_v4_0_3_sw_fini - sw fini for VCN block 245 * 246 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 247 * 248 * VCN suspend and free up sw allocation 249 */ 250 static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) 251 { 252 struct amdgpu_device *adev = ip_block->adev; 253 int i, r, idx; 254 255 if (drm_dev_enter(&adev->ddev, &idx)) { 256 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 257 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 258 259 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 260 fw_shared->present_flag_0 = 0; 261 fw_shared->sq.is_enabled = cpu_to_le32(false); 262 } 263 drm_dev_exit(idx); 264 } 265 266 if (amdgpu_sriov_vf(adev)) 267 amdgpu_virt_free_mm_table(adev); 268 269 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 270 r = amdgpu_vcn_suspend(adev, i); 271 if (r) 272 return r; 273 } 274 275 amdgpu_vcn_sysfs_reset_mask_fini(adev); 276 277 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 278 r = amdgpu_vcn_sw_fini(adev, i); 279 if (r) 280 return r; 281 } 282 283 kfree(adev->vcn.ip_dump); 284 285 return 0; 286 } 287 288 static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst) 289 { 290 int vcn_inst; 291 struct amdgpu_device *adev = vinst->adev; 292 struct amdgpu_ring *ring; 293 int inst_idx = vinst->inst; 294 295 vcn_inst = GET_INST(VCN, inst_idx); 296 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 297 if (ring->use_doorbell) { 298 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 299 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst, 300 adev->vcn.inst[inst_idx].aid_id); 301 302 WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, 303 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 304 VCN_RB1_DB_CTRL__EN_MASK); 305 306 /* Read DB_CTRL to flush the write DB_CTRL command. */ 307 RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); 308 } 309 310 return 0; 311 } 312 313 /** 314 * vcn_v4_0_3_hw_init - start and test VCN block 315 * 316 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 317 * 318 * Initialize the hardware, boot up the VCPU and do some testing 319 */ 320 static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) 321 { 322 struct amdgpu_device *adev = ip_block->adev; 323 struct amdgpu_ring *ring; 324 struct amdgpu_vcn_inst *vinst; 325 int i, r; 326 327 if (amdgpu_sriov_vf(adev)) { 328 r = vcn_v4_0_3_start_sriov(adev); 329 if (r) 330 return r; 331 332 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 333 ring = &adev->vcn.inst[i].ring_enc[0]; 334 ring->wptr = 0; 335 ring->wptr_old = 0; 336 vcn_v4_0_3_unified_ring_set_wptr(ring); 337 ring->sched.ready = true; 338 } 339 } else { 340 /* This flag is not set for VF, assumed to be disabled always */ 341 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 342 0x100) 343 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 344 345 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 346 struct amdgpu_vcn4_fw_shared *fw_shared; 347 348 ring = &adev->vcn.inst[i].ring_enc[0]; 349 vinst = &adev->vcn.inst[i]; 350 vcn_v4_0_3_hw_init_inst(vinst); 351 352 /* Re-init fw_shared when RAS fatal error occurred */ 353 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 354 if (!fw_shared->sq.is_enabled) 355 vcn_v4_0_3_fw_shared_init(adev, i); 356 357 r = amdgpu_ring_test_helper(ring); 358 if (r) 359 return r; 360 } 361 } 362 363 return r; 364 } 365 366 /** 367 * vcn_v4_0_3_hw_fini - stop the hardware block 368 * 369 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 370 * 371 * Stop the VCN block, mark ring as not ready any more 372 */ 373 static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) 374 { 375 struct amdgpu_device *adev = ip_block->adev; 376 int i; 377 378 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 379 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 380 381 cancel_delayed_work_sync(&vinst->idle_work); 382 383 if (vinst->cur_state != AMD_PG_STATE_GATE) 384 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 385 } 386 387 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN) && !amdgpu_sriov_vf(adev)) 388 amdgpu_irq_put(adev, &adev->vcn.inst->ras_poison_irq, 0); 389 390 return 0; 391 } 392 393 /** 394 * vcn_v4_0_3_suspend - suspend VCN block 395 * 396 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 397 * 398 * HW fini and suspend VCN block 399 */ 400 static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) 401 { 402 struct amdgpu_device *adev = ip_block->adev; 403 int r, i; 404 405 r = vcn_v4_0_3_hw_fini(ip_block); 406 if (r) 407 return r; 408 409 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 410 r = amdgpu_vcn_suspend(adev, i); 411 if (r) 412 return r; 413 } 414 415 return 0; 416 } 417 418 /** 419 * vcn_v4_0_3_resume - resume VCN block 420 * 421 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 422 * 423 * Resume firmware and hw init VCN block 424 */ 425 static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) 426 { 427 struct amdgpu_device *adev = ip_block->adev; 428 int r, i; 429 430 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 431 r = amdgpu_vcn_resume(ip_block->adev, i); 432 if (r) 433 return r; 434 } 435 436 r = vcn_v4_0_3_hw_init(ip_block); 437 438 return r; 439 } 440 441 /** 442 * vcn_v4_0_3_mc_resume - memory controller programming 443 * 444 * @vinst: VCN instance 445 * 446 * Let the VCN memory controller know it's offsets 447 */ 448 static void vcn_v4_0_3_mc_resume(struct amdgpu_vcn_inst *vinst) 449 { 450 struct amdgpu_device *adev = vinst->adev; 451 int inst_idx = vinst->inst; 452 uint32_t offset, size, vcn_inst; 453 const struct common_firmware_header *hdr; 454 455 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 456 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 457 458 vcn_inst = GET_INST(VCN, inst_idx); 459 /* cache window 0: fw */ 460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 461 WREG32_SOC15( 462 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 463 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 464 .tmr_mc_addr_lo)); 465 WREG32_SOC15( 466 VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 467 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx] 468 .tmr_mc_addr_hi)); 469 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); 470 offset = 0; 471 } else { 472 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 473 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 474 WREG32_SOC15(VCN, vcn_inst, 475 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 476 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr)); 477 offset = size; 478 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 479 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 480 } 481 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); 482 483 /* cache window 1: stack */ 484 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 486 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 487 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset)); 488 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); 489 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, 490 AMDGPU_VCN_STACK_SIZE); 491 492 /* cache window 2: context */ 493 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 494 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 495 AMDGPU_VCN_STACK_SIZE)); 496 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 497 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 498 AMDGPU_VCN_STACK_SIZE)); 499 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); 500 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, 501 AMDGPU_VCN_CONTEXT_SIZE); 502 503 /* non-cache window */ 504 WREG32_SOC15( 505 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 506 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 507 WREG32_SOC15( 508 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 509 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr)); 510 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 511 WREG32_SOC15( 512 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, 513 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 514 } 515 516 /** 517 * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode 518 * 519 * @vinst: VCN instance 520 * @indirect: indirectly write sram 521 * 522 * Let the VCN memory controller know it's offsets with dpg mode 523 */ 524 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 525 bool indirect) 526 { 527 struct amdgpu_device *adev = vinst->adev; 528 int inst_idx = vinst->inst; 529 uint32_t offset, size; 530 const struct common_firmware_header *hdr; 531 532 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 533 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 534 535 /* cache window 0: fw */ 536 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 537 if (!indirect) { 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 540 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 541 inst_idx].tmr_mc_addr_lo), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 544 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + 545 inst_idx].tmr_mc_addr_hi), 0, indirect); 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 548 } else { 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 551 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 552 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 553 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 554 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 555 } 556 offset = 0; 557 } else { 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 560 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 561 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 562 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 563 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 564 offset = size; 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 567 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 568 } 569 570 if (!indirect) 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 573 else 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 576 577 /* cache window 1: stack */ 578 if (!indirect) { 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 581 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 582 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 583 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 584 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 587 } else { 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 590 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 591 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 594 } 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 597 598 /* cache window 2: context */ 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 600 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 601 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 602 AMDGPU_VCN_STACK_SIZE), 0, indirect); 603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 604 VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 605 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + 606 AMDGPU_VCN_STACK_SIZE), 0, indirect); 607 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 608 VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 609 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 610 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 611 612 /* non-cache window */ 613 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 614 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 615 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 617 VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 618 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 621 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 622 VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), 623 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 624 625 /* VCN global tiling registers */ 626 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 627 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 629 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 630 } 631 632 /** 633 * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating 634 * 635 * @vinst: VCN instance 636 * 637 * Disable clock gating for VCN block 638 */ 639 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 640 { 641 struct amdgpu_device *adev = vinst->adev; 642 int inst_idx = vinst->inst; 643 uint32_t data; 644 int vcn_inst; 645 646 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 647 return; 648 649 vcn_inst = GET_INST(VCN, inst_idx); 650 651 /* VCN disable CGC */ 652 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 653 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 654 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 655 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 656 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 657 658 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE); 659 data &= ~(UVD_CGC_GATE__SYS_MASK 660 | UVD_CGC_GATE__MPEG2_MASK 661 | UVD_CGC_GATE__REGS_MASK 662 | UVD_CGC_GATE__RBC_MASK 663 | UVD_CGC_GATE__LMI_MC_MASK 664 | UVD_CGC_GATE__LMI_UMC_MASK 665 | UVD_CGC_GATE__MPC_MASK 666 | UVD_CGC_GATE__LBSI_MASK 667 | UVD_CGC_GATE__LRBBM_MASK 668 | UVD_CGC_GATE__WCB_MASK 669 | UVD_CGC_GATE__VCPU_MASK 670 | UVD_CGC_GATE__MMSCH_MASK); 671 672 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data); 673 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 674 675 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 676 data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK 677 | UVD_CGC_CTRL__MPEG2_MODE_MASK 678 | UVD_CGC_CTRL__REGS_MODE_MASK 679 | UVD_CGC_CTRL__RBC_MODE_MASK 680 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 681 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 682 | UVD_CGC_CTRL__MPC_MODE_MASK 683 | UVD_CGC_CTRL__LBSI_MODE_MASK 684 | UVD_CGC_CTRL__LRBBM_MODE_MASK 685 | UVD_CGC_CTRL__WCB_MODE_MASK 686 | UVD_CGC_CTRL__VCPU_MODE_MASK 687 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 688 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 689 690 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE); 691 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 692 | UVD_SUVD_CGC_GATE__SIT_MASK 693 | UVD_SUVD_CGC_GATE__SMP_MASK 694 | UVD_SUVD_CGC_GATE__SCM_MASK 695 | UVD_SUVD_CGC_GATE__SDB_MASK 696 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 697 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 698 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 699 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 700 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 701 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 702 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 703 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 704 | UVD_SUVD_CGC_GATE__ENT_MASK 705 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 706 | UVD_SUVD_CGC_GATE__SITE_MASK 707 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 708 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 709 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 710 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 711 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 712 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data); 713 714 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 715 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 716 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 717 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 718 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 721 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 722 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 723 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 724 } 725 726 /** 727 * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 728 * 729 * @vinst: VCN instance 730 * @sram_sel: sram select 731 * @indirect: indirectly write sram 732 * 733 * Disable clock gating for VCN block with dpg mode 734 */ 735 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 736 uint8_t sram_sel, 737 uint8_t indirect) 738 { 739 struct amdgpu_device *adev = vinst->adev; 740 int inst_idx = vinst->inst; 741 uint32_t reg_data = 0; 742 743 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 744 return; 745 746 /* enable sw clock gating control */ 747 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 748 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 749 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 750 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | 751 UVD_CGC_CTRL__MPEG2_MODE_MASK | 752 UVD_CGC_CTRL__REGS_MODE_MASK | 753 UVD_CGC_CTRL__RBC_MODE_MASK | 754 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 755 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 756 UVD_CGC_CTRL__IDCT_MODE_MASK | 757 UVD_CGC_CTRL__MPRD_MODE_MASK | 758 UVD_CGC_CTRL__MPC_MODE_MASK | 759 UVD_CGC_CTRL__LBSI_MODE_MASK | 760 UVD_CGC_CTRL__LRBBM_MODE_MASK | 761 UVD_CGC_CTRL__WCB_MODE_MASK | 762 UVD_CGC_CTRL__VCPU_MODE_MASK); 763 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 764 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 765 766 /* turn off clock gating */ 767 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 768 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect); 769 770 /* turn on SUVD clock gating */ 771 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 772 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 773 774 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 775 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 776 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 777 } 778 779 /** 780 * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating 781 * 782 * @vinst: VCN instance 783 * 784 * Enable clock gating for VCN block 785 */ 786 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 787 { 788 struct amdgpu_device *adev = vinst->adev; 789 int inst_idx = vinst->inst; 790 uint32_t data; 791 int vcn_inst; 792 793 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 794 return; 795 796 vcn_inst = GET_INST(VCN, inst_idx); 797 798 /* enable VCN CGC */ 799 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 800 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 801 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 802 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 803 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 804 805 data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL); 806 data |= (UVD_CGC_CTRL__SYS_MODE_MASK 807 | UVD_CGC_CTRL__MPEG2_MODE_MASK 808 | UVD_CGC_CTRL__REGS_MODE_MASK 809 | UVD_CGC_CTRL__RBC_MODE_MASK 810 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 811 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 812 | UVD_CGC_CTRL__MPC_MODE_MASK 813 | UVD_CGC_CTRL__LBSI_MODE_MASK 814 | UVD_CGC_CTRL__LRBBM_MODE_MASK 815 | UVD_CGC_CTRL__WCB_MODE_MASK 816 | UVD_CGC_CTRL__VCPU_MODE_MASK); 817 WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data); 818 819 data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL); 820 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 828 WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data); 829 } 830 831 /** 832 * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode 833 * 834 * @vinst: VCN instance 835 * @indirect: indirectly write sram 836 * 837 * Start VCN block with dpg mode 838 */ 839 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, 840 bool indirect) 841 { 842 struct amdgpu_device *adev = vinst->adev; 843 int inst_idx = vinst->inst; 844 volatile struct amdgpu_vcn4_fw_shared *fw_shared = 845 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 846 struct amdgpu_ring *ring; 847 int vcn_inst, ret; 848 uint32_t tmp; 849 850 vcn_inst = GET_INST(VCN, inst_idx); 851 /* disable register anti-hang mechanism */ 852 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, 853 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 854 /* enable dynamic power gating mode */ 855 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); 856 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 857 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 858 WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); 859 860 if (indirect) { 861 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d", 862 inst_idx, adev->vcn.inst[inst_idx].aid_id); 863 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = 864 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 865 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ 866 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF, 867 adev->vcn.inst[inst_idx].aid_id, 0, true); 868 } 869 870 /* enable clock gating */ 871 vcn_v4_0_3_disable_clock_gating_dpg_mode(vinst, 0, indirect); 872 873 /* enable VCPU clock */ 874 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 875 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 876 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 877 878 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 879 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 880 881 /* disable master interrupt */ 882 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 883 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); 884 885 /* setup regUVD_LMI_CTRL */ 886 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 887 UVD_LMI_CTRL__REQ_MODE_MASK | 888 UVD_LMI_CTRL__CRC_RESET_MASK | 889 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 890 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 891 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 892 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 893 0x00100000L); 894 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 895 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); 896 897 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 898 VCN, 0, regUVD_MPC_CNTL), 899 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 900 901 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 902 VCN, 0, regUVD_MPC_SET_MUXA0), 903 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 904 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 905 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 906 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 907 908 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 909 VCN, 0, regUVD_MPC_SET_MUXB0), 910 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 911 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 912 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 913 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 914 915 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 916 VCN, 0, regUVD_MPC_SET_MUX), 917 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 918 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 919 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 920 921 vcn_v4_0_3_mc_resume_dpg_mode(vinst, indirect); 922 923 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 924 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 925 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 926 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); 927 928 /* enable LMI MC and UMC channels */ 929 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 930 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 931 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); 932 933 vcn_v4_0_3_enable_ras(adev, inst_idx, indirect); 934 935 /* enable master interrupt */ 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, 0, regUVD_MASTINT_EN), 938 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 939 940 if (indirect) { 941 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 942 if (ret) { 943 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 944 return ret; 945 } 946 } 947 948 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 949 950 /* program the RB_BASE for ring buffer */ 951 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 952 lower_32_bits(ring->gpu_addr)); 953 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 954 upper_32_bits(ring->gpu_addr)); 955 956 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 957 ring->ring_size / sizeof(uint32_t)); 958 959 /* resetting ring, fw should not check RB ring */ 960 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 961 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 962 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 963 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 964 965 /* Initialize the ring buffer's read and write pointers */ 966 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 967 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 968 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 969 970 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 971 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 972 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 973 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 974 975 /*resetting done, fw can check RB ring */ 976 fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 977 978 /* Keeping one read-back to ensure all register writes are done, 979 * otherwise it may introduce race conditions. 980 */ 981 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 982 983 return 0; 984 } 985 986 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev) 987 { 988 int i, vcn_inst; 989 struct amdgpu_ring *ring_enc; 990 uint64_t cache_addr; 991 uint64_t rb_enc_addr; 992 uint64_t ctx_addr; 993 uint32_t param, resp, expected; 994 uint32_t offset, cache_size; 995 uint32_t tmp, timeout; 996 997 struct amdgpu_mm_table *table = &adev->virt.mm_table; 998 uint32_t *table_loc; 999 uint32_t table_size; 1000 uint32_t size, size_dw; 1001 uint32_t init_status; 1002 uint32_t enabled_vcn; 1003 1004 struct mmsch_v4_0_cmd_direct_write 1005 direct_wt = { {0} }; 1006 struct mmsch_v4_0_cmd_direct_read_modify_write 1007 direct_rd_mod_wt = { {0} }; 1008 struct mmsch_v4_0_cmd_end end = { {0} }; 1009 struct mmsch_v4_0_3_init_header header; 1010 1011 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1012 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1013 1014 direct_wt.cmd_header.command_type = 1015 MMSCH_COMMAND__DIRECT_REG_WRITE; 1016 direct_rd_mod_wt.cmd_header.command_type = 1017 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1018 end.cmd_header.command_type = MMSCH_COMMAND__END; 1019 1020 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1021 vcn_inst = GET_INST(VCN, i); 1022 1023 vcn_v4_0_3_fw_shared_init(adev, vcn_inst); 1024 1025 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header)); 1026 header.version = MMSCH_VERSION; 1027 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2; 1028 1029 table_loc = (uint32_t *)table->cpu_addr; 1030 table_loc += header.total_size; 1031 1032 table_size = 0; 1033 1034 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), 1035 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1036 1037 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1038 1039 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1040 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1041 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1042 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1043 1044 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1045 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1046 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1047 1048 offset = 0; 1049 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1050 regUVD_VCPU_CACHE_OFFSET0), 0); 1051 } else { 1052 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1053 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1054 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1055 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1056 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1057 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1058 offset = cache_size; 1059 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1060 regUVD_VCPU_CACHE_OFFSET0), 1061 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1062 } 1063 1064 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1065 regUVD_VCPU_CACHE_SIZE0), 1066 cache_size); 1067 1068 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset; 1069 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1070 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1071 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1072 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1073 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1074 regUVD_VCPU_CACHE_OFFSET1), 0); 1075 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1076 regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); 1077 1078 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset + 1079 AMDGPU_VCN_STACK_SIZE; 1080 1081 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1082 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr)); 1083 1084 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1085 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr)); 1086 1087 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1088 regUVD_VCPU_CACHE_OFFSET2), 0); 1089 1090 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1091 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); 1092 1093 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr; 1094 rb_setup = &fw_shared->rb_setup; 1095 1096 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0]; 1097 ring_enc->wptr = 0; 1098 rb_enc_addr = ring_enc->gpu_addr; 1099 1100 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1101 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1102 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1103 rb_setup->rb_size = ring_enc->ring_size / 4; 1104 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1105 1106 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1107 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1108 lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1109 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1110 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1111 upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr)); 1112 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0, 1113 regUVD_VCPU_NONCACHE_SIZE0), 1114 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1115 MMSCH_V4_0_INSERT_END(); 1116 1117 header.vcn0.init_status = 0; 1118 header.vcn0.table_offset = header.total_size; 1119 header.vcn0.table_size = table_size; 1120 header.total_size += table_size; 1121 1122 /* Send init table to mmsch */ 1123 size = sizeof(struct mmsch_v4_0_3_init_header); 1124 table_loc = (uint32_t *)table->cpu_addr; 1125 memcpy((void *)table_loc, &header, size); 1126 1127 ctx_addr = table->gpu_addr; 1128 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1129 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1130 1131 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID); 1132 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1133 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1134 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp); 1135 1136 size = header.total_size; 1137 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size); 1138 1139 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); 1140 1141 param = 0x00000001; 1142 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param); 1143 tmp = 0; 1144 timeout = 1000; 1145 resp = 0; 1146 expected = MMSCH_VF_MAILBOX_RESP__OK; 1147 while (resp != expected) { 1148 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); 1149 if (resp != 0) 1150 break; 1151 1152 udelay(10); 1153 tmp = tmp + 10; 1154 if (tmp >= timeout) { 1155 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1156 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1157 "(expected=0x%08x, readback=0x%08x)\n", 1158 tmp, expected, resp); 1159 return -EBUSY; 1160 } 1161 } 1162 1163 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1164 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status; 1165 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1166 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) { 1167 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1168 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1169 } 1170 } 1171 1172 return 0; 1173 } 1174 1175 /** 1176 * vcn_v4_0_3_start - VCN start 1177 * 1178 * @vinst: VCN instance 1179 * 1180 * Start VCN block 1181 */ 1182 static int vcn_v4_0_3_start(struct amdgpu_vcn_inst *vinst) 1183 { 1184 struct amdgpu_device *adev = vinst->adev; 1185 int i = vinst->inst; 1186 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1187 struct amdgpu_ring *ring; 1188 int j, k, r, vcn_inst; 1189 uint32_t tmp; 1190 1191 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1192 return vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1193 1194 vcn_inst = GET_INST(VCN, i); 1195 /* set VCN status busy */ 1196 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | 1197 UVD_STATUS__UVD_BUSY; 1198 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); 1199 1200 /* SW clock gating */ 1201 vcn_v4_0_3_disable_clock_gating(vinst); 1202 1203 /* enable VCPU clock */ 1204 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1205 UVD_VCPU_CNTL__CLK_EN_MASK, 1206 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1207 1208 /* disable master interrupt */ 1209 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, 1210 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1211 1212 /* enable LMI MC and UMC channels */ 1213 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, 1214 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1215 1216 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1217 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1218 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1219 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1220 1221 /* setup regUVD_LMI_CTRL */ 1222 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); 1223 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, 1224 tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1225 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1226 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1227 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1228 1229 /* setup regUVD_MPC_CNTL */ 1230 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL); 1231 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1232 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1233 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp); 1234 1235 /* setup UVD_MPC_SET_MUXA0 */ 1236 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0, 1237 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1238 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1239 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1240 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1241 1242 /* setup UVD_MPC_SET_MUXB0 */ 1243 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0, 1244 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1245 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1246 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1247 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1248 1249 /* setup UVD_MPC_SET_MUX */ 1250 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX, 1251 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1252 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1253 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1254 1255 vcn_v4_0_3_mc_resume(vinst); 1256 1257 /* VCN global tiling registers */ 1258 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG, 1259 adev->gfx.config.gb_addr_config); 1260 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, 1261 adev->gfx.config.gb_addr_config); 1262 1263 /* unblock VCPU register access */ 1264 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, 1265 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1266 1267 /* release VCPU reset to boot */ 1268 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1269 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1270 1271 for (j = 0; j < 10; ++j) { 1272 uint32_t status; 1273 1274 for (k = 0; k < 100; ++k) { 1275 status = RREG32_SOC15(VCN, vcn_inst, 1276 regUVD_STATUS); 1277 if (status & 2) 1278 break; 1279 mdelay(10); 1280 } 1281 r = 0; 1282 if (status & 2) 1283 break; 1284 1285 DRM_DEV_ERROR(adev->dev, 1286 "VCN decode not responding, trying to reset the VCPU!!!\n"); 1287 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1288 regUVD_VCPU_CNTL), 1289 UVD_VCPU_CNTL__BLK_RST_MASK, 1290 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1291 mdelay(10); 1292 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, 1293 regUVD_VCPU_CNTL), 1294 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); 1295 1296 mdelay(10); 1297 r = -1; 1298 } 1299 1300 if (r) { 1301 DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n"); 1302 return r; 1303 } 1304 1305 /* enable master interrupt */ 1306 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 1307 UVD_MASTINT_EN__VCPU_EN_MASK, 1308 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1309 1310 /* clear the busy bit of VCN_STATUS */ 1311 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, 1312 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1313 1314 ring = &adev->vcn.inst[i].ring_enc[0]; 1315 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1316 1317 /* program the RB_BASE for ring buffer */ 1318 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, 1319 lower_32_bits(ring->gpu_addr)); 1320 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, 1321 upper_32_bits(ring->gpu_addr)); 1322 1323 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, 1324 ring->ring_size / sizeof(uint32_t)); 1325 1326 /* resetting ring, fw should not check RB ring */ 1327 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1328 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK); 1329 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1330 1331 /* Initialize the ring buffer's read and write pointers */ 1332 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); 1333 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); 1334 1335 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); 1336 tmp |= VCN_RB_ENABLE__RB_EN_MASK; 1337 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); 1338 1339 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1340 fw_shared->sq.queue_mode &= 1341 cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF)); 1342 1343 return 0; 1344 } 1345 1346 /** 1347 * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode 1348 * 1349 * @vinst: VCN instance 1350 * 1351 * Stop VCN block with dpg mode 1352 */ 1353 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1354 { 1355 struct amdgpu_device *adev = vinst->adev; 1356 int inst_idx = vinst->inst; 1357 uint32_t tmp; 1358 int vcn_inst; 1359 1360 vcn_inst = GET_INST(VCN, inst_idx); 1361 1362 /* Wait for power status to be 1 */ 1363 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1364 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1365 1366 /* wait for read ptr to be equal to write ptr */ 1367 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); 1368 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1369 1370 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, 1371 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1372 1373 /* disable dynamic power gating mode */ 1374 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, 1375 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1376 1377 /* Keeping one read-back to ensure all register writes are done, 1378 * otherwise it may introduce race conditions. 1379 */ 1380 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1381 1382 return 0; 1383 } 1384 1385 /** 1386 * vcn_v4_0_3_stop - VCN stop 1387 * 1388 * @vinst: VCN instance 1389 * 1390 * Stop VCN block 1391 */ 1392 static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) 1393 { 1394 struct amdgpu_device *adev = vinst->adev; 1395 int i = vinst->inst; 1396 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1397 int r = 0, vcn_inst; 1398 uint32_t tmp; 1399 1400 vcn_inst = GET_INST(VCN, i); 1401 1402 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1403 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1404 1405 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1406 vcn_v4_0_3_stop_dpg_mode(vinst); 1407 goto Done; 1408 } 1409 1410 /* wait for vcn idle */ 1411 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, 1412 UVD_STATUS__IDLE, 0x7); 1413 if (r) 1414 goto Done; 1415 1416 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1417 UVD_LMI_STATUS__READ_CLEAN_MASK | 1418 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1419 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1420 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1421 tmp); 1422 if (r) 1423 goto Done; 1424 1425 /* stall UMC channel */ 1426 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); 1427 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1428 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); 1429 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1430 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1431 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, 1432 tmp); 1433 if (r) 1434 goto Done; 1435 1436 /* Unblock VCPU Register access */ 1437 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 1438 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1439 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1440 1441 /* release VCPU reset to boot */ 1442 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 1443 UVD_VCPU_CNTL__BLK_RST_MASK, 1444 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1445 1446 /* disable VCPU clock */ 1447 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, 1448 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1449 1450 /* reset LMI UMC/LMI/VCPU */ 1451 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1452 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1453 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1454 1455 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); 1456 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1457 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); 1458 1459 /* clear VCN status */ 1460 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); 1461 1462 /* apply HW clock gating */ 1463 vcn_v4_0_3_enable_clock_gating(vinst); 1464 1465 /* Keeping one read-back to ensure all register writes are done, 1466 * otherwise it may introduce race conditions. 1467 */ 1468 RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); 1469 1470 Done: 1471 return 0; 1472 } 1473 1474 /** 1475 * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode 1476 * 1477 * @vinst: VCN instance 1478 * @new_state: pause state 1479 * 1480 * Pause dpg mode for VCN block 1481 */ 1482 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1483 struct dpg_pause_state *new_state) 1484 { 1485 1486 return 0; 1487 } 1488 1489 /** 1490 * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer 1491 * 1492 * @ring: amdgpu_ring pointer 1493 * 1494 * Returns the current hardware unified read pointer 1495 */ 1496 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring) 1497 { 1498 struct amdgpu_device *adev = ring->adev; 1499 1500 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1501 DRM_ERROR("wrong ring id is identified in %s", __func__); 1502 1503 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); 1504 } 1505 1506 /** 1507 * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer 1508 * 1509 * @ring: amdgpu_ring pointer 1510 * 1511 * Returns the current hardware unified write pointer 1512 */ 1513 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring) 1514 { 1515 struct amdgpu_device *adev = ring->adev; 1516 1517 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1518 DRM_ERROR("wrong ring id is identified in %s", __func__); 1519 1520 if (ring->use_doorbell) 1521 return *ring->wptr_cpu_addr; 1522 else 1523 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), 1524 regUVD_RB_WPTR); 1525 } 1526 1527 void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1528 uint32_t val, uint32_t mask) 1529 { 1530 /* Use normalized offsets when required */ 1531 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1532 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1533 1534 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1535 amdgpu_ring_write(ring, reg << 2); 1536 amdgpu_ring_write(ring, mask); 1537 amdgpu_ring_write(ring, val); 1538 } 1539 1540 void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 1541 uint32_t val) 1542 { 1543 /* Use normalized offsets when required */ 1544 if (vcn_v4_0_3_normalizn_reqd(ring->adev)) 1545 reg = NORMALIZE_VCN_REG_OFFSET(reg); 1546 1547 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1548 amdgpu_ring_write(ring, reg << 2); 1549 amdgpu_ring_write(ring, val); 1550 } 1551 1552 void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1553 unsigned int vmid, uint64_t pd_addr) 1554 { 1555 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1556 1557 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1558 1559 /* wait for reg writes */ 1560 vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1561 vmid * hub->ctx_addr_distance, 1562 lower_32_bits(pd_addr), 0xffffffff); 1563 } 1564 1565 void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1566 { 1567 /* VCN engine access for HDP flush doesn't work when RRMT is enabled. 1568 * This is a workaround to avoid any HDP flush through VCN ring. 1569 */ 1570 } 1571 1572 /** 1573 * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer 1574 * 1575 * @ring: amdgpu_ring pointer 1576 * 1577 * Commits the enc write pointer to the hardware 1578 */ 1579 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) 1580 { 1581 struct amdgpu_device *adev = ring->adev; 1582 1583 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1584 DRM_ERROR("wrong ring id is identified in %s", __func__); 1585 1586 if (ring->use_doorbell) { 1587 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1588 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1589 } else { 1590 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, 1591 lower_32_bits(ring->wptr)); 1592 } 1593 } 1594 1595 static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, 1596 unsigned int vmid, 1597 struct amdgpu_fence *timedout_fence) 1598 { 1599 int r = 0; 1600 int vcn_inst; 1601 struct amdgpu_device *adev = ring->adev; 1602 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; 1603 1604 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 1605 1606 vcn_inst = GET_INST(VCN, ring->me); 1607 r = amdgpu_dpm_reset_vcn(adev, 1 << vcn_inst); 1608 1609 if (r) { 1610 DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); 1611 return r; 1612 } 1613 1614 /* This flag is not set for VF, assumed to be disabled always */ 1615 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) 1616 adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); 1617 vcn_v4_0_3_hw_init_inst(vinst); 1618 vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); 1619 1620 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 1621 } 1622 1623 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { 1624 .type = AMDGPU_RING_TYPE_VCN_ENC, 1625 .align_mask = 0x3f, 1626 .nop = VCN_ENC_CMD_NO_OP, 1627 .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, 1628 .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, 1629 .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, 1630 .emit_frame_size = 1631 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1632 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1633 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1634 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1635 1, /* vcn_v2_0_enc_ring_insert_end */ 1636 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1637 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1638 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1639 .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, 1640 .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, 1641 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1642 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1643 .insert_nop = amdgpu_ring_insert_nop, 1644 .insert_end = vcn_v2_0_enc_ring_insert_end, 1645 .pad_ib = amdgpu_ring_generic_pad_ib, 1646 .begin_use = amdgpu_vcn_ring_begin_use, 1647 .end_use = amdgpu_vcn_ring_end_use, 1648 .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, 1649 .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, 1650 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1651 .reset = vcn_v4_0_3_ring_reset, 1652 }; 1653 1654 /** 1655 * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions 1656 * 1657 * @adev: amdgpu_device pointer 1658 * 1659 * Set unified ring functions 1660 */ 1661 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev) 1662 { 1663 int i, vcn_inst; 1664 1665 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1666 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs; 1667 adev->vcn.inst[i].ring_enc[0].me = i; 1668 vcn_inst = GET_INST(VCN, i); 1669 adev->vcn.inst[i].aid_id = 1670 vcn_inst / adev->vcn.num_inst_per_aid; 1671 } 1672 } 1673 1674 /** 1675 * vcn_v4_0_3_is_idle - check VCN block is idle 1676 * 1677 * @ip_block: Pointer to the amdgpu_ip_block structure 1678 * 1679 * Check whether VCN block is idle 1680 */ 1681 static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block) 1682 { 1683 struct amdgpu_device *adev = ip_block->adev; 1684 int i, ret = 1; 1685 1686 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1687 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == 1688 UVD_STATUS__IDLE); 1689 } 1690 1691 return ret; 1692 } 1693 1694 /** 1695 * vcn_v4_0_3_wait_for_idle - wait for VCN block idle 1696 * 1697 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1698 * 1699 * Wait for VCN block idle 1700 */ 1701 static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 1702 { 1703 struct amdgpu_device *adev = ip_block->adev; 1704 int i, ret = 0; 1705 1706 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1707 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, 1708 UVD_STATUS__IDLE, UVD_STATUS__IDLE); 1709 if (ret) 1710 return ret; 1711 } 1712 1713 return ret; 1714 } 1715 1716 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state 1717 * 1718 * @ip_block: amdgpu_ip_block pointer 1719 * @state: clock gating state 1720 * 1721 * Set VCN block clockgating state 1722 */ 1723 static int vcn_v4_0_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1724 enum amd_clockgating_state state) 1725 { 1726 struct amdgpu_device *adev = ip_block->adev; 1727 bool enable = state == AMD_CG_STATE_GATE; 1728 int i; 1729 1730 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1731 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 1732 1733 if (enable) { 1734 if (RREG32_SOC15(VCN, GET_INST(VCN, i), 1735 regUVD_STATUS) != UVD_STATUS__IDLE) 1736 return -EBUSY; 1737 vcn_v4_0_3_enable_clock_gating(vinst); 1738 } else { 1739 vcn_v4_0_3_disable_clock_gating(vinst); 1740 } 1741 } 1742 return 0; 1743 } 1744 1745 static int vcn_v4_0_3_set_pg_state(struct amdgpu_vcn_inst *vinst, 1746 enum amd_powergating_state state) 1747 { 1748 struct amdgpu_device *adev = vinst->adev; 1749 int ret = 0; 1750 1751 /* for SRIOV, guest should not control VCN Power-gating 1752 * MMSCH FW should control Power-gating and clock-gating 1753 * guest should avoid touching CGC and PG 1754 */ 1755 if (amdgpu_sriov_vf(adev)) { 1756 vinst->cur_state = AMD_PG_STATE_UNGATE; 1757 return 0; 1758 } 1759 1760 if (state == vinst->cur_state) 1761 return 0; 1762 1763 if (state == AMD_PG_STATE_GATE) 1764 ret = vcn_v4_0_3_stop(vinst); 1765 else 1766 ret = vcn_v4_0_3_start(vinst); 1767 1768 if (!ret) 1769 vinst->cur_state = state; 1770 1771 return ret; 1772 } 1773 1774 /** 1775 * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state 1776 * 1777 * @adev: amdgpu_device pointer 1778 * @source: interrupt sources 1779 * @type: interrupt types 1780 * @state: interrupt states 1781 * 1782 * Set VCN block interrupt state 1783 */ 1784 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev, 1785 struct amdgpu_irq_src *source, 1786 unsigned int type, 1787 enum amdgpu_interrupt_state state) 1788 { 1789 return 0; 1790 } 1791 1792 /** 1793 * vcn_v4_0_3_process_interrupt - process VCN block interrupt 1794 * 1795 * @adev: amdgpu_device pointer 1796 * @source: interrupt sources 1797 * @entry: interrupt entry from clients and sources 1798 * 1799 * Process VCN block interrupt 1800 */ 1801 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev, 1802 struct amdgpu_irq_src *source, 1803 struct amdgpu_iv_entry *entry) 1804 { 1805 uint32_t i, inst; 1806 1807 i = node_id_to_phys_map[entry->node_id]; 1808 1809 DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); 1810 1811 for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) 1812 if (adev->vcn.inst[inst].aid_id == i) 1813 break; 1814 1815 if (inst >= adev->vcn.num_vcn_inst) { 1816 dev_WARN_ONCE(adev->dev, 1, 1817 "Interrupt received for unknown VCN instance %d", 1818 entry->node_id); 1819 return 0; 1820 } 1821 1822 switch (entry->src_id) { 1823 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1824 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); 1825 break; 1826 default: 1827 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", 1828 entry->src_id, entry->src_data[0]); 1829 break; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static int vcn_v4_0_3_set_ras_interrupt_state(struct amdgpu_device *adev, 1836 struct amdgpu_irq_src *source, 1837 unsigned int type, 1838 enum amdgpu_interrupt_state state) 1839 { 1840 return 0; 1841 } 1842 1843 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = { 1844 .set = vcn_v4_0_3_set_interrupt_state, 1845 .process = vcn_v4_0_3_process_interrupt, 1846 }; 1847 1848 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_ras_irq_funcs = { 1849 .set = vcn_v4_0_3_set_ras_interrupt_state, 1850 .process = amdgpu_vcn_process_poison_irq, 1851 }; 1852 1853 /** 1854 * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions 1855 * 1856 * @adev: amdgpu_device pointer 1857 * 1858 * Set VCN block interrupt irq functions 1859 */ 1860 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) 1861 { 1862 int i; 1863 1864 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1865 adev->vcn.inst->irq.num_types++; 1866 } 1867 adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; 1868 1869 adev->vcn.inst->ras_poison_irq.num_types = 1; 1870 adev->vcn.inst->ras_poison_irq.funcs = &vcn_v4_0_3_ras_irq_funcs; 1871 } 1872 1873 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { 1874 .name = "vcn_v4_0_3", 1875 .early_init = vcn_v4_0_3_early_init, 1876 .sw_init = vcn_v4_0_3_sw_init, 1877 .sw_fini = vcn_v4_0_3_sw_fini, 1878 .hw_init = vcn_v4_0_3_hw_init, 1879 .hw_fini = vcn_v4_0_3_hw_fini, 1880 .suspend = vcn_v4_0_3_suspend, 1881 .resume = vcn_v4_0_3_resume, 1882 .is_idle = vcn_v4_0_3_is_idle, 1883 .wait_for_idle = vcn_v4_0_3_wait_for_idle, 1884 .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, 1885 .set_powergating_state = vcn_set_powergating_state, 1886 .dump_ip_state = amdgpu_vcn_dump_ip_state, 1887 .print_ip_state = amdgpu_vcn_print_ip_state, 1888 }; 1889 1890 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { 1891 .type = AMD_IP_BLOCK_TYPE_VCN, 1892 .major = 4, 1893 .minor = 0, 1894 .rev = 3, 1895 .funcs = &vcn_v4_0_3_ip_funcs, 1896 }; 1897 1898 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = { 1899 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD), 1900 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"}, 1901 {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV), 1902 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"}, 1903 }; 1904 1905 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev, 1906 uint32_t vcn_inst, 1907 void *ras_err_status) 1908 { 1909 struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status; 1910 1911 /* vcn v4_0_3 only support query uncorrectable errors */ 1912 amdgpu_ras_inst_query_ras_error_count(adev, 1913 vcn_v4_0_3_ue_reg_list, 1914 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1915 NULL, 0, GET_INST(VCN, vcn_inst), 1916 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 1917 &err_data->ue_count); 1918 } 1919 1920 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev, 1921 void *ras_err_status) 1922 { 1923 uint32_t i; 1924 1925 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1926 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1927 return; 1928 } 1929 1930 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1931 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status); 1932 } 1933 1934 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev, 1935 uint32_t vcn_inst) 1936 { 1937 amdgpu_ras_inst_reset_ras_error_count(adev, 1938 vcn_v4_0_3_ue_reg_list, 1939 ARRAY_SIZE(vcn_v4_0_3_ue_reg_list), 1940 GET_INST(VCN, vcn_inst)); 1941 } 1942 1943 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev) 1944 { 1945 uint32_t i; 1946 1947 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) { 1948 dev_warn(adev->dev, "VCN RAS is not supported\n"); 1949 return; 1950 } 1951 1952 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 1953 vcn_v4_0_3_inst_reset_ras_error_count(adev, i); 1954 } 1955 1956 static uint32_t vcn_v4_0_3_query_poison_by_instance(struct amdgpu_device *adev, 1957 uint32_t instance, uint32_t sub_block) 1958 { 1959 uint32_t poison_stat = 0, reg_value = 0; 1960 1961 switch (sub_block) { 1962 case AMDGPU_VCN_V4_0_3_VCPU_VCODEC: 1963 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 1964 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 1965 break; 1966 default: 1967 break; 1968 } 1969 1970 if (poison_stat) 1971 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 1972 instance, sub_block); 1973 1974 return poison_stat; 1975 } 1976 1977 static bool vcn_v4_0_3_query_poison_status(struct amdgpu_device *adev) 1978 { 1979 uint32_t inst, sub; 1980 uint32_t poison_stat = 0; 1981 1982 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 1983 for (sub = 0; sub < AMDGPU_VCN_V4_0_3_MAX_SUB_BLOCK; sub++) 1984 poison_stat += 1985 vcn_v4_0_3_query_poison_by_instance(adev, inst, sub); 1986 1987 return !!poison_stat; 1988 } 1989 1990 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = { 1991 .query_ras_error_count = vcn_v4_0_3_query_ras_error_count, 1992 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count, 1993 .query_poison_status = vcn_v4_0_3_query_poison_status, 1994 }; 1995 1996 static int vcn_v4_0_3_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 1997 enum aca_smu_type type, void *data) 1998 { 1999 struct aca_bank_info info; 2000 u64 misc0; 2001 int ret; 2002 2003 ret = aca_bank_info_decode(bank, &info); 2004 if (ret) 2005 return ret; 2006 2007 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 2008 switch (type) { 2009 case ACA_SMU_TYPE_UE: 2010 bank->aca_err_type = ACA_ERROR_TYPE_UE; 2011 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, 2012 1ULL); 2013 break; 2014 case ACA_SMU_TYPE_CE: 2015 bank->aca_err_type = ACA_ERROR_TYPE_CE; 2016 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 2017 ACA_REG__MISC0__ERRCNT(misc0)); 2018 break; 2019 default: 2020 return -EINVAL; 2021 } 2022 2023 return ret; 2024 } 2025 2026 /* reference to smu driver if header file */ 2027 static int vcn_v4_0_3_err_codes[] = { 2028 14, 15, /* VCN */ 2029 }; 2030 2031 static bool vcn_v4_0_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 2032 enum aca_smu_type type, void *data) 2033 { 2034 u32 instlo; 2035 2036 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 2037 instlo &= GENMASK(31, 1); 2038 2039 if (instlo != mmSMNAID_AID0_MCA_SMU) 2040 return false; 2041 2042 if (aca_bank_check_error_codes(handle->adev, bank, 2043 vcn_v4_0_3_err_codes, 2044 ARRAY_SIZE(vcn_v4_0_3_err_codes))) 2045 return false; 2046 2047 return true; 2048 } 2049 2050 static const struct aca_bank_ops vcn_v4_0_3_aca_bank_ops = { 2051 .aca_bank_parser = vcn_v4_0_3_aca_bank_parser, 2052 .aca_bank_is_valid = vcn_v4_0_3_aca_bank_is_valid, 2053 }; 2054 2055 static const struct aca_info vcn_v4_0_3_aca_info = { 2056 .hwip = ACA_HWIP_TYPE_SMU, 2057 .mask = ACA_ERROR_UE_MASK, 2058 .bank_ops = &vcn_v4_0_3_aca_bank_ops, 2059 }; 2060 2061 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 2062 { 2063 int r; 2064 2065 r = amdgpu_ras_block_late_init(adev, ras_block); 2066 if (r) 2067 return r; 2068 2069 if (amdgpu_ras_is_supported(adev, ras_block->block) && 2070 adev->vcn.inst->ras_poison_irq.funcs) { 2071 r = amdgpu_irq_get(adev, &adev->vcn.inst->ras_poison_irq, 0); 2072 if (r) 2073 goto late_fini; 2074 } 2075 2076 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__VCN, 2077 &vcn_v4_0_3_aca_info, NULL); 2078 if (r) 2079 goto late_fini; 2080 2081 return 0; 2082 2083 late_fini: 2084 amdgpu_ras_block_late_fini(adev, ras_block); 2085 2086 return r; 2087 } 2088 2089 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = { 2090 .ras_block = { 2091 .hw_ops = &vcn_v4_0_3_ras_hw_ops, 2092 .ras_late_init = vcn_v4_0_3_ras_late_init, 2093 }, 2094 }; 2095 2096 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) 2097 { 2098 adev->vcn.ras = &vcn_v4_0_3_ras; 2099 } 2100 2101 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, 2102 int inst_idx, bool indirect) 2103 { 2104 uint32_t tmp; 2105 2106 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 2107 return; 2108 2109 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 2110 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 2111 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 2112 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 2113 WREG32_SOC15_DPG_MODE(inst_idx, 2114 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 2115 tmp, 0, indirect); 2116 2117 tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK; 2118 WREG32_SOC15_DPG_MODE(inst_idx, 2119 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2), 2120 tmp, 0, indirect); 2121 2122 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 2123 WREG32_SOC15_DPG_MODE(inst_idx, 2124 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 2125 tmp, 0, indirect); 2126 } 2127