1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = { 56 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), 57 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), 58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), 59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), 60 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), 61 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), 62 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), 63 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), 64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), 65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), 66 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), 67 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), 68 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), 69 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), 70 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), 71 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), 72 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), 73 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), 74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), 75 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), 76 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), 77 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), 78 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), 79 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), 80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), 81 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), 82 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), 83 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), 84 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), 85 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), 86 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), 87 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), 88 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) 89 }; 90 91 static int amdgpu_ih_clientid_vcns[] = { 92 SOC15_IH_CLIENTID_VCN, 93 SOC15_IH_CLIENTID_VCN1 94 }; 95 96 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 97 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 100 enum amd_powergating_state state); 101 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 102 int inst_idx, struct dpg_pause_state *new_state); 103 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 104 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 105 106 /** 107 * vcn_v4_0_early_init - set function pointers and load microcode 108 * 109 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 110 * 111 * Set ring and irq function pointers 112 * Load microcode from filesystem 113 */ 114 static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block) 115 { 116 struct amdgpu_device *adev = ip_block->adev; 117 int i; 118 119 if (amdgpu_sriov_vf(adev)) { 120 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 122 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 123 adev->vcn.harvest_config |= 1 << i; 124 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 125 } 126 } 127 } 128 129 /* re-use enc ring as unified ring */ 130 adev->vcn.num_enc_rings = 1; 131 132 vcn_v4_0_set_unified_ring_funcs(adev); 133 vcn_v4_0_set_irq_funcs(adev); 134 vcn_v4_0_set_ras_funcs(adev); 135 136 return amdgpu_vcn_early_init(adev); 137 } 138 139 static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) 140 { 141 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 142 143 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 144 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 145 fw_shared->sq.is_enabled = 1; 146 147 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 148 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 149 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 150 151 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == 152 IP_VERSION(4, 0, 2)) { 153 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 154 fw_shared->drm_key_wa.method = 155 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 156 } 157 158 if (amdgpu_vcnfw_log) 159 amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); 160 161 return 0; 162 } 163 164 /** 165 * vcn_v4_0_sw_init - sw init for VCN block 166 * 167 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 168 * 169 * Load firmware and sw initialization 170 */ 171 static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) 172 { 173 struct amdgpu_ring *ring; 174 struct amdgpu_device *adev = ip_block->adev; 175 int i, r; 176 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 177 uint32_t *ptr; 178 179 r = amdgpu_vcn_sw_init(adev); 180 if (r) 181 return r; 182 183 amdgpu_vcn_setup_ucode(adev); 184 185 r = amdgpu_vcn_resume(adev); 186 if (r) 187 return r; 188 189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 190 if (adev->vcn.harvest_config & (1 << i)) 191 continue; 192 193 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */ 194 if (i == 0) 195 atomic_set(&adev->vcn.inst[i].sched_score, 1); 196 else 197 atomic_set(&adev->vcn.inst[i].sched_score, 0); 198 199 /* VCN UNIFIED TRAP */ 200 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 201 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 202 if (r) 203 return r; 204 205 /* VCN POISON TRAP */ 206 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 207 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq); 208 if (r) 209 return r; 210 211 ring = &adev->vcn.inst[i].ring_enc[0]; 212 ring->use_doorbell = true; 213 if (amdgpu_sriov_vf(adev)) 214 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 215 else 216 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 217 ring->vm_hub = AMDGPU_MMHUB0(0); 218 sprintf(ring->name, "vcn_unified_%d", i); 219 220 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 221 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 222 if (r) 223 return r; 224 225 vcn_v4_0_fw_shared_init(adev, i); 226 } 227 228 /* TODO: Add queue reset mask when FW fully supports it */ 229 adev->vcn.supported_reset = 230 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 231 232 if (amdgpu_sriov_vf(adev)) { 233 r = amdgpu_virt_alloc_mm_table(adev); 234 if (r) 235 return r; 236 } 237 238 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 239 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 240 241 r = amdgpu_vcn_ras_sw_init(adev); 242 if (r) 243 return r; 244 245 /* Allocate memory for VCN IP Dump buffer */ 246 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 247 if (!ptr) { 248 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 249 adev->vcn.ip_dump = NULL; 250 } else { 251 adev->vcn.ip_dump = ptr; 252 } 253 254 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 255 if (r) 256 return r; 257 258 return 0; 259 } 260 261 /** 262 * vcn_v4_0_sw_fini - sw fini for VCN block 263 * 264 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 265 * 266 * VCN suspend and free up sw allocation 267 */ 268 static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) 269 { 270 struct amdgpu_device *adev = ip_block->adev; 271 int i, r, idx; 272 273 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 274 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 275 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 276 277 if (adev->vcn.harvest_config & (1 << i)) 278 continue; 279 280 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 281 fw_shared->present_flag_0 = 0; 282 fw_shared->sq.is_enabled = 0; 283 } 284 285 drm_dev_exit(idx); 286 } 287 288 if (amdgpu_sriov_vf(adev)) 289 amdgpu_virt_free_mm_table(adev); 290 291 r = amdgpu_vcn_suspend(adev); 292 if (r) 293 return r; 294 295 amdgpu_vcn_sysfs_reset_mask_fini(adev); 296 r = amdgpu_vcn_sw_fini(adev); 297 298 kfree(adev->vcn.ip_dump); 299 300 return r; 301 } 302 303 /** 304 * vcn_v4_0_hw_init - start and test VCN block 305 * 306 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 307 * 308 * Initialize the hardware, boot up the VCPU and do some testing 309 */ 310 static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block) 311 { 312 struct amdgpu_device *adev = ip_block->adev; 313 struct amdgpu_ring *ring; 314 int i, r; 315 316 if (amdgpu_sriov_vf(adev)) { 317 r = vcn_v4_0_start_sriov(adev); 318 if (r) 319 return r; 320 321 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 322 if (adev->vcn.harvest_config & (1 << i)) 323 continue; 324 325 ring = &adev->vcn.inst[i].ring_enc[0]; 326 ring->wptr = 0; 327 ring->wptr_old = 0; 328 vcn_v4_0_unified_ring_set_wptr(ring); 329 ring->sched.ready = true; 330 } 331 } else { 332 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 333 if (adev->vcn.harvest_config & (1 << i)) 334 continue; 335 336 ring = &adev->vcn.inst[i].ring_enc[0]; 337 338 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 339 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 340 341 r = amdgpu_ring_test_helper(ring); 342 if (r) 343 return r; 344 } 345 } 346 347 return 0; 348 } 349 350 /** 351 * vcn_v4_0_hw_fini - stop the hardware block 352 * 353 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 354 * 355 * Stop the VCN block, mark ring as not ready any more 356 */ 357 static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) 358 { 359 struct amdgpu_device *adev = ip_block->adev; 360 int i; 361 362 cancel_delayed_work_sync(&adev->vcn.idle_work); 363 364 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 365 if (adev->vcn.harvest_config & (1 << i)) 366 continue; 367 if (!amdgpu_sriov_vf(adev)) { 368 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 369 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 370 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 371 vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 372 } 373 } 374 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 375 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 376 } 377 378 return 0; 379 } 380 381 /** 382 * vcn_v4_0_suspend - suspend VCN block 383 * 384 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 385 * 386 * HW fini and suspend VCN block 387 */ 388 static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) 389 { 390 int r; 391 392 r = vcn_v4_0_hw_fini(ip_block); 393 if (r) 394 return r; 395 396 r = amdgpu_vcn_suspend(ip_block->adev); 397 398 return r; 399 } 400 401 /** 402 * vcn_v4_0_resume - resume VCN block 403 * 404 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 405 * 406 * Resume firmware and hw init VCN block 407 */ 408 static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block) 409 { 410 int r; 411 412 r = amdgpu_vcn_resume(ip_block->adev); 413 if (r) 414 return r; 415 416 r = vcn_v4_0_hw_init(ip_block); 417 418 return r; 419 } 420 421 /** 422 * vcn_v4_0_mc_resume - memory controller programming 423 * 424 * @adev: amdgpu_device pointer 425 * @inst: instance number 426 * 427 * Let the VCN memory controller know it's offsets 428 */ 429 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 430 { 431 uint32_t offset, size; 432 const struct common_firmware_header *hdr; 433 434 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; 435 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 436 437 /* cache window 0: fw */ 438 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 439 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 441 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 442 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 443 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 444 offset = 0; 445 } else { 446 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 447 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 448 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 449 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 450 offset = size; 451 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 452 } 453 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 454 455 /* cache window 1: stack */ 456 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 457 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 458 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 459 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 460 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 461 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 462 463 /* cache window 2: context */ 464 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 465 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 466 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 467 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 468 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 469 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 470 471 /* non-cache window */ 472 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 473 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 474 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 475 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 476 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 477 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 478 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 479 } 480 481 /** 482 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 483 * 484 * @adev: amdgpu_device pointer 485 * @inst_idx: instance number index 486 * @indirect: indirectly write sram 487 * 488 * Let the VCN memory controller know it's offsets with dpg mode 489 */ 490 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 491 { 492 uint32_t offset, size; 493 const struct common_firmware_header *hdr; 494 hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; 495 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 496 497 /* cache window 0: fw */ 498 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 499 if (!indirect) { 500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 501 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 502 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 505 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 508 } else { 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 515 } 516 offset = 0; 517 } else { 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 520 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 523 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 524 offset = size; 525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 526 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 527 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 528 } 529 530 if (!indirect) 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 533 else 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 536 537 /* cache window 1: stack */ 538 if (!indirect) { 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 541 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 544 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 545 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 546 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 547 } else { 548 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 549 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 550 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 551 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 554 } 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 557 558 /* cache window 2: context */ 559 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 560 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 561 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 563 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 564 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 567 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 568 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 569 570 /* non-cache window */ 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 573 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 574 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 575 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 576 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 579 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 580 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 581 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 582 583 /* VCN global tiling registers */ 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 586 } 587 588 /** 589 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 590 * 591 * @adev: amdgpu_device pointer 592 * @inst: instance number 593 * 594 * Disable static power gating for VCN block 595 */ 596 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 597 { 598 uint32_t data = 0; 599 600 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 601 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 602 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 603 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 605 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 615 616 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 617 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 618 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 619 } else { 620 uint32_t value; 621 622 value = (inst) ? 0x2200800 : 0; 623 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 632 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 633 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 634 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 635 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 636 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 637 638 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 639 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 640 } 641 642 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 643 data &= ~0x103; 644 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 645 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 646 UVD_POWER_STATUS__UVD_PG_EN_MASK; 647 648 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 649 650 return; 651 } 652 653 /** 654 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 655 * 656 * @adev: amdgpu_device pointer 657 * @inst: instance number 658 * 659 * Enable static power gating for VCN block 660 */ 661 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 662 { 663 uint32_t data; 664 665 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 666 /* Before power off, this indicator has to be turned on */ 667 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 668 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 669 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 670 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 671 672 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 673 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 674 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 675 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 676 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 677 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 678 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 679 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 680 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 681 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 682 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 686 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 687 688 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 689 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 690 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 691 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 692 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 693 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 694 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 695 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 696 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 697 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 698 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 699 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 700 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 701 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 702 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 703 } 704 705 return; 706 } 707 708 /** 709 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 710 * 711 * @adev: amdgpu_device pointer 712 * @inst: instance number 713 * 714 * Disable clock gating for VCN block 715 */ 716 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 717 { 718 uint32_t data; 719 720 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 721 return; 722 723 /* VCN disable CGC */ 724 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 725 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 726 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 727 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 728 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 729 730 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 731 data &= ~(UVD_CGC_GATE__SYS_MASK 732 | UVD_CGC_GATE__UDEC_MASK 733 | UVD_CGC_GATE__MPEG2_MASK 734 | UVD_CGC_GATE__REGS_MASK 735 | UVD_CGC_GATE__RBC_MASK 736 | UVD_CGC_GATE__LMI_MC_MASK 737 | UVD_CGC_GATE__LMI_UMC_MASK 738 | UVD_CGC_GATE__IDCT_MASK 739 | UVD_CGC_GATE__MPRD_MASK 740 | UVD_CGC_GATE__MPC_MASK 741 | UVD_CGC_GATE__LBSI_MASK 742 | UVD_CGC_GATE__LRBBM_MASK 743 | UVD_CGC_GATE__UDEC_RE_MASK 744 | UVD_CGC_GATE__UDEC_CM_MASK 745 | UVD_CGC_GATE__UDEC_IT_MASK 746 | UVD_CGC_GATE__UDEC_DB_MASK 747 | UVD_CGC_GATE__UDEC_MP_MASK 748 | UVD_CGC_GATE__WCB_MASK 749 | UVD_CGC_GATE__VCPU_MASK 750 | UVD_CGC_GATE__MMSCH_MASK); 751 752 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 753 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 754 755 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 756 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 757 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 758 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 759 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 760 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 761 | UVD_CGC_CTRL__SYS_MODE_MASK 762 | UVD_CGC_CTRL__UDEC_MODE_MASK 763 | UVD_CGC_CTRL__MPEG2_MODE_MASK 764 | UVD_CGC_CTRL__REGS_MODE_MASK 765 | UVD_CGC_CTRL__RBC_MODE_MASK 766 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 767 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 768 | UVD_CGC_CTRL__IDCT_MODE_MASK 769 | UVD_CGC_CTRL__MPRD_MODE_MASK 770 | UVD_CGC_CTRL__MPC_MODE_MASK 771 | UVD_CGC_CTRL__LBSI_MODE_MASK 772 | UVD_CGC_CTRL__LRBBM_MODE_MASK 773 | UVD_CGC_CTRL__WCB_MODE_MASK 774 | UVD_CGC_CTRL__VCPU_MODE_MASK 775 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 776 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 777 778 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 779 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 780 | UVD_SUVD_CGC_GATE__SIT_MASK 781 | UVD_SUVD_CGC_GATE__SMP_MASK 782 | UVD_SUVD_CGC_GATE__SCM_MASK 783 | UVD_SUVD_CGC_GATE__SDB_MASK 784 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 785 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 786 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 787 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 788 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 789 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 790 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 791 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 792 | UVD_SUVD_CGC_GATE__SCLR_MASK 793 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 794 | UVD_SUVD_CGC_GATE__ENT_MASK 795 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 796 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 797 | UVD_SUVD_CGC_GATE__SITE_MASK 798 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 799 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 800 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 801 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 802 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 803 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 804 805 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 806 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 816 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 817 } 818 819 /** 820 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 821 * 822 * @adev: amdgpu_device pointer 823 * @sram_sel: sram select 824 * @inst_idx: instance number index 825 * @indirect: indirectly write sram 826 * 827 * Disable clock gating for VCN block with dpg mode 828 */ 829 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 830 int inst_idx, uint8_t indirect) 831 { 832 uint32_t reg_data = 0; 833 834 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 835 return; 836 837 /* enable sw clock gating control */ 838 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 839 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 840 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 841 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 843 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 844 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 845 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 846 UVD_CGC_CTRL__SYS_MODE_MASK | 847 UVD_CGC_CTRL__UDEC_MODE_MASK | 848 UVD_CGC_CTRL__MPEG2_MODE_MASK | 849 UVD_CGC_CTRL__REGS_MODE_MASK | 850 UVD_CGC_CTRL__RBC_MODE_MASK | 851 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 852 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 853 UVD_CGC_CTRL__IDCT_MODE_MASK | 854 UVD_CGC_CTRL__MPRD_MODE_MASK | 855 UVD_CGC_CTRL__MPC_MODE_MASK | 856 UVD_CGC_CTRL__LBSI_MODE_MASK | 857 UVD_CGC_CTRL__LRBBM_MODE_MASK | 858 UVD_CGC_CTRL__WCB_MODE_MASK | 859 UVD_CGC_CTRL__VCPU_MODE_MASK); 860 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 861 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 862 863 /* turn off clock gating */ 864 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 865 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 866 867 /* turn on SUVD clock gating */ 868 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 869 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 870 871 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 872 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 873 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 874 } 875 876 /** 877 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 878 * 879 * @adev: amdgpu_device pointer 880 * @inst: instance number 881 * 882 * Enable clock gating for VCN block 883 */ 884 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 885 { 886 uint32_t data; 887 888 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 889 return; 890 891 /* enable VCN CGC */ 892 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 893 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 894 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 895 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 896 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 897 898 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 899 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 900 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 902 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 903 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 904 | UVD_CGC_CTRL__SYS_MODE_MASK 905 | UVD_CGC_CTRL__UDEC_MODE_MASK 906 | UVD_CGC_CTRL__MPEG2_MODE_MASK 907 | UVD_CGC_CTRL__REGS_MODE_MASK 908 | UVD_CGC_CTRL__RBC_MODE_MASK 909 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 910 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 911 | UVD_CGC_CTRL__IDCT_MODE_MASK 912 | UVD_CGC_CTRL__MPRD_MODE_MASK 913 | UVD_CGC_CTRL__MPC_MODE_MASK 914 | UVD_CGC_CTRL__LBSI_MODE_MASK 915 | UVD_CGC_CTRL__LRBBM_MODE_MASK 916 | UVD_CGC_CTRL__WCB_MODE_MASK 917 | UVD_CGC_CTRL__VCPU_MODE_MASK 918 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 919 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 920 921 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 922 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 932 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 933 } 934 935 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 936 bool indirect) 937 { 938 uint32_t tmp; 939 940 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 941 return; 942 943 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 944 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 945 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 946 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 947 WREG32_SOC15_DPG_MODE(inst_idx, 948 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 949 tmp, 0, indirect); 950 951 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 952 WREG32_SOC15_DPG_MODE(inst_idx, 953 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 954 tmp, 0, indirect); 955 } 956 957 /** 958 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 959 * 960 * @adev: amdgpu_device pointer 961 * @inst_idx: instance number index 962 * @indirect: indirectly write sram 963 * 964 * Start VCN block with dpg mode 965 */ 966 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 967 { 968 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 969 struct amdgpu_ring *ring; 970 uint32_t tmp; 971 972 /* disable register anti-hang mechanism */ 973 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 974 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 975 /* enable dynamic power gating mode */ 976 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 977 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 978 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 979 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 980 981 if (indirect) 982 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 983 984 /* enable clock gating */ 985 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 986 987 /* enable VCPU clock */ 988 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 989 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 990 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 991 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 992 993 /* disable master interupt */ 994 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 995 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 996 997 /* setup regUVD_LMI_CTRL */ 998 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 999 UVD_LMI_CTRL__REQ_MODE_MASK | 1000 UVD_LMI_CTRL__CRC_RESET_MASK | 1001 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1002 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1003 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1004 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1005 0x00100000L); 1006 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1007 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 1008 1009 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1010 VCN, inst_idx, regUVD_MPC_CNTL), 1011 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1012 1013 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1014 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 1015 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1016 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1017 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1018 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1019 1020 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1021 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 1022 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1023 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1024 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1025 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1026 1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1028 VCN, inst_idx, regUVD_MPC_SET_MUX), 1029 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1030 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1031 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1032 1033 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1034 1035 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1036 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1037 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1038 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 1039 1040 /* enable LMI MC and UMC channels */ 1041 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 1042 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1043 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 1044 1045 vcn_v4_0_enable_ras(adev, inst_idx, indirect); 1046 1047 /* enable master interrupt */ 1048 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1049 VCN, inst_idx, regUVD_MASTINT_EN), 1050 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1051 1052 1053 if (indirect) 1054 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1055 1056 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1057 1058 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1059 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1060 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1061 1062 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1063 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1064 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1065 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1066 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1067 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1068 1069 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1070 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1071 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1072 1073 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1074 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1075 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1076 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1077 1078 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1079 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1080 VCN_RB1_DB_CTRL__EN_MASK); 1081 1082 return 0; 1083 } 1084 1085 1086 /** 1087 * vcn_v4_0_start - VCN start 1088 * 1089 * @adev: amdgpu_device pointer 1090 * 1091 * Start VCN block 1092 */ 1093 static int vcn_v4_0_start(struct amdgpu_device *adev) 1094 { 1095 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1096 struct amdgpu_ring *ring; 1097 uint32_t tmp; 1098 int i, j, k, r; 1099 1100 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1101 if (adev->pm.dpm_enabled) 1102 amdgpu_dpm_enable_vcn(adev, true, i); 1103 } 1104 1105 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1106 if (adev->vcn.harvest_config & (1 << i)) 1107 continue; 1108 1109 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1110 1111 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1112 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1113 continue; 1114 } 1115 1116 /* disable VCN power gating */ 1117 vcn_v4_0_disable_static_power_gating(adev, i); 1118 1119 /* set VCN status busy */ 1120 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1121 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1122 1123 /*SW clock gating */ 1124 vcn_v4_0_disable_clock_gating(adev, i); 1125 1126 /* enable VCPU clock */ 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1128 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1129 1130 /* disable master interrupt */ 1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1132 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1133 1134 /* enable LMI MC and UMC channels */ 1135 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1136 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1137 1138 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1139 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1140 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1141 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1142 1143 /* setup regUVD_LMI_CTRL */ 1144 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1145 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1146 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1147 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1148 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1149 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1150 1151 /* setup regUVD_MPC_CNTL */ 1152 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1153 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1154 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1155 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1156 1157 /* setup UVD_MPC_SET_MUXA0 */ 1158 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1159 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1160 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1161 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1162 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1163 1164 /* setup UVD_MPC_SET_MUXB0 */ 1165 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1166 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1167 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1168 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1169 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1170 1171 /* setup UVD_MPC_SET_MUX */ 1172 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1173 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1174 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1175 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1176 1177 vcn_v4_0_mc_resume(adev, i); 1178 1179 /* VCN global tiling registers */ 1180 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1181 adev->gfx.config.gb_addr_config); 1182 1183 /* unblock VCPU register access */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1185 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1186 1187 /* release VCPU reset to boot */ 1188 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1189 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1190 1191 for (j = 0; j < 10; ++j) { 1192 uint32_t status; 1193 1194 for (k = 0; k < 100; ++k) { 1195 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1196 if (status & 2) 1197 break; 1198 mdelay(10); 1199 if (amdgpu_emu_mode == 1) 1200 msleep(1); 1201 } 1202 1203 if (amdgpu_emu_mode == 1) { 1204 r = -1; 1205 if (status & 2) { 1206 r = 0; 1207 break; 1208 } 1209 } else { 1210 r = 0; 1211 if (status & 2) 1212 break; 1213 1214 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1215 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1216 UVD_VCPU_CNTL__BLK_RST_MASK, 1217 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1218 mdelay(10); 1219 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1220 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1221 1222 mdelay(10); 1223 r = -1; 1224 } 1225 } 1226 1227 if (r) { 1228 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1229 return r; 1230 } 1231 1232 /* enable master interrupt */ 1233 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1234 UVD_MASTINT_EN__VCPU_EN_MASK, 1235 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1236 1237 /* clear the busy bit of VCN_STATUS */ 1238 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1239 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1240 1241 ring = &adev->vcn.inst[i].ring_enc[0]; 1242 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1243 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1244 VCN_RB1_DB_CTRL__EN_MASK); 1245 1246 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1247 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1248 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1249 1250 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1251 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1252 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1253 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1254 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1255 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1256 1257 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1258 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1259 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1260 1261 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1262 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1263 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1264 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc) 1271 { 1272 struct amdgpu_vcn_rb_metadata *rb_metadata = NULL; 1273 uint8_t *rb_ptr = (uint8_t *)ring_enc->ring; 1274 1275 rb_ptr += ring_enc->ring_size; 1276 rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr; 1277 1278 memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata)); 1279 rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata); 1280 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1281 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1282 rb_metadata->version = 1; 1283 rb_metadata->ring_id = vcn_inst & 0xFF; 1284 1285 return 0; 1286 } 1287 1288 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1289 { 1290 int i; 1291 struct amdgpu_ring *ring_enc; 1292 uint64_t cache_addr; 1293 uint64_t rb_enc_addr; 1294 uint64_t ctx_addr; 1295 uint32_t param, resp, expected; 1296 uint32_t offset, cache_size; 1297 uint32_t tmp, timeout; 1298 1299 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1300 uint32_t *table_loc; 1301 uint32_t table_size; 1302 uint32_t size, size_dw; 1303 uint32_t init_status; 1304 uint32_t enabled_vcn; 1305 1306 struct mmsch_v4_0_cmd_direct_write 1307 direct_wt = { {0} }; 1308 struct mmsch_v4_0_cmd_direct_read_modify_write 1309 direct_rd_mod_wt = { {0} }; 1310 struct mmsch_v4_0_cmd_end end = { {0} }; 1311 struct mmsch_v4_0_init_header header; 1312 1313 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1314 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1315 1316 direct_wt.cmd_header.command_type = 1317 MMSCH_COMMAND__DIRECT_REG_WRITE; 1318 direct_rd_mod_wt.cmd_header.command_type = 1319 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1320 end.cmd_header.command_type = 1321 MMSCH_COMMAND__END; 1322 1323 header.version = MMSCH_VERSION; 1324 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1325 for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) { 1326 header.inst[i].init_status = 0; 1327 header.inst[i].table_offset = 0; 1328 header.inst[i].table_size = 0; 1329 } 1330 1331 table_loc = (uint32_t *)table->cpu_addr; 1332 table_loc += header.total_size; 1333 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1334 if (adev->vcn.harvest_config & (1 << i)) 1335 continue; 1336 1337 // Must re/init fw_shared at beginning 1338 vcn_v4_0_fw_shared_init(adev, i); 1339 1340 table_size = 0; 1341 1342 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1343 regUVD_STATUS), 1344 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1345 1346 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1347 1348 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1349 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1350 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1351 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1352 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1353 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1354 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1355 offset = 0; 1356 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1357 regUVD_VCPU_CACHE_OFFSET0), 1358 0); 1359 } else { 1360 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1361 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1362 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1363 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1364 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1365 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1366 offset = cache_size; 1367 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1368 regUVD_VCPU_CACHE_OFFSET0), 1369 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1370 } 1371 1372 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1373 regUVD_VCPU_CACHE_SIZE0), 1374 cache_size); 1375 1376 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1377 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1378 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1379 lower_32_bits(cache_addr)); 1380 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1381 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1382 upper_32_bits(cache_addr)); 1383 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1384 regUVD_VCPU_CACHE_OFFSET1), 1385 0); 1386 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1387 regUVD_VCPU_CACHE_SIZE1), 1388 AMDGPU_VCN_STACK_SIZE); 1389 1390 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1391 AMDGPU_VCN_STACK_SIZE; 1392 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1393 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1394 lower_32_bits(cache_addr)); 1395 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1396 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1397 upper_32_bits(cache_addr)); 1398 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1399 regUVD_VCPU_CACHE_OFFSET2), 1400 0); 1401 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1402 regUVD_VCPU_CACHE_SIZE2), 1403 AMDGPU_VCN_CONTEXT_SIZE); 1404 1405 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1406 rb_setup = &fw_shared->rb_setup; 1407 1408 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1409 ring_enc->wptr = 0; 1410 rb_enc_addr = ring_enc->gpu_addr; 1411 1412 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1413 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1414 1415 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 1416 vcn_v4_0_init_ring_metadata(adev, i, ring_enc); 1417 1418 memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP); 1419 if (!(adev->vcn.harvest_config & (1 << 0))) { 1420 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1421 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1422 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4; 1423 } 1424 if (!(adev->vcn.harvest_config & (1 << 1))) { 1425 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1426 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1427 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4; 1428 } 1429 fw_shared->decouple.is_enabled = 1; 1430 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1431 } else { 1432 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1433 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1434 rb_setup->rb_size = ring_enc->ring_size / 4; 1435 } 1436 1437 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1438 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1439 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1440 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1441 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1442 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1443 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1444 regUVD_VCPU_NONCACHE_SIZE0), 1445 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1446 1447 /* add end packet */ 1448 MMSCH_V4_0_INSERT_END(); 1449 1450 /* refine header */ 1451 header.inst[i].init_status = 0; 1452 header.inst[i].table_offset = header.total_size; 1453 header.inst[i].table_size = table_size; 1454 header.total_size += table_size; 1455 } 1456 1457 /* Update init table header in memory */ 1458 size = sizeof(struct mmsch_v4_0_init_header); 1459 table_loc = (uint32_t *)table->cpu_addr; 1460 memcpy((void *)table_loc, &header, size); 1461 1462 /* message MMSCH (in VCN[0]) to initialize this client 1463 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1464 * of memory descriptor location 1465 */ 1466 ctx_addr = table->gpu_addr; 1467 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1468 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1469 1470 /* 2, update vmid of descriptor */ 1471 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1472 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1473 /* use domain0 for MM scheduler */ 1474 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1475 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1476 1477 /* 3, notify mmsch about the size of this descriptor */ 1478 size = header.total_size; 1479 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1480 1481 /* 4, set resp to zero */ 1482 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1483 1484 /* 5, kick off the initialization and wait until 1485 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1486 */ 1487 param = 0x00000001; 1488 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1489 tmp = 0; 1490 timeout = 1000; 1491 resp = 0; 1492 expected = MMSCH_VF_MAILBOX_RESP__OK; 1493 while (resp != expected) { 1494 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1495 if (resp != 0) 1496 break; 1497 1498 udelay(10); 1499 tmp = tmp + 10; 1500 if (tmp >= timeout) { 1501 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1502 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1503 "(expected=0x%08x, readback=0x%08x)\n", 1504 tmp, expected, resp); 1505 return -EBUSY; 1506 } 1507 } 1508 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1509 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1510 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1511 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1512 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1513 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1514 1515 return 0; 1516 } 1517 1518 /** 1519 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1520 * 1521 * @adev: amdgpu_device pointer 1522 * @inst_idx: instance number index 1523 * 1524 * Stop VCN block with dpg mode 1525 */ 1526 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1527 { 1528 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1529 uint32_t tmp; 1530 1531 vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state); 1532 /* Wait for power status to be 1 */ 1533 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1534 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1535 1536 /* wait for read ptr to be equal to write ptr */ 1537 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1538 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1539 1540 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1541 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1542 1543 /* disable dynamic power gating mode */ 1544 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1545 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1546 } 1547 1548 /** 1549 * vcn_v4_0_stop - VCN stop 1550 * 1551 * @adev: amdgpu_device pointer 1552 * 1553 * Stop VCN block 1554 */ 1555 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1556 { 1557 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1558 uint32_t tmp; 1559 int i, r = 0; 1560 1561 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1562 if (adev->vcn.harvest_config & (1 << i)) 1563 continue; 1564 1565 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1566 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1567 1568 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1569 vcn_v4_0_stop_dpg_mode(adev, i); 1570 continue; 1571 } 1572 1573 /* wait for vcn idle */ 1574 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1575 if (r) 1576 return r; 1577 1578 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1579 UVD_LMI_STATUS__READ_CLEAN_MASK | 1580 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1581 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1582 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1583 if (r) 1584 return r; 1585 1586 /* disable LMI UMC channel */ 1587 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1588 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1589 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1590 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1591 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1592 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1593 if (r) 1594 return r; 1595 1596 /* block VCPU register access */ 1597 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1598 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1599 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1600 1601 /* reset VCPU */ 1602 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1603 UVD_VCPU_CNTL__BLK_RST_MASK, 1604 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1605 1606 /* disable VCPU clock */ 1607 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1608 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1609 1610 /* apply soft reset */ 1611 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1612 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1613 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1614 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1615 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1616 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1617 1618 /* clear status */ 1619 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1620 1621 /* apply HW clock gating */ 1622 vcn_v4_0_enable_clock_gating(adev, i); 1623 1624 /* enable VCN power gating */ 1625 vcn_v4_0_enable_static_power_gating(adev, i); 1626 } 1627 1628 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1629 if (adev->pm.dpm_enabled) 1630 amdgpu_dpm_enable_vcn(adev, false, i); 1631 } 1632 1633 return 0; 1634 } 1635 1636 /** 1637 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1638 * 1639 * @adev: amdgpu_device pointer 1640 * @inst_idx: instance number index 1641 * @new_state: pause state 1642 * 1643 * Pause dpg mode for VCN block 1644 */ 1645 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1646 struct dpg_pause_state *new_state) 1647 { 1648 uint32_t reg_data = 0; 1649 int ret_code; 1650 1651 /* pause/unpause if state is changed */ 1652 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1653 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1654 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1655 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1656 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1657 1658 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1659 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1660 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1661 1662 if (!ret_code) { 1663 /* pause DPG */ 1664 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1665 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1666 1667 /* wait for ACK */ 1668 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1669 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1670 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1671 1672 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1673 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1674 } 1675 } else { 1676 /* unpause dpg, no need to wait */ 1677 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1678 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1679 } 1680 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1681 } 1682 1683 return 0; 1684 } 1685 1686 /** 1687 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1688 * 1689 * @ring: amdgpu_ring pointer 1690 * 1691 * Returns the current hardware unified read pointer 1692 */ 1693 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1694 { 1695 struct amdgpu_device *adev = ring->adev; 1696 1697 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1698 DRM_ERROR("wrong ring id is identified in %s", __func__); 1699 1700 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1701 } 1702 1703 /** 1704 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1705 * 1706 * @ring: amdgpu_ring pointer 1707 * 1708 * Returns the current hardware unified write pointer 1709 */ 1710 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1711 { 1712 struct amdgpu_device *adev = ring->adev; 1713 1714 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1715 DRM_ERROR("wrong ring id is identified in %s", __func__); 1716 1717 if (ring->use_doorbell) 1718 return *ring->wptr_cpu_addr; 1719 else 1720 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1721 } 1722 1723 /** 1724 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1725 * 1726 * @ring: amdgpu_ring pointer 1727 * 1728 * Commits the enc write pointer to the hardware 1729 */ 1730 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1731 { 1732 struct amdgpu_device *adev = ring->adev; 1733 1734 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1735 DRM_ERROR("wrong ring id is identified in %s", __func__); 1736 1737 if (ring->use_doorbell) { 1738 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1739 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1740 } else { 1741 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1742 } 1743 } 1744 1745 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1746 struct amdgpu_job *job) 1747 { 1748 struct drm_gpu_scheduler **scheds; 1749 1750 /* The create msg must be in the first IB submitted */ 1751 if (atomic_read(&job->base.entity->fence_seq)) 1752 return -EINVAL; 1753 1754 /* if VCN0 is harvested, we can't support AV1 */ 1755 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1756 return -EINVAL; 1757 1758 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1759 [AMDGPU_RING_PRIO_0].sched; 1760 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1761 return 0; 1762 } 1763 1764 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1765 uint64_t addr) 1766 { 1767 struct ttm_operation_ctx ctx = { false, false }; 1768 struct amdgpu_bo_va_mapping *map; 1769 uint32_t *msg, num_buffers; 1770 struct amdgpu_bo *bo; 1771 uint64_t start, end; 1772 unsigned int i; 1773 void *ptr; 1774 int r; 1775 1776 addr &= AMDGPU_GMC_HOLE_MASK; 1777 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1778 if (r) { 1779 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1780 return r; 1781 } 1782 1783 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1784 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1785 if (addr & 0x7) { 1786 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1787 return -EINVAL; 1788 } 1789 1790 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1791 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1792 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1793 if (r) { 1794 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1795 return r; 1796 } 1797 1798 r = amdgpu_bo_kmap(bo, &ptr); 1799 if (r) { 1800 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1801 return r; 1802 } 1803 1804 msg = ptr + addr - start; 1805 1806 /* Check length */ 1807 if (msg[1] > end - addr) { 1808 r = -EINVAL; 1809 goto out; 1810 } 1811 1812 if (msg[3] != RDECODE_MSG_CREATE) 1813 goto out; 1814 1815 num_buffers = msg[2]; 1816 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1817 uint32_t offset, size, *create; 1818 1819 if (msg[0] != RDECODE_MESSAGE_CREATE) 1820 continue; 1821 1822 offset = msg[1]; 1823 size = msg[2]; 1824 1825 if (offset + size > end) { 1826 r = -EINVAL; 1827 goto out; 1828 } 1829 1830 create = ptr + addr + offset - start; 1831 1832 /* H264, HEVC and VP9 can run on any instance */ 1833 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1834 continue; 1835 1836 r = vcn_v4_0_limit_sched(p, job); 1837 if (r) 1838 goto out; 1839 } 1840 1841 out: 1842 amdgpu_bo_kunmap(bo); 1843 return r; 1844 } 1845 1846 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1847 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1848 1849 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1850 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1851 1852 #define RENCODE_ENCODE_STANDARD_AV1 2 1853 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1854 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1855 1856 /* return the offset in ib if id is found, -1 otherwise 1857 * to speed up the searching we only search upto max_offset 1858 */ 1859 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1860 { 1861 int i; 1862 1863 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1864 if (ib->ptr[i + 1] == id) 1865 return i; 1866 } 1867 return -1; 1868 } 1869 1870 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1871 struct amdgpu_job *job, 1872 struct amdgpu_ib *ib) 1873 { 1874 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1875 struct amdgpu_vcn_decode_buffer *decode_buffer; 1876 uint64_t addr; 1877 uint32_t val; 1878 int idx; 1879 1880 /* The first instance can decode anything */ 1881 if (!ring->me) 1882 return 0; 1883 1884 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1885 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1886 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1887 if (idx < 0) /* engine info is missing */ 1888 return 0; 1889 1890 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1891 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1892 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1893 1894 if (!(decode_buffer->valid_buf_flag & 0x1)) 1895 return 0; 1896 1897 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1898 decode_buffer->msg_buffer_address_lo; 1899 return vcn_v4_0_dec_msg(p, job, addr); 1900 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1901 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1902 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1903 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1904 return vcn_v4_0_limit_sched(p, job); 1905 } 1906 return 0; 1907 } 1908 1909 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1910 .type = AMDGPU_RING_TYPE_VCN_ENC, 1911 .align_mask = 0x3f, 1912 .nop = VCN_ENC_CMD_NO_OP, 1913 .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata), 1914 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1915 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1916 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1917 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1918 .emit_frame_size = 1919 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1920 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1921 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1922 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1923 1, /* vcn_v2_0_enc_ring_insert_end */ 1924 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1925 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1926 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1927 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1928 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1929 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1930 .insert_nop = amdgpu_ring_insert_nop, 1931 .insert_end = vcn_v2_0_enc_ring_insert_end, 1932 .pad_ib = amdgpu_ring_generic_pad_ib, 1933 .begin_use = amdgpu_vcn_ring_begin_use, 1934 .end_use = amdgpu_vcn_ring_end_use, 1935 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1936 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1937 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1938 }; 1939 1940 /** 1941 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1942 * 1943 * @adev: amdgpu_device pointer 1944 * 1945 * Set unified ring functions 1946 */ 1947 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1948 { 1949 int i; 1950 1951 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1952 if (adev->vcn.harvest_config & (1 << i)) 1953 continue; 1954 1955 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2)) 1956 vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true; 1957 1958 adev->vcn.inst[i].ring_enc[0].funcs = 1959 (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs; 1960 adev->vcn.inst[i].ring_enc[0].me = i; 1961 } 1962 } 1963 1964 /** 1965 * vcn_v4_0_is_idle - check VCN block is idle 1966 * 1967 * @handle: amdgpu_device pointer 1968 * 1969 * Check whether VCN block is idle 1970 */ 1971 static bool vcn_v4_0_is_idle(void *handle) 1972 { 1973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1974 int i, ret = 1; 1975 1976 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1977 if (adev->vcn.harvest_config & (1 << i)) 1978 continue; 1979 1980 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1981 } 1982 1983 return ret; 1984 } 1985 1986 /** 1987 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1988 * 1989 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 1990 * 1991 * Wait for VCN block idle 1992 */ 1993 static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1994 { 1995 struct amdgpu_device *adev = ip_block->adev; 1996 int i, ret = 0; 1997 1998 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1999 if (adev->vcn.harvest_config & (1 << i)) 2000 continue; 2001 2002 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 2003 UVD_STATUS__IDLE); 2004 if (ret) 2005 return ret; 2006 } 2007 2008 return ret; 2009 } 2010 2011 /** 2012 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 2013 * 2014 * @ip_block: amdgpu_ip_block pointer 2015 * @state: clock gating state 2016 * 2017 * Set VCN block clockgating state 2018 */ 2019 static int vcn_v4_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2020 enum amd_clockgating_state state) 2021 { 2022 struct amdgpu_device *adev = ip_block->adev; 2023 bool enable = state == AMD_CG_STATE_GATE; 2024 int i; 2025 2026 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2027 if (adev->vcn.harvest_config & (1 << i)) 2028 continue; 2029 2030 if (enable) { 2031 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 2032 return -EBUSY; 2033 vcn_v4_0_enable_clock_gating(adev, i); 2034 } else { 2035 vcn_v4_0_disable_clock_gating(adev, i); 2036 } 2037 } 2038 2039 return 0; 2040 } 2041 2042 /** 2043 * vcn_v4_0_set_powergating_state - set VCN block powergating state 2044 * 2045 * @ip_block: amdgpu_ip_block pointer 2046 * @state: power gating state 2047 * 2048 * Set VCN block powergating state 2049 */ 2050 static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 2051 enum amd_powergating_state state) 2052 { 2053 struct amdgpu_device *adev = ip_block->adev; 2054 int ret; 2055 2056 /* for SRIOV, guest should not control VCN Power-gating 2057 * MMSCH FW should control Power-gating and clock-gating 2058 * guest should avoid touching CGC and PG 2059 */ 2060 if (amdgpu_sriov_vf(adev)) { 2061 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2062 return 0; 2063 } 2064 2065 if (state == adev->vcn.cur_state) 2066 return 0; 2067 2068 if (state == AMD_PG_STATE_GATE) 2069 ret = vcn_v4_0_stop(adev); 2070 else 2071 ret = vcn_v4_0_start(adev); 2072 2073 if (!ret) 2074 adev->vcn.cur_state = state; 2075 2076 return ret; 2077 } 2078 2079 /** 2080 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state 2081 * 2082 * @adev: amdgpu_device pointer 2083 * @source: interrupt sources 2084 * @type: interrupt types 2085 * @state: interrupt states 2086 * 2087 * Set VCN block RAS interrupt state 2088 */ 2089 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 2090 struct amdgpu_irq_src *source, 2091 unsigned int type, 2092 enum amdgpu_interrupt_state state) 2093 { 2094 return 0; 2095 } 2096 2097 /** 2098 * vcn_v4_0_process_interrupt - process VCN block interrupt 2099 * 2100 * @adev: amdgpu_device pointer 2101 * @source: interrupt sources 2102 * @entry: interrupt entry from clients and sources 2103 * 2104 * Process VCN block interrupt 2105 */ 2106 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2107 struct amdgpu_iv_entry *entry) 2108 { 2109 uint32_t ip_instance; 2110 2111 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 2112 ip_instance = entry->ring_id; 2113 } else { 2114 switch (entry->client_id) { 2115 case SOC15_IH_CLIENTID_VCN: 2116 ip_instance = 0; 2117 break; 2118 case SOC15_IH_CLIENTID_VCN1: 2119 ip_instance = 1; 2120 break; 2121 default: 2122 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2123 return 0; 2124 } 2125 } 2126 2127 DRM_DEBUG("IH: VCN TRAP\n"); 2128 2129 switch (entry->src_id) { 2130 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2131 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2132 break; 2133 default: 2134 DRM_ERROR("Unhandled interrupt: %d %d\n", 2135 entry->src_id, entry->src_data[0]); 2136 break; 2137 } 2138 2139 return 0; 2140 } 2141 2142 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2143 .process = vcn_v4_0_process_interrupt, 2144 }; 2145 2146 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = { 2147 .set = vcn_v4_0_set_ras_interrupt_state, 2148 .process = amdgpu_vcn_process_poison_irq, 2149 }; 2150 2151 /** 2152 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 2153 * 2154 * @adev: amdgpu_device pointer 2155 * 2156 * Set VCN block interrupt irq functions 2157 */ 2158 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2159 { 2160 int i; 2161 2162 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2163 if (adev->vcn.harvest_config & (1 << i)) 2164 continue; 2165 2166 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2167 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2168 2169 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; 2170 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs; 2171 } 2172 } 2173 2174 static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2175 { 2176 struct amdgpu_device *adev = ip_block->adev; 2177 int i, j; 2178 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 2179 uint32_t inst_off, is_powered; 2180 2181 if (!adev->vcn.ip_dump) 2182 return; 2183 2184 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2185 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2186 if (adev->vcn.harvest_config & (1 << i)) { 2187 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2188 continue; 2189 } 2190 2191 inst_off = i * reg_count; 2192 is_powered = (adev->vcn.ip_dump[inst_off] & 2193 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2194 2195 if (is_powered) { 2196 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2197 for (j = 0; j < reg_count; j++) 2198 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name, 2199 adev->vcn.ip_dump[inst_off + j]); 2200 } else { 2201 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2202 } 2203 } 2204 } 2205 2206 static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2207 { 2208 struct amdgpu_device *adev = ip_block->adev; 2209 int i, j; 2210 bool is_powered; 2211 uint32_t inst_off; 2212 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); 2213 2214 if (!adev->vcn.ip_dump) 2215 return; 2216 2217 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2218 if (adev->vcn.harvest_config & (1 << i)) 2219 continue; 2220 2221 inst_off = i * reg_count; 2222 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2223 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); 2224 is_powered = (adev->vcn.ip_dump[inst_off] & 2225 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2226 2227 if (is_powered) 2228 for (j = 1; j < reg_count; j++) 2229 adev->vcn.ip_dump[inst_off + j] = 2230 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j], 2231 i)); 2232 } 2233 } 2234 2235 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2236 .name = "vcn_v4_0", 2237 .early_init = vcn_v4_0_early_init, 2238 .sw_init = vcn_v4_0_sw_init, 2239 .sw_fini = vcn_v4_0_sw_fini, 2240 .hw_init = vcn_v4_0_hw_init, 2241 .hw_fini = vcn_v4_0_hw_fini, 2242 .suspend = vcn_v4_0_suspend, 2243 .resume = vcn_v4_0_resume, 2244 .is_idle = vcn_v4_0_is_idle, 2245 .wait_for_idle = vcn_v4_0_wait_for_idle, 2246 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2247 .set_powergating_state = vcn_v4_0_set_powergating_state, 2248 .dump_ip_state = vcn_v4_0_dump_ip_state, 2249 .print_ip_state = vcn_v4_0_print_ip_state, 2250 }; 2251 2252 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { 2253 .type = AMD_IP_BLOCK_TYPE_VCN, 2254 .major = 4, 2255 .minor = 0, 2256 .rev = 0, 2257 .funcs = &vcn_v4_0_ip_funcs, 2258 }; 2259 2260 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2261 uint32_t instance, uint32_t sub_block) 2262 { 2263 uint32_t poison_stat = 0, reg_value = 0; 2264 2265 switch (sub_block) { 2266 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2267 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2268 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2269 break; 2270 default: 2271 break; 2272 } 2273 2274 if (poison_stat) 2275 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2276 instance, sub_block); 2277 2278 return poison_stat; 2279 } 2280 2281 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2282 { 2283 uint32_t inst, sub; 2284 uint32_t poison_stat = 0; 2285 2286 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2287 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2288 poison_stat += 2289 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2290 2291 return !!poison_stat; 2292 } 2293 2294 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2295 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2296 }; 2297 2298 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2299 .ras_block = { 2300 .hw_ops = &vcn_v4_0_ras_hw_ops, 2301 .ras_late_init = amdgpu_vcn_ras_late_init, 2302 }, 2303 }; 2304 2305 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2306 { 2307 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2308 case IP_VERSION(4, 0, 0): 2309 adev->vcn.ras = &vcn_v4_0_ras; 2310 break; 2311 default: 2312 break; 2313 } 2314 } 2315