1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static int amdgpu_ih_clientid_vcns[] = { 56 SOC15_IH_CLIENTID_VCN, 57 SOC15_IH_CLIENTID_VCN1 58 }; 59 60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int vcn_v4_0_set_powergating_state(void *handle, 64 enum amd_powergating_state state); 65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 66 int inst_idx, struct dpg_pause_state *new_state); 67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 69 70 /** 71 * vcn_v4_0_early_init - set function pointers and load microcode 72 * 73 * @handle: amdgpu_device pointer 74 * 75 * Set ring and irq function pointers 76 * Load microcode from filesystem 77 */ 78 static int vcn_v4_0_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 int i; 82 83 if (amdgpu_sriov_vf(adev)) { 84 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 85 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 86 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 87 adev->vcn.harvest_config |= 1 << i; 88 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 89 } 90 } 91 } 92 93 /* re-use enc ring as unified ring */ 94 adev->vcn.num_enc_rings = 1; 95 96 vcn_v4_0_set_unified_ring_funcs(adev); 97 vcn_v4_0_set_irq_funcs(adev); 98 vcn_v4_0_set_ras_funcs(adev); 99 100 return amdgpu_vcn_early_init(adev); 101 } 102 103 /** 104 * vcn_v4_0_sw_init - sw init for VCN block 105 * 106 * @handle: amdgpu_device pointer 107 * 108 * Load firmware and sw initialization 109 */ 110 static int vcn_v4_0_sw_init(void *handle) 111 { 112 struct amdgpu_ring *ring; 113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 114 int i, r; 115 116 r = amdgpu_vcn_sw_init(adev); 117 if (r) 118 return r; 119 120 amdgpu_vcn_setup_ucode(adev); 121 122 r = amdgpu_vcn_resume(adev); 123 if (r) 124 return r; 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 127 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 128 129 if (adev->vcn.harvest_config & (1 << i)) 130 continue; 131 132 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */ 133 if (i == 0) 134 atomic_set(&adev->vcn.inst[i].sched_score, 1); 135 else 136 atomic_set(&adev->vcn.inst[i].sched_score, 0); 137 138 /* VCN UNIFIED TRAP */ 139 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 140 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 141 if (r) 142 return r; 143 144 /* VCN POISON TRAP */ 145 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 146 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq); 147 if (r) 148 return r; 149 150 ring = &adev->vcn.inst[i].ring_enc[0]; 151 ring->use_doorbell = true; 152 if (amdgpu_sriov_vf(adev)) 153 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 154 else 155 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 156 ring->vm_hub = AMDGPU_MMHUB0(0); 157 sprintf(ring->name, "vcn_unified_%d", i); 158 159 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 160 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 161 if (r) 162 return r; 163 164 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 165 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 166 fw_shared->sq.is_enabled = 1; 167 168 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 169 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 170 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 171 172 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == 173 IP_VERSION(4, 0, 2)) { 174 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 175 fw_shared->drm_key_wa.method = 176 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 177 } 178 179 if (amdgpu_vcnfw_log) 180 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 181 } 182 183 if (amdgpu_sriov_vf(adev)) { 184 r = amdgpu_virt_alloc_mm_table(adev); 185 if (r) 186 return r; 187 } 188 189 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 190 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 191 192 r = amdgpu_vcn_ras_sw_init(adev); 193 if (r) 194 return r; 195 196 return 0; 197 } 198 199 /** 200 * vcn_v4_0_sw_fini - sw fini for VCN block 201 * 202 * @handle: amdgpu_device pointer 203 * 204 * VCN suspend and free up sw allocation 205 */ 206 static int vcn_v4_0_sw_fini(void *handle) 207 { 208 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 209 int i, r, idx; 210 211 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 212 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 213 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 214 215 if (adev->vcn.harvest_config & (1 << i)) 216 continue; 217 218 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 219 fw_shared->present_flag_0 = 0; 220 fw_shared->sq.is_enabled = 0; 221 } 222 223 drm_dev_exit(idx); 224 } 225 226 if (amdgpu_sriov_vf(adev)) 227 amdgpu_virt_free_mm_table(adev); 228 229 r = amdgpu_vcn_suspend(adev); 230 if (r) 231 return r; 232 233 r = amdgpu_vcn_sw_fini(adev); 234 235 return r; 236 } 237 238 /** 239 * vcn_v4_0_hw_init - start and test VCN block 240 * 241 * @handle: amdgpu_device pointer 242 * 243 * Initialize the hardware, boot up the VCPU and do some testing 244 */ 245 static int vcn_v4_0_hw_init(void *handle) 246 { 247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 248 struct amdgpu_ring *ring; 249 int i, r; 250 251 if (amdgpu_sriov_vf(adev)) { 252 r = vcn_v4_0_start_sriov(adev); 253 if (r) 254 goto done; 255 256 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 257 if (adev->vcn.harvest_config & (1 << i)) 258 continue; 259 260 ring = &adev->vcn.inst[i].ring_enc[0]; 261 ring->wptr = 0; 262 ring->wptr_old = 0; 263 vcn_v4_0_unified_ring_set_wptr(ring); 264 ring->sched.ready = true; 265 266 } 267 } else { 268 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 269 if (adev->vcn.harvest_config & (1 << i)) 270 continue; 271 272 ring = &adev->vcn.inst[i].ring_enc[0]; 273 274 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 275 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 276 277 r = amdgpu_ring_test_helper(ring); 278 if (r) 279 goto done; 280 281 } 282 } 283 284 done: 285 if (!r) 286 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 287 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 288 289 return r; 290 } 291 292 /** 293 * vcn_v4_0_hw_fini - stop the hardware block 294 * 295 * @handle: amdgpu_device pointer 296 * 297 * Stop the VCN block, mark ring as not ready any more 298 */ 299 static int vcn_v4_0_hw_fini(void *handle) 300 { 301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 302 int i; 303 304 cancel_delayed_work_sync(&adev->vcn.idle_work); 305 306 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 307 if (adev->vcn.harvest_config & (1 << i)) 308 continue; 309 if (!amdgpu_sriov_vf(adev)) { 310 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 311 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 312 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 313 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 314 } 315 } 316 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 317 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 318 } 319 320 return 0; 321 } 322 323 /** 324 * vcn_v4_0_suspend - suspend VCN block 325 * 326 * @handle: amdgpu_device pointer 327 * 328 * HW fini and suspend VCN block 329 */ 330 static int vcn_v4_0_suspend(void *handle) 331 { 332 int r; 333 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 334 335 r = vcn_v4_0_hw_fini(adev); 336 if (r) 337 return r; 338 339 r = amdgpu_vcn_suspend(adev); 340 341 return r; 342 } 343 344 /** 345 * vcn_v4_0_resume - resume VCN block 346 * 347 * @handle: amdgpu_device pointer 348 * 349 * Resume firmware and hw init VCN block 350 */ 351 static int vcn_v4_0_resume(void *handle) 352 { 353 int r; 354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 355 356 r = amdgpu_vcn_resume(adev); 357 if (r) 358 return r; 359 360 r = vcn_v4_0_hw_init(adev); 361 362 return r; 363 } 364 365 /** 366 * vcn_v4_0_mc_resume - memory controller programming 367 * 368 * @adev: amdgpu_device pointer 369 * @inst: instance number 370 * 371 * Let the VCN memory controller know it's offsets 372 */ 373 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 374 { 375 uint32_t offset, size; 376 const struct common_firmware_header *hdr; 377 378 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 379 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 380 381 /* cache window 0: fw */ 382 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 383 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 384 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 385 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 386 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 387 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 388 offset = 0; 389 } else { 390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 391 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 392 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 393 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 394 offset = size; 395 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 396 } 397 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 398 399 /* cache window 1: stack */ 400 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 401 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 402 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 403 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 404 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 405 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 406 407 /* cache window 2: context */ 408 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 409 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 410 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 411 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 412 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 413 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 414 415 /* non-cache window */ 416 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 417 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 418 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 419 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 420 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 421 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 422 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 423 } 424 425 /** 426 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 427 * 428 * @adev: amdgpu_device pointer 429 * @inst_idx: instance number index 430 * @indirect: indirectly write sram 431 * 432 * Let the VCN memory controller know it's offsets with dpg mode 433 */ 434 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 435 { 436 uint32_t offset, size; 437 const struct common_firmware_header *hdr; 438 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 439 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 440 441 /* cache window 0: fw */ 442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 443 if (!indirect) { 444 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 445 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 446 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 447 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 449 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 450 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 451 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 452 } else { 453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 454 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 455 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 456 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 457 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 458 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 459 } 460 offset = 0; 461 } else { 462 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 463 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 464 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 467 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 468 offset = size; 469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 470 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 471 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 472 } 473 474 if (!indirect) 475 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 476 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 477 else 478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 479 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 480 481 /* cache window 1: stack */ 482 if (!indirect) { 483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 484 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 486 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 487 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 488 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 491 } else { 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 495 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 496 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 497 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 498 } 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 501 502 /* cache window 2: context */ 503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 504 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 505 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 508 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 512 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 513 514 /* non-cache window */ 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 517 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 520 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 525 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 526 527 /* VCN global tiling registers */ 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 530 } 531 532 /** 533 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 534 * 535 * @adev: amdgpu_device pointer 536 * @inst: instance number 537 * 538 * Disable static power gating for VCN block 539 */ 540 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 541 { 542 uint32_t data = 0; 543 544 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 545 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 546 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 547 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 548 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 549 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 550 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 551 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 552 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 553 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 554 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 555 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 556 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 557 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 558 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 559 560 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 561 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 562 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 563 } else { 564 uint32_t value; 565 566 value = (inst) ? 0x2200800 : 0; 567 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 568 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 569 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 570 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 571 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 572 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 573 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 574 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 575 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 576 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 577 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 578 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 579 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 580 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 581 582 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 583 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 584 } 585 586 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 587 data &= ~0x103; 588 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 589 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 590 UVD_POWER_STATUS__UVD_PG_EN_MASK; 591 592 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 593 594 return; 595 } 596 597 /** 598 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 599 * 600 * @adev: amdgpu_device pointer 601 * @inst: instance number 602 * 603 * Enable static power gating for VCN block 604 */ 605 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 606 { 607 uint32_t data; 608 609 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 610 /* Before power off, this indicator has to be turned on */ 611 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 612 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 613 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 614 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 615 616 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 617 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 618 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 619 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 620 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 624 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 625 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 626 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 627 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 628 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 629 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 630 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 631 632 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 633 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 634 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 635 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 636 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 637 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 638 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 639 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 640 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 641 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 642 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 643 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 644 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 645 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 646 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 647 } 648 649 return; 650 } 651 652 /** 653 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 654 * 655 * @adev: amdgpu_device pointer 656 * @inst: instance number 657 * 658 * Disable clock gating for VCN block 659 */ 660 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 661 { 662 uint32_t data; 663 664 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 665 return; 666 667 /* VCN disable CGC */ 668 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 669 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 670 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 671 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 672 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 673 674 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 675 data &= ~(UVD_CGC_GATE__SYS_MASK 676 | UVD_CGC_GATE__UDEC_MASK 677 | UVD_CGC_GATE__MPEG2_MASK 678 | UVD_CGC_GATE__REGS_MASK 679 | UVD_CGC_GATE__RBC_MASK 680 | UVD_CGC_GATE__LMI_MC_MASK 681 | UVD_CGC_GATE__LMI_UMC_MASK 682 | UVD_CGC_GATE__IDCT_MASK 683 | UVD_CGC_GATE__MPRD_MASK 684 | UVD_CGC_GATE__MPC_MASK 685 | UVD_CGC_GATE__LBSI_MASK 686 | UVD_CGC_GATE__LRBBM_MASK 687 | UVD_CGC_GATE__UDEC_RE_MASK 688 | UVD_CGC_GATE__UDEC_CM_MASK 689 | UVD_CGC_GATE__UDEC_IT_MASK 690 | UVD_CGC_GATE__UDEC_DB_MASK 691 | UVD_CGC_GATE__UDEC_MP_MASK 692 | UVD_CGC_GATE__WCB_MASK 693 | UVD_CGC_GATE__VCPU_MASK 694 | UVD_CGC_GATE__MMSCH_MASK); 695 696 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 697 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 698 699 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 700 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 701 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 702 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 703 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 704 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 705 | UVD_CGC_CTRL__SYS_MODE_MASK 706 | UVD_CGC_CTRL__UDEC_MODE_MASK 707 | UVD_CGC_CTRL__MPEG2_MODE_MASK 708 | UVD_CGC_CTRL__REGS_MODE_MASK 709 | UVD_CGC_CTRL__RBC_MODE_MASK 710 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 711 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 712 | UVD_CGC_CTRL__IDCT_MODE_MASK 713 | UVD_CGC_CTRL__MPRD_MODE_MASK 714 | UVD_CGC_CTRL__MPC_MODE_MASK 715 | UVD_CGC_CTRL__LBSI_MODE_MASK 716 | UVD_CGC_CTRL__LRBBM_MODE_MASK 717 | UVD_CGC_CTRL__WCB_MODE_MASK 718 | UVD_CGC_CTRL__VCPU_MODE_MASK 719 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 720 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 721 722 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 723 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 724 | UVD_SUVD_CGC_GATE__SIT_MASK 725 | UVD_SUVD_CGC_GATE__SMP_MASK 726 | UVD_SUVD_CGC_GATE__SCM_MASK 727 | UVD_SUVD_CGC_GATE__SDB_MASK 728 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 729 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 730 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 731 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 732 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 733 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 734 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 735 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 736 | UVD_SUVD_CGC_GATE__SCLR_MASK 737 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 738 | UVD_SUVD_CGC_GATE__ENT_MASK 739 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 740 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 741 | UVD_SUVD_CGC_GATE__SITE_MASK 742 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 743 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 744 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 745 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 746 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 747 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 748 749 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 750 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 751 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 752 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 753 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 754 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 755 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 756 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 760 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 761 } 762 763 /** 764 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 765 * 766 * @adev: amdgpu_device pointer 767 * @sram_sel: sram select 768 * @inst_idx: instance number index 769 * @indirect: indirectly write sram 770 * 771 * Disable clock gating for VCN block with dpg mode 772 */ 773 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 774 int inst_idx, uint8_t indirect) 775 { 776 uint32_t reg_data = 0; 777 778 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 779 return; 780 781 /* enable sw clock gating control */ 782 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 783 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 784 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 785 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 786 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 787 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 788 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 789 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 790 UVD_CGC_CTRL__SYS_MODE_MASK | 791 UVD_CGC_CTRL__UDEC_MODE_MASK | 792 UVD_CGC_CTRL__MPEG2_MODE_MASK | 793 UVD_CGC_CTRL__REGS_MODE_MASK | 794 UVD_CGC_CTRL__RBC_MODE_MASK | 795 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 796 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 797 UVD_CGC_CTRL__IDCT_MODE_MASK | 798 UVD_CGC_CTRL__MPRD_MODE_MASK | 799 UVD_CGC_CTRL__MPC_MODE_MASK | 800 UVD_CGC_CTRL__LBSI_MODE_MASK | 801 UVD_CGC_CTRL__LRBBM_MODE_MASK | 802 UVD_CGC_CTRL__WCB_MODE_MASK | 803 UVD_CGC_CTRL__VCPU_MODE_MASK); 804 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 805 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 806 807 /* turn off clock gating */ 808 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 809 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 810 811 /* turn on SUVD clock gating */ 812 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 813 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 814 815 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 816 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 817 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 818 } 819 820 /** 821 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 822 * 823 * @adev: amdgpu_device pointer 824 * @inst: instance number 825 * 826 * Enable clock gating for VCN block 827 */ 828 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 829 { 830 uint32_t data; 831 832 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 833 return; 834 835 /* enable VCN CGC */ 836 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 837 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 838 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 839 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 840 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 841 842 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 843 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 844 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 845 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 846 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 847 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 848 | UVD_CGC_CTRL__SYS_MODE_MASK 849 | UVD_CGC_CTRL__UDEC_MODE_MASK 850 | UVD_CGC_CTRL__MPEG2_MODE_MASK 851 | UVD_CGC_CTRL__REGS_MODE_MASK 852 | UVD_CGC_CTRL__RBC_MODE_MASK 853 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 854 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 855 | UVD_CGC_CTRL__IDCT_MODE_MASK 856 | UVD_CGC_CTRL__MPRD_MODE_MASK 857 | UVD_CGC_CTRL__MPC_MODE_MASK 858 | UVD_CGC_CTRL__LBSI_MODE_MASK 859 | UVD_CGC_CTRL__LRBBM_MODE_MASK 860 | UVD_CGC_CTRL__WCB_MODE_MASK 861 | UVD_CGC_CTRL__VCPU_MODE_MASK 862 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 863 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 864 865 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 866 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 867 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 868 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 869 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 870 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 871 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 872 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 873 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 874 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 875 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 876 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 877 } 878 879 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 880 bool indirect) 881 { 882 uint32_t tmp; 883 884 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 885 return; 886 887 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 888 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 889 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 890 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 891 WREG32_SOC15_DPG_MODE(inst_idx, 892 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 893 tmp, 0, indirect); 894 895 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 896 WREG32_SOC15_DPG_MODE(inst_idx, 897 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 898 tmp, 0, indirect); 899 } 900 901 /** 902 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 903 * 904 * @adev: amdgpu_device pointer 905 * @inst_idx: instance number index 906 * @indirect: indirectly write sram 907 * 908 * Start VCN block with dpg mode 909 */ 910 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 911 { 912 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 913 struct amdgpu_ring *ring; 914 uint32_t tmp; 915 916 /* disable register anti-hang mechanism */ 917 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 918 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 919 /* enable dynamic power gating mode */ 920 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 921 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 922 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 923 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 924 925 if (indirect) 926 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 927 928 /* enable clock gating */ 929 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 930 931 /* enable VCPU clock */ 932 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 933 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 934 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 935 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 936 937 /* disable master interupt */ 938 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 939 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 940 941 /* setup regUVD_LMI_CTRL */ 942 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 943 UVD_LMI_CTRL__REQ_MODE_MASK | 944 UVD_LMI_CTRL__CRC_RESET_MASK | 945 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 946 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 947 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 948 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 949 0x00100000L); 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 952 953 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 954 VCN, inst_idx, regUVD_MPC_CNTL), 955 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 956 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 959 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 960 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 961 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 962 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 963 964 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 965 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 966 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 967 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 968 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 969 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 970 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, regUVD_MPC_SET_MUX), 973 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 974 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 975 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 976 977 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 978 979 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 980 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 981 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 982 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 983 984 /* enable LMI MC and UMC channels */ 985 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 988 989 vcn_v4_0_enable_ras(adev, inst_idx, indirect); 990 991 /* enable master interrupt */ 992 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 993 VCN, inst_idx, regUVD_MASTINT_EN), 994 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 995 996 997 if (indirect) 998 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 999 1000 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1001 1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1003 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1004 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1005 1006 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1007 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1008 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1009 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1010 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1011 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1012 1013 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1014 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1015 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1016 1017 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1018 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1019 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1020 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1021 1022 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1023 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1024 VCN_RB1_DB_CTRL__EN_MASK); 1025 1026 return 0; 1027 } 1028 1029 1030 /** 1031 * vcn_v4_0_start - VCN start 1032 * 1033 * @adev: amdgpu_device pointer 1034 * 1035 * Start VCN block 1036 */ 1037 static int vcn_v4_0_start(struct amdgpu_device *adev) 1038 { 1039 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1040 struct amdgpu_ring *ring; 1041 uint32_t tmp; 1042 int i, j, k, r; 1043 1044 if (adev->pm.dpm_enabled) 1045 amdgpu_dpm_enable_uvd(adev, true); 1046 1047 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1048 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1049 1050 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1051 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1052 continue; 1053 } 1054 1055 /* disable VCN power gating */ 1056 vcn_v4_0_disable_static_power_gating(adev, i); 1057 1058 /* set VCN status busy */ 1059 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1060 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1061 1062 /*SW clock gating */ 1063 vcn_v4_0_disable_clock_gating(adev, i); 1064 1065 /* enable VCPU clock */ 1066 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1067 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1068 1069 /* disable master interrupt */ 1070 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1071 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1072 1073 /* enable LMI MC and UMC channels */ 1074 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1075 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1076 1077 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1078 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1079 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1080 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1081 1082 /* setup regUVD_LMI_CTRL */ 1083 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1084 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1085 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1086 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1087 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1088 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1089 1090 /* setup regUVD_MPC_CNTL */ 1091 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1092 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1093 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1094 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1095 1096 /* setup UVD_MPC_SET_MUXA0 */ 1097 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1098 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1099 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1100 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1101 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1102 1103 /* setup UVD_MPC_SET_MUXB0 */ 1104 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1105 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1106 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1107 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1108 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1109 1110 /* setup UVD_MPC_SET_MUX */ 1111 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1112 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1113 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1114 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1115 1116 vcn_v4_0_mc_resume(adev, i); 1117 1118 /* VCN global tiling registers */ 1119 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1120 adev->gfx.config.gb_addr_config); 1121 1122 /* unblock VCPU register access */ 1123 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1124 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1125 1126 /* release VCPU reset to boot */ 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1128 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1129 1130 for (j = 0; j < 10; ++j) { 1131 uint32_t status; 1132 1133 for (k = 0; k < 100; ++k) { 1134 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1135 if (status & 2) 1136 break; 1137 mdelay(10); 1138 if (amdgpu_emu_mode == 1) 1139 msleep(1); 1140 } 1141 1142 if (amdgpu_emu_mode == 1) { 1143 r = -1; 1144 if (status & 2) { 1145 r = 0; 1146 break; 1147 } 1148 } else { 1149 r = 0; 1150 if (status & 2) 1151 break; 1152 1153 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1154 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1155 UVD_VCPU_CNTL__BLK_RST_MASK, 1156 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1157 mdelay(10); 1158 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1159 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1160 1161 mdelay(10); 1162 r = -1; 1163 } 1164 } 1165 1166 if (r) { 1167 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1168 return r; 1169 } 1170 1171 /* enable master interrupt */ 1172 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1173 UVD_MASTINT_EN__VCPU_EN_MASK, 1174 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1175 1176 /* clear the busy bit of VCN_STATUS */ 1177 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1178 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1179 1180 ring = &adev->vcn.inst[i].ring_enc[0]; 1181 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1182 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1183 VCN_RB1_DB_CTRL__EN_MASK); 1184 1185 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1186 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1187 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1188 1189 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1190 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1191 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1192 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1193 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1194 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1195 1196 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1197 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1198 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1199 1200 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1201 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1202 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1203 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1204 } 1205 1206 return 0; 1207 } 1208 1209 static int vcn_v4_0_init_ring_metadata(struct amdgpu_device *adev, uint32_t vcn_inst, struct amdgpu_ring *ring_enc) 1210 { 1211 struct amdgpu_vcn_rb_metadata *rb_metadata = NULL; 1212 uint8_t *rb_ptr = (uint8_t *)ring_enc->ring; 1213 1214 rb_ptr += ring_enc->ring_size; 1215 rb_metadata = (struct amdgpu_vcn_rb_metadata *)rb_ptr; 1216 1217 memset(rb_metadata, 0, sizeof(struct amdgpu_vcn_rb_metadata)); 1218 rb_metadata->size = sizeof(struct amdgpu_vcn_rb_metadata); 1219 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1220 rb_metadata->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1221 rb_metadata->version = 1; 1222 rb_metadata->ring_id = vcn_inst & 0xFF; 1223 1224 return 0; 1225 } 1226 1227 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1228 { 1229 int i; 1230 struct amdgpu_ring *ring_enc; 1231 uint64_t cache_addr; 1232 uint64_t rb_enc_addr; 1233 uint64_t ctx_addr; 1234 uint32_t param, resp, expected; 1235 uint32_t offset, cache_size; 1236 uint32_t tmp, timeout; 1237 1238 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1239 uint32_t *table_loc; 1240 uint32_t table_size; 1241 uint32_t size, size_dw; 1242 uint32_t init_status; 1243 uint32_t enabled_vcn; 1244 1245 struct mmsch_v4_0_cmd_direct_write 1246 direct_wt = { {0} }; 1247 struct mmsch_v4_0_cmd_direct_read_modify_write 1248 direct_rd_mod_wt = { {0} }; 1249 struct mmsch_v4_0_cmd_end end = { {0} }; 1250 struct mmsch_v4_0_init_header header; 1251 1252 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1253 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1254 1255 direct_wt.cmd_header.command_type = 1256 MMSCH_COMMAND__DIRECT_REG_WRITE; 1257 direct_rd_mod_wt.cmd_header.command_type = 1258 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1259 end.cmd_header.command_type = 1260 MMSCH_COMMAND__END; 1261 1262 header.version = MMSCH_VERSION; 1263 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1264 for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) { 1265 header.inst[i].init_status = 0; 1266 header.inst[i].table_offset = 0; 1267 header.inst[i].table_size = 0; 1268 } 1269 1270 table_loc = (uint32_t *)table->cpu_addr; 1271 table_loc += header.total_size; 1272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1273 if (adev->vcn.harvest_config & (1 << i)) 1274 continue; 1275 1276 table_size = 0; 1277 1278 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1279 regUVD_STATUS), 1280 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1281 1282 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1283 1284 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1285 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1286 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1287 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1288 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1289 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1290 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1291 offset = 0; 1292 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1293 regUVD_VCPU_CACHE_OFFSET0), 1294 0); 1295 } else { 1296 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1297 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1298 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1299 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1300 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1301 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1302 offset = cache_size; 1303 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1304 regUVD_VCPU_CACHE_OFFSET0), 1305 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1306 } 1307 1308 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1309 regUVD_VCPU_CACHE_SIZE0), 1310 cache_size); 1311 1312 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1313 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1314 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1315 lower_32_bits(cache_addr)); 1316 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1317 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1318 upper_32_bits(cache_addr)); 1319 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1320 regUVD_VCPU_CACHE_OFFSET1), 1321 0); 1322 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1323 regUVD_VCPU_CACHE_SIZE1), 1324 AMDGPU_VCN_STACK_SIZE); 1325 1326 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1327 AMDGPU_VCN_STACK_SIZE; 1328 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1329 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1330 lower_32_bits(cache_addr)); 1331 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1332 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1333 upper_32_bits(cache_addr)); 1334 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1335 regUVD_VCPU_CACHE_OFFSET2), 1336 0); 1337 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1338 regUVD_VCPU_CACHE_SIZE2), 1339 AMDGPU_VCN_CONTEXT_SIZE); 1340 1341 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1342 rb_setup = &fw_shared->rb_setup; 1343 1344 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1345 ring_enc->wptr = 0; 1346 rb_enc_addr = ring_enc->gpu_addr; 1347 1348 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1349 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1350 1351 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 1352 vcn_v4_0_init_ring_metadata(adev, i, ring_enc); 1353 1354 memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SETUP); 1355 if (!(adev->vcn.harvest_config & (1 << 0))) { 1356 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1357 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); 1358 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4; 1359 } 1360 if (!(adev->vcn.harvest_config & (1 << 1))) { 1361 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1362 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); 1363 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4; 1364 } 1365 fw_shared->decouple.is_enabled = 1; 1366 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_DECOUPLE_FLAG); 1367 } else { 1368 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1369 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1370 rb_setup->rb_size = ring_enc->ring_size / 4; 1371 } 1372 1373 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1374 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1375 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1376 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1377 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1378 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1379 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1380 regUVD_VCPU_NONCACHE_SIZE0), 1381 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1382 1383 /* add end packet */ 1384 MMSCH_V4_0_INSERT_END(); 1385 1386 /* refine header */ 1387 header.inst[i].init_status = 0; 1388 header.inst[i].table_offset = header.total_size; 1389 header.inst[i].table_size = table_size; 1390 header.total_size += table_size; 1391 } 1392 1393 /* Update init table header in memory */ 1394 size = sizeof(struct mmsch_v4_0_init_header); 1395 table_loc = (uint32_t *)table->cpu_addr; 1396 memcpy((void *)table_loc, &header, size); 1397 1398 /* message MMSCH (in VCN[0]) to initialize this client 1399 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1400 * of memory descriptor location 1401 */ 1402 ctx_addr = table->gpu_addr; 1403 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1404 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1405 1406 /* 2, update vmid of descriptor */ 1407 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1408 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1409 /* use domain0 for MM scheduler */ 1410 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1411 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1412 1413 /* 3, notify mmsch about the size of this descriptor */ 1414 size = header.total_size; 1415 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1416 1417 /* 4, set resp to zero */ 1418 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1419 1420 /* 5, kick off the initialization and wait until 1421 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1422 */ 1423 param = 0x00000001; 1424 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1425 tmp = 0; 1426 timeout = 1000; 1427 resp = 0; 1428 expected = MMSCH_VF_MAILBOX_RESP__OK; 1429 while (resp != expected) { 1430 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1431 if (resp != 0) 1432 break; 1433 1434 udelay(10); 1435 tmp = tmp + 10; 1436 if (tmp >= timeout) { 1437 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1438 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1439 "(expected=0x%08x, readback=0x%08x)\n", 1440 tmp, expected, resp); 1441 return -EBUSY; 1442 } 1443 } 1444 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1445 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1446 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1447 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1448 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1449 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1450 1451 return 0; 1452 } 1453 1454 /** 1455 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1456 * 1457 * @adev: amdgpu_device pointer 1458 * @inst_idx: instance number index 1459 * 1460 * Stop VCN block with dpg mode 1461 */ 1462 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1463 { 1464 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1465 uint32_t tmp; 1466 1467 vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state); 1468 /* Wait for power status to be 1 */ 1469 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1470 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1471 1472 /* wait for read ptr to be equal to write ptr */ 1473 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1474 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1475 1476 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1477 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1478 1479 /* disable dynamic power gating mode */ 1480 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1481 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1482 } 1483 1484 /** 1485 * vcn_v4_0_stop - VCN stop 1486 * 1487 * @adev: amdgpu_device pointer 1488 * 1489 * Stop VCN block 1490 */ 1491 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1492 { 1493 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1494 uint32_t tmp; 1495 int i, r = 0; 1496 1497 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1498 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1499 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1500 1501 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1502 vcn_v4_0_stop_dpg_mode(adev, i); 1503 continue; 1504 } 1505 1506 /* wait for vcn idle */ 1507 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1508 if (r) 1509 return r; 1510 1511 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1512 UVD_LMI_STATUS__READ_CLEAN_MASK | 1513 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1514 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1515 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1516 if (r) 1517 return r; 1518 1519 /* disable LMI UMC channel */ 1520 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1521 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1522 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1523 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1524 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1525 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1526 if (r) 1527 return r; 1528 1529 /* block VCPU register access */ 1530 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1531 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1532 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1533 1534 /* reset VCPU */ 1535 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1536 UVD_VCPU_CNTL__BLK_RST_MASK, 1537 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1538 1539 /* disable VCPU clock */ 1540 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1541 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1542 1543 /* apply soft reset */ 1544 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1545 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1546 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1547 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1548 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1549 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1550 1551 /* clear status */ 1552 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1553 1554 /* apply HW clock gating */ 1555 vcn_v4_0_enable_clock_gating(adev, i); 1556 1557 /* enable VCN power gating */ 1558 vcn_v4_0_enable_static_power_gating(adev, i); 1559 } 1560 1561 if (adev->pm.dpm_enabled) 1562 amdgpu_dpm_enable_uvd(adev, false); 1563 1564 return 0; 1565 } 1566 1567 /** 1568 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1569 * 1570 * @adev: amdgpu_device pointer 1571 * @inst_idx: instance number index 1572 * @new_state: pause state 1573 * 1574 * Pause dpg mode for VCN block 1575 */ 1576 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1577 struct dpg_pause_state *new_state) 1578 { 1579 uint32_t reg_data = 0; 1580 int ret_code; 1581 1582 /* pause/unpause if state is changed */ 1583 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1584 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1585 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1586 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1587 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1588 1589 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1590 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1591 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1592 1593 if (!ret_code) { 1594 /* pause DPG */ 1595 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1596 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1597 1598 /* wait for ACK */ 1599 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1600 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1601 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1602 1603 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1604 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1605 } 1606 } else { 1607 /* unpause dpg, no need to wait */ 1608 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1609 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1610 } 1611 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1612 } 1613 1614 return 0; 1615 } 1616 1617 /** 1618 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1619 * 1620 * @ring: amdgpu_ring pointer 1621 * 1622 * Returns the current hardware unified read pointer 1623 */ 1624 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1625 { 1626 struct amdgpu_device *adev = ring->adev; 1627 1628 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1629 DRM_ERROR("wrong ring id is identified in %s", __func__); 1630 1631 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1632 } 1633 1634 /** 1635 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1636 * 1637 * @ring: amdgpu_ring pointer 1638 * 1639 * Returns the current hardware unified write pointer 1640 */ 1641 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1642 { 1643 struct amdgpu_device *adev = ring->adev; 1644 1645 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1646 DRM_ERROR("wrong ring id is identified in %s", __func__); 1647 1648 if (ring->use_doorbell) 1649 return *ring->wptr_cpu_addr; 1650 else 1651 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1652 } 1653 1654 /** 1655 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1656 * 1657 * @ring: amdgpu_ring pointer 1658 * 1659 * Commits the enc write pointer to the hardware 1660 */ 1661 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1662 { 1663 struct amdgpu_device *adev = ring->adev; 1664 1665 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1666 DRM_ERROR("wrong ring id is identified in %s", __func__); 1667 1668 if (ring->use_doorbell) { 1669 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1670 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1671 } else { 1672 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1673 } 1674 } 1675 1676 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1677 struct amdgpu_job *job) 1678 { 1679 struct drm_gpu_scheduler **scheds; 1680 1681 /* The create msg must be in the first IB submitted */ 1682 if (atomic_read(&job->base.entity->fence_seq)) 1683 return -EINVAL; 1684 1685 /* if VCN0 is harvested, we can't support AV1 */ 1686 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1687 return -EINVAL; 1688 1689 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1690 [AMDGPU_RING_PRIO_0].sched; 1691 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1692 return 0; 1693 } 1694 1695 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1696 uint64_t addr) 1697 { 1698 struct ttm_operation_ctx ctx = { false, false }; 1699 struct amdgpu_bo_va_mapping *map; 1700 uint32_t *msg, num_buffers; 1701 struct amdgpu_bo *bo; 1702 uint64_t start, end; 1703 unsigned int i; 1704 void *ptr; 1705 int r; 1706 1707 addr &= AMDGPU_GMC_HOLE_MASK; 1708 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1709 if (r) { 1710 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1711 return r; 1712 } 1713 1714 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1715 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1716 if (addr & 0x7) { 1717 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1718 return -EINVAL; 1719 } 1720 1721 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1722 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1723 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1724 if (r) { 1725 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1726 return r; 1727 } 1728 1729 r = amdgpu_bo_kmap(bo, &ptr); 1730 if (r) { 1731 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1732 return r; 1733 } 1734 1735 msg = ptr + addr - start; 1736 1737 /* Check length */ 1738 if (msg[1] > end - addr) { 1739 r = -EINVAL; 1740 goto out; 1741 } 1742 1743 if (msg[3] != RDECODE_MSG_CREATE) 1744 goto out; 1745 1746 num_buffers = msg[2]; 1747 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1748 uint32_t offset, size, *create; 1749 1750 if (msg[0] != RDECODE_MESSAGE_CREATE) 1751 continue; 1752 1753 offset = msg[1]; 1754 size = msg[2]; 1755 1756 if (offset + size > end) { 1757 r = -EINVAL; 1758 goto out; 1759 } 1760 1761 create = ptr + addr + offset - start; 1762 1763 /* H264, HEVC and VP9 can run on any instance */ 1764 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1765 continue; 1766 1767 r = vcn_v4_0_limit_sched(p, job); 1768 if (r) 1769 goto out; 1770 } 1771 1772 out: 1773 amdgpu_bo_kunmap(bo); 1774 return r; 1775 } 1776 1777 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1778 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1779 1780 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1781 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1782 1783 #define RENCODE_ENCODE_STANDARD_AV1 2 1784 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1785 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1786 1787 /* return the offset in ib if id is found, -1 otherwise 1788 * to speed up the searching we only search upto max_offset 1789 */ 1790 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1791 { 1792 int i; 1793 1794 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1795 if (ib->ptr[i + 1] == id) 1796 return i; 1797 } 1798 return -1; 1799 } 1800 1801 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1802 struct amdgpu_job *job, 1803 struct amdgpu_ib *ib) 1804 { 1805 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1806 struct amdgpu_vcn_decode_buffer *decode_buffer; 1807 uint64_t addr; 1808 uint32_t val; 1809 int idx; 1810 1811 /* The first instance can decode anything */ 1812 if (!ring->me) 1813 return 0; 1814 1815 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1816 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1817 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1818 if (idx < 0) /* engine info is missing */ 1819 return 0; 1820 1821 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1822 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1823 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1824 1825 if (!(decode_buffer->valid_buf_flag & 0x1)) 1826 return 0; 1827 1828 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1829 decode_buffer->msg_buffer_address_lo; 1830 return vcn_v4_0_dec_msg(p, job, addr); 1831 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1832 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1833 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1834 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1835 return vcn_v4_0_limit_sched(p, job); 1836 } 1837 return 0; 1838 } 1839 1840 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1841 .type = AMDGPU_RING_TYPE_VCN_ENC, 1842 .align_mask = 0x3f, 1843 .nop = VCN_ENC_CMD_NO_OP, 1844 .extra_dw = sizeof(struct amdgpu_vcn_rb_metadata), 1845 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1846 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1847 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1848 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1849 .emit_frame_size = 1850 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1851 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1852 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1853 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1854 1, /* vcn_v2_0_enc_ring_insert_end */ 1855 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1856 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1857 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1858 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1859 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1860 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1861 .insert_nop = amdgpu_ring_insert_nop, 1862 .insert_end = vcn_v2_0_enc_ring_insert_end, 1863 .pad_ib = amdgpu_ring_generic_pad_ib, 1864 .begin_use = amdgpu_vcn_ring_begin_use, 1865 .end_use = amdgpu_vcn_ring_end_use, 1866 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1867 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1868 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1869 }; 1870 1871 /** 1872 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1873 * 1874 * @adev: amdgpu_device pointer 1875 * 1876 * Set unified ring functions 1877 */ 1878 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1879 { 1880 int i; 1881 1882 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1883 if (adev->vcn.harvest_config & (1 << i)) 1884 continue; 1885 1886 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2)) 1887 vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true; 1888 1889 adev->vcn.inst[i].ring_enc[0].funcs = 1890 (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs; 1891 adev->vcn.inst[i].ring_enc[0].me = i; 1892 1893 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1894 } 1895 } 1896 1897 /** 1898 * vcn_v4_0_is_idle - check VCN block is idle 1899 * 1900 * @handle: amdgpu_device pointer 1901 * 1902 * Check whether VCN block is idle 1903 */ 1904 static bool vcn_v4_0_is_idle(void *handle) 1905 { 1906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1907 int i, ret = 1; 1908 1909 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1910 if (adev->vcn.harvest_config & (1 << i)) 1911 continue; 1912 1913 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1914 } 1915 1916 return ret; 1917 } 1918 1919 /** 1920 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1921 * 1922 * @handle: amdgpu_device pointer 1923 * 1924 * Wait for VCN block idle 1925 */ 1926 static int vcn_v4_0_wait_for_idle(void *handle) 1927 { 1928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1929 int i, ret = 0; 1930 1931 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1932 if (adev->vcn.harvest_config & (1 << i)) 1933 continue; 1934 1935 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1936 UVD_STATUS__IDLE); 1937 if (ret) 1938 return ret; 1939 } 1940 1941 return ret; 1942 } 1943 1944 /** 1945 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1946 * 1947 * @handle: amdgpu_device pointer 1948 * @state: clock gating state 1949 * 1950 * Set VCN block clockgating state 1951 */ 1952 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1953 { 1954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1955 bool enable = state == AMD_CG_STATE_GATE; 1956 int i; 1957 1958 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1959 if (adev->vcn.harvest_config & (1 << i)) 1960 continue; 1961 1962 if (enable) { 1963 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1964 return -EBUSY; 1965 vcn_v4_0_enable_clock_gating(adev, i); 1966 } else { 1967 vcn_v4_0_disable_clock_gating(adev, i); 1968 } 1969 } 1970 1971 return 0; 1972 } 1973 1974 /** 1975 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1976 * 1977 * @handle: amdgpu_device pointer 1978 * @state: power gating state 1979 * 1980 * Set VCN block powergating state 1981 */ 1982 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1983 { 1984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1985 int ret; 1986 1987 /* for SRIOV, guest should not control VCN Power-gating 1988 * MMSCH FW should control Power-gating and clock-gating 1989 * guest should avoid touching CGC and PG 1990 */ 1991 if (amdgpu_sriov_vf(adev)) { 1992 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1993 return 0; 1994 } 1995 1996 if (state == adev->vcn.cur_state) 1997 return 0; 1998 1999 if (state == AMD_PG_STATE_GATE) 2000 ret = vcn_v4_0_stop(adev); 2001 else 2002 ret = vcn_v4_0_start(adev); 2003 2004 if (!ret) 2005 adev->vcn.cur_state = state; 2006 2007 return ret; 2008 } 2009 2010 /** 2011 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 2012 * 2013 * @adev: amdgpu_device pointer 2014 * @source: interrupt sources 2015 * @type: interrupt types 2016 * @state: interrupt states 2017 * 2018 * Set VCN block interrupt state 2019 */ 2020 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2021 unsigned type, enum amdgpu_interrupt_state state) 2022 { 2023 return 0; 2024 } 2025 2026 /** 2027 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state 2028 * 2029 * @adev: amdgpu_device pointer 2030 * @source: interrupt sources 2031 * @type: interrupt types 2032 * @state: interrupt states 2033 * 2034 * Set VCN block RAS interrupt state 2035 */ 2036 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 2037 struct amdgpu_irq_src *source, 2038 unsigned int type, 2039 enum amdgpu_interrupt_state state) 2040 { 2041 return 0; 2042 } 2043 2044 /** 2045 * vcn_v4_0_process_interrupt - process VCN block interrupt 2046 * 2047 * @adev: amdgpu_device pointer 2048 * @source: interrupt sources 2049 * @entry: interrupt entry from clients and sources 2050 * 2051 * Process VCN block interrupt 2052 */ 2053 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2054 struct amdgpu_iv_entry *entry) 2055 { 2056 uint32_t ip_instance; 2057 2058 if (amdgpu_sriov_is_vcn_rb_decouple(adev)) { 2059 ip_instance = entry->ring_id; 2060 } else { 2061 switch (entry->client_id) { 2062 case SOC15_IH_CLIENTID_VCN: 2063 ip_instance = 0; 2064 break; 2065 case SOC15_IH_CLIENTID_VCN1: 2066 ip_instance = 1; 2067 break; 2068 default: 2069 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2070 return 0; 2071 } 2072 } 2073 2074 DRM_DEBUG("IH: VCN TRAP\n"); 2075 2076 switch (entry->src_id) { 2077 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2078 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2079 break; 2080 default: 2081 DRM_ERROR("Unhandled interrupt: %d %d\n", 2082 entry->src_id, entry->src_data[0]); 2083 break; 2084 } 2085 2086 return 0; 2087 } 2088 2089 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2090 .set = vcn_v4_0_set_interrupt_state, 2091 .process = vcn_v4_0_process_interrupt, 2092 }; 2093 2094 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = { 2095 .set = vcn_v4_0_set_ras_interrupt_state, 2096 .process = amdgpu_vcn_process_poison_irq, 2097 }; 2098 2099 /** 2100 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 2101 * 2102 * @adev: amdgpu_device pointer 2103 * 2104 * Set VCN block interrupt irq functions 2105 */ 2106 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2107 { 2108 int i; 2109 2110 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2111 if (adev->vcn.harvest_config & (1 << i)) 2112 continue; 2113 2114 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2115 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2116 2117 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; 2118 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs; 2119 } 2120 } 2121 2122 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2123 .name = "vcn_v4_0", 2124 .early_init = vcn_v4_0_early_init, 2125 .late_init = NULL, 2126 .sw_init = vcn_v4_0_sw_init, 2127 .sw_fini = vcn_v4_0_sw_fini, 2128 .hw_init = vcn_v4_0_hw_init, 2129 .hw_fini = vcn_v4_0_hw_fini, 2130 .suspend = vcn_v4_0_suspend, 2131 .resume = vcn_v4_0_resume, 2132 .is_idle = vcn_v4_0_is_idle, 2133 .wait_for_idle = vcn_v4_0_wait_for_idle, 2134 .check_soft_reset = NULL, 2135 .pre_soft_reset = NULL, 2136 .soft_reset = NULL, 2137 .post_soft_reset = NULL, 2138 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2139 .set_powergating_state = vcn_v4_0_set_powergating_state, 2140 }; 2141 2142 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { 2143 .type = AMD_IP_BLOCK_TYPE_VCN, 2144 .major = 4, 2145 .minor = 0, 2146 .rev = 0, 2147 .funcs = &vcn_v4_0_ip_funcs, 2148 }; 2149 2150 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2151 uint32_t instance, uint32_t sub_block) 2152 { 2153 uint32_t poison_stat = 0, reg_value = 0; 2154 2155 switch (sub_block) { 2156 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2157 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2158 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2159 break; 2160 default: 2161 break; 2162 } 2163 2164 if (poison_stat) 2165 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2166 instance, sub_block); 2167 2168 return poison_stat; 2169 } 2170 2171 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2172 { 2173 uint32_t inst, sub; 2174 uint32_t poison_stat = 0; 2175 2176 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2177 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2178 poison_stat += 2179 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2180 2181 return !!poison_stat; 2182 } 2183 2184 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2185 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2186 }; 2187 2188 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2189 .ras_block = { 2190 .hw_ops = &vcn_v4_0_ras_hw_ops, 2191 .ras_late_init = amdgpu_vcn_ras_late_init, 2192 }, 2193 }; 2194 2195 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2196 { 2197 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2198 case IP_VERSION(4, 0, 0): 2199 adev->vcn.ras = &vcn_v4_0_ras; 2200 break; 2201 default: 2202 break; 2203 } 2204 } 2205