1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_hw_ip.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v4_0.h" 34 #include "vcn_v4_0.h" 35 36 #include "vcn/vcn_4_0_0_offset.h" 37 #include "vcn/vcn_4_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h" 39 40 #include <drm/drm_drv.h> 41 42 #define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL 43 #define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX 44 #define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA 45 #define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX 46 47 #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 48 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 49 50 #define VCN_HARVEST_MMSCH 0 51 52 #define RDECODE_MSG_CREATE 0x00000000 53 #define RDECODE_MESSAGE_CREATE 0x00000001 54 55 static int amdgpu_ih_clientid_vcns[] = { 56 SOC15_IH_CLIENTID_VCN, 57 SOC15_IH_CLIENTID_VCN1 58 }; 59 60 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev); 61 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev); 62 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev); 63 static int vcn_v4_0_set_powergating_state(void *handle, 64 enum amd_powergating_state state); 65 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, 66 int inst_idx, struct dpg_pause_state *new_state); 67 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring); 68 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); 69 70 /** 71 * vcn_v4_0_early_init - set function pointers and load microcode 72 * 73 * @handle: amdgpu_device pointer 74 * 75 * Set ring and irq function pointers 76 * Load microcode from filesystem 77 */ 78 static int vcn_v4_0_early_init(void *handle) 79 { 80 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 81 int i; 82 83 if (amdgpu_sriov_vf(adev)) { 84 adev->vcn.harvest_config = VCN_HARVEST_MMSCH; 85 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 86 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 87 adev->vcn.harvest_config |= 1 << i; 88 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i); 89 } 90 } 91 } 92 93 /* re-use enc ring as unified ring */ 94 adev->vcn.num_enc_rings = 1; 95 96 vcn_v4_0_set_unified_ring_funcs(adev); 97 vcn_v4_0_set_irq_funcs(adev); 98 vcn_v4_0_set_ras_funcs(adev); 99 100 return amdgpu_vcn_early_init(adev); 101 } 102 103 /** 104 * vcn_v4_0_sw_init - sw init for VCN block 105 * 106 * @handle: amdgpu_device pointer 107 * 108 * Load firmware and sw initialization 109 */ 110 static int vcn_v4_0_sw_init(void *handle) 111 { 112 struct amdgpu_ring *ring; 113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 114 int i, r; 115 116 r = amdgpu_vcn_sw_init(adev); 117 if (r) 118 return r; 119 120 amdgpu_vcn_setup_ucode(adev); 121 122 r = amdgpu_vcn_resume(adev); 123 if (r) 124 return r; 125 126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 127 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 128 129 if (adev->vcn.harvest_config & (1 << i)) 130 continue; 131 132 /* Init instance 0 sched_score to 1, so it's scheduled after other instances */ 133 if (i == 0) 134 atomic_set(&adev->vcn.inst[i].sched_score, 1); 135 else 136 atomic_set(&adev->vcn.inst[i].sched_score, 0); 137 138 /* VCN UNIFIED TRAP */ 139 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 140 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 141 if (r) 142 return r; 143 144 /* VCN POISON TRAP */ 145 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 146 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq); 147 if (r) 148 return r; 149 150 ring = &adev->vcn.inst[i].ring_enc[0]; 151 ring->use_doorbell = true; 152 if (amdgpu_sriov_vf(adev)) 153 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1; 154 else 155 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i; 156 ring->vm_hub = AMDGPU_MMHUB0(0); 157 sprintf(ring->name, "vcn_unified_%d", i); 158 159 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 160 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score); 161 if (r) 162 return r; 163 164 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 165 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); 166 fw_shared->sq.is_enabled = 1; 167 168 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); 169 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? 170 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; 171 172 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == 173 IP_VERSION(4, 0, 2)) { 174 fw_shared->present_flag_0 |= AMDGPU_FW_SHARED_FLAG_0_DRM_KEY_INJECT; 175 fw_shared->drm_key_wa.method = 176 AMDGPU_DRM_KEY_INJECT_WORKAROUND_VCNFW_ASD_HANDSHAKING; 177 } 178 179 if (amdgpu_sriov_vf(adev)) 180 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 181 182 if (amdgpu_vcnfw_log) 183 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 184 } 185 186 if (amdgpu_sriov_vf(adev)) { 187 r = amdgpu_virt_alloc_mm_table(adev); 188 if (r) 189 return r; 190 } 191 192 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 193 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode; 194 195 r = amdgpu_vcn_ras_sw_init(adev); 196 if (r) 197 return r; 198 199 return 0; 200 } 201 202 /** 203 * vcn_v4_0_sw_fini - sw fini for VCN block 204 * 205 * @handle: amdgpu_device pointer 206 * 207 * VCN suspend and free up sw allocation 208 */ 209 static int vcn_v4_0_sw_fini(void *handle) 210 { 211 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 212 int i, r, idx; 213 214 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 215 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 216 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 217 218 if (adev->vcn.harvest_config & (1 << i)) 219 continue; 220 221 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 222 fw_shared->present_flag_0 = 0; 223 fw_shared->sq.is_enabled = 0; 224 } 225 226 drm_dev_exit(idx); 227 } 228 229 if (amdgpu_sriov_vf(adev)) 230 amdgpu_virt_free_mm_table(adev); 231 232 r = amdgpu_vcn_suspend(adev); 233 if (r) 234 return r; 235 236 r = amdgpu_vcn_sw_fini(adev); 237 238 return r; 239 } 240 241 /** 242 * vcn_v4_0_hw_init - start and test VCN block 243 * 244 * @handle: amdgpu_device pointer 245 * 246 * Initialize the hardware, boot up the VCPU and do some testing 247 */ 248 static int vcn_v4_0_hw_init(void *handle) 249 { 250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 251 struct amdgpu_ring *ring; 252 int i, r; 253 254 if (amdgpu_sriov_vf(adev)) { 255 r = vcn_v4_0_start_sriov(adev); 256 if (r) 257 goto done; 258 259 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 260 if (adev->vcn.harvest_config & (1 << i)) 261 continue; 262 263 ring = &adev->vcn.inst[i].ring_enc[0]; 264 ring->wptr = 0; 265 ring->wptr_old = 0; 266 vcn_v4_0_unified_ring_set_wptr(ring); 267 ring->sched.ready = true; 268 269 } 270 } else { 271 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 272 if (adev->vcn.harvest_config & (1 << i)) 273 continue; 274 275 ring = &adev->vcn.inst[i].ring_enc[0]; 276 277 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 278 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i); 279 280 r = amdgpu_ring_test_helper(ring); 281 if (r) 282 goto done; 283 284 } 285 } 286 287 done: 288 if (!r) 289 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 290 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 291 292 return r; 293 } 294 295 /** 296 * vcn_v4_0_hw_fini - stop the hardware block 297 * 298 * @handle: amdgpu_device pointer 299 * 300 * Stop the VCN block, mark ring as not ready any more 301 */ 302 static int vcn_v4_0_hw_fini(void *handle) 303 { 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 int i; 306 307 cancel_delayed_work_sync(&adev->vcn.idle_work); 308 309 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 310 if (adev->vcn.harvest_config & (1 << i)) 311 continue; 312 if (!amdgpu_sriov_vf(adev)) { 313 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 314 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 315 RREG32_SOC15(VCN, i, regUVD_STATUS))) { 316 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 317 } 318 } 319 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 320 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 321 } 322 323 return 0; 324 } 325 326 /** 327 * vcn_v4_0_suspend - suspend VCN block 328 * 329 * @handle: amdgpu_device pointer 330 * 331 * HW fini and suspend VCN block 332 */ 333 static int vcn_v4_0_suspend(void *handle) 334 { 335 int r; 336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 337 338 r = vcn_v4_0_hw_fini(adev); 339 if (r) 340 return r; 341 342 r = amdgpu_vcn_suspend(adev); 343 344 return r; 345 } 346 347 /** 348 * vcn_v4_0_resume - resume VCN block 349 * 350 * @handle: amdgpu_device pointer 351 * 352 * Resume firmware and hw init VCN block 353 */ 354 static int vcn_v4_0_resume(void *handle) 355 { 356 int r; 357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 358 359 r = amdgpu_vcn_resume(adev); 360 if (r) 361 return r; 362 363 r = vcn_v4_0_hw_init(adev); 364 365 return r; 366 } 367 368 /** 369 * vcn_v4_0_mc_resume - memory controller programming 370 * 371 * @adev: amdgpu_device pointer 372 * @inst: instance number 373 * 374 * Let the VCN memory controller know it's offsets 375 */ 376 static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst) 377 { 378 uint32_t offset, size; 379 const struct common_firmware_header *hdr; 380 381 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 382 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 383 384 /* cache window 0: fw */ 385 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 386 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 387 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 388 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 389 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 390 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0); 391 offset = 0; 392 } else { 393 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 394 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 395 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 396 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 397 offset = size; 398 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 399 } 400 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size); 401 402 /* cache window 1: stack */ 403 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 404 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 405 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 406 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 407 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); 408 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 409 410 /* cache window 2: context */ 411 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 412 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 413 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 414 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 415 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0); 416 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 417 418 /* non-cache window */ 419 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 420 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 421 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 422 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 423 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); 424 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0, 425 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 426 } 427 428 /** 429 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode 430 * 431 * @adev: amdgpu_device pointer 432 * @inst_idx: instance number index 433 * @indirect: indirectly write sram 434 * 435 * Let the VCN memory controller know it's offsets with dpg mode 436 */ 437 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 438 { 439 uint32_t offset, size; 440 const struct common_firmware_header *hdr; 441 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 442 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 443 444 /* cache window 0: fw */ 445 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 446 if (!indirect) { 447 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 449 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 450 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 451 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 452 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 454 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 455 } else { 456 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 457 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 459 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 460 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 461 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 462 } 463 offset = 0; 464 } else { 465 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 466 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 467 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 468 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 469 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 470 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 471 offset = size; 472 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 473 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 474 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 475 } 476 477 if (!indirect) 478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 479 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 480 else 481 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 482 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 483 484 /* cache window 1: stack */ 485 if (!indirect) { 486 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 487 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 488 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 490 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 491 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 494 } else { 495 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 496 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 498 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 500 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 501 } 502 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 503 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 504 505 /* cache window 2: context */ 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 508 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 511 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 514 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 515 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 516 517 /* non-cache window */ 518 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 519 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 520 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 523 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), 528 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect); 529 530 /* VCN global tiling registers */ 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 533 } 534 535 /** 536 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating 537 * 538 * @adev: amdgpu_device pointer 539 * @inst: instance number 540 * 541 * Disable static power gating for VCN block 542 */ 543 static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 544 { 545 uint32_t data = 0; 546 547 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 548 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 549 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 550 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 551 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 552 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 553 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 554 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 555 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 556 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 557 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 558 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 559 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 560 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 561 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 562 563 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 564 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, 565 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 566 } else { 567 uint32_t value; 568 569 value = (inst) ? 0x2200800 : 0; 570 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 571 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 572 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 573 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 574 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 575 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 576 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 577 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 578 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 579 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 580 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 581 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 582 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 583 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 584 585 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); 587 } 588 589 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 590 data &= ~0x103; 591 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 592 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 593 UVD_POWER_STATUS__UVD_PG_EN_MASK; 594 595 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 596 597 return; 598 } 599 600 /** 601 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating 602 * 603 * @adev: amdgpu_device pointer 604 * @inst: instance number 605 * 606 * Enable static power gating for VCN block 607 */ 608 static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 609 { 610 uint32_t data; 611 612 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 613 /* Before power off, this indicator has to be turned on */ 614 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS); 615 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 616 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 617 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data); 618 619 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 620 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 624 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT 625 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 626 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 627 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 628 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 629 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 630 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT 631 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 632 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 633 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data); 634 635 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 636 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT 637 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 638 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT 639 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 640 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT 641 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 642 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 643 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 644 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 645 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 646 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT 647 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 648 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 649 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 650 } 651 652 return; 653 } 654 655 /** 656 * vcn_v4_0_disable_clock_gating - disable VCN clock gating 657 * 658 * @adev: amdgpu_device pointer 659 * @inst: instance number 660 * 661 * Disable clock gating for VCN block 662 */ 663 static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 664 { 665 uint32_t data; 666 667 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 668 return; 669 670 /* VCN disable CGC */ 671 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 672 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 673 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 674 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 675 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 676 677 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE); 678 data &= ~(UVD_CGC_GATE__SYS_MASK 679 | UVD_CGC_GATE__UDEC_MASK 680 | UVD_CGC_GATE__MPEG2_MASK 681 | UVD_CGC_GATE__REGS_MASK 682 | UVD_CGC_GATE__RBC_MASK 683 | UVD_CGC_GATE__LMI_MC_MASK 684 | UVD_CGC_GATE__LMI_UMC_MASK 685 | UVD_CGC_GATE__IDCT_MASK 686 | UVD_CGC_GATE__MPRD_MASK 687 | UVD_CGC_GATE__MPC_MASK 688 | UVD_CGC_GATE__LBSI_MASK 689 | UVD_CGC_GATE__LRBBM_MASK 690 | UVD_CGC_GATE__UDEC_RE_MASK 691 | UVD_CGC_GATE__UDEC_CM_MASK 692 | UVD_CGC_GATE__UDEC_IT_MASK 693 | UVD_CGC_GATE__UDEC_DB_MASK 694 | UVD_CGC_GATE__UDEC_MP_MASK 695 | UVD_CGC_GATE__WCB_MASK 696 | UVD_CGC_GATE__VCPU_MASK 697 | UVD_CGC_GATE__MMSCH_MASK); 698 699 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data); 700 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); 701 702 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 703 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 704 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 705 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 706 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 707 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 708 | UVD_CGC_CTRL__SYS_MODE_MASK 709 | UVD_CGC_CTRL__UDEC_MODE_MASK 710 | UVD_CGC_CTRL__MPEG2_MODE_MASK 711 | UVD_CGC_CTRL__REGS_MODE_MASK 712 | UVD_CGC_CTRL__RBC_MODE_MASK 713 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 714 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 715 | UVD_CGC_CTRL__IDCT_MODE_MASK 716 | UVD_CGC_CTRL__MPRD_MODE_MASK 717 | UVD_CGC_CTRL__MPC_MODE_MASK 718 | UVD_CGC_CTRL__LBSI_MODE_MASK 719 | UVD_CGC_CTRL__LRBBM_MODE_MASK 720 | UVD_CGC_CTRL__WCB_MODE_MASK 721 | UVD_CGC_CTRL__VCPU_MODE_MASK 722 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 723 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 724 725 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE); 726 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 727 | UVD_SUVD_CGC_GATE__SIT_MASK 728 | UVD_SUVD_CGC_GATE__SMP_MASK 729 | UVD_SUVD_CGC_GATE__SCM_MASK 730 | UVD_SUVD_CGC_GATE__SDB_MASK 731 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 732 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 733 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 734 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 735 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 736 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 737 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 738 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 739 | UVD_SUVD_CGC_GATE__SCLR_MASK 740 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 741 | UVD_SUVD_CGC_GATE__ENT_MASK 742 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 743 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 744 | UVD_SUVD_CGC_GATE__SITE_MASK 745 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 746 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 747 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 748 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 749 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 750 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data); 751 752 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 753 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 754 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 755 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 756 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 763 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 764 } 765 766 /** 767 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode 768 * 769 * @adev: amdgpu_device pointer 770 * @sram_sel: sram select 771 * @inst_idx: instance number index 772 * @indirect: indirectly write sram 773 * 774 * Disable clock gating for VCN block with dpg mode 775 */ 776 static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel, 777 int inst_idx, uint8_t indirect) 778 { 779 uint32_t reg_data = 0; 780 781 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 782 return; 783 784 /* enable sw clock gating control */ 785 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 786 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 787 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 788 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 789 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 790 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 791 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 792 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 793 UVD_CGC_CTRL__SYS_MODE_MASK | 794 UVD_CGC_CTRL__UDEC_MODE_MASK | 795 UVD_CGC_CTRL__MPEG2_MODE_MASK | 796 UVD_CGC_CTRL__REGS_MODE_MASK | 797 UVD_CGC_CTRL__RBC_MODE_MASK | 798 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 799 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 800 UVD_CGC_CTRL__IDCT_MODE_MASK | 801 UVD_CGC_CTRL__MPRD_MODE_MASK | 802 UVD_CGC_CTRL__MPC_MODE_MASK | 803 UVD_CGC_CTRL__LBSI_MODE_MASK | 804 UVD_CGC_CTRL__LRBBM_MODE_MASK | 805 UVD_CGC_CTRL__WCB_MODE_MASK | 806 UVD_CGC_CTRL__VCPU_MODE_MASK); 807 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 808 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); 809 810 /* turn off clock gating */ 811 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 812 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect); 813 814 /* turn on SUVD clock gating */ 815 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 816 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 817 818 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 819 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 820 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 821 } 822 823 /** 824 * vcn_v4_0_enable_clock_gating - enable VCN clock gating 825 * 826 * @adev: amdgpu_device pointer 827 * @inst: instance number 828 * 829 * Enable clock gating for VCN block 830 */ 831 static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 832 { 833 uint32_t data; 834 835 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 836 return; 837 838 /* enable VCN CGC */ 839 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 840 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 841 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 842 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 843 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 844 845 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL); 846 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 847 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 848 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 849 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 850 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 851 | UVD_CGC_CTRL__SYS_MODE_MASK 852 | UVD_CGC_CTRL__UDEC_MODE_MASK 853 | UVD_CGC_CTRL__MPEG2_MODE_MASK 854 | UVD_CGC_CTRL__REGS_MODE_MASK 855 | UVD_CGC_CTRL__RBC_MODE_MASK 856 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 857 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 858 | UVD_CGC_CTRL__IDCT_MODE_MASK 859 | UVD_CGC_CTRL__MPRD_MODE_MASK 860 | UVD_CGC_CTRL__MPC_MODE_MASK 861 | UVD_CGC_CTRL__LBSI_MODE_MASK 862 | UVD_CGC_CTRL__LRBBM_MODE_MASK 863 | UVD_CGC_CTRL__WCB_MODE_MASK 864 | UVD_CGC_CTRL__VCPU_MODE_MASK 865 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 866 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data); 867 868 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL); 869 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 870 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 871 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 872 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 873 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 874 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 875 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 876 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 877 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 878 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 879 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data); 880 881 return; 882 } 883 884 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, 885 bool indirect) 886 { 887 uint32_t tmp; 888 889 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 890 return; 891 892 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 893 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 894 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 895 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 896 WREG32_SOC15_DPG_MODE(inst_idx, 897 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), 898 tmp, 0, indirect); 899 900 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 901 WREG32_SOC15_DPG_MODE(inst_idx, 902 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN), 903 tmp, 0, indirect); 904 } 905 906 /** 907 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode 908 * 909 * @adev: amdgpu_device pointer 910 * @inst_idx: instance number index 911 * @indirect: indirectly write sram 912 * 913 * Start VCN block with dpg mode 914 */ 915 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 916 { 917 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 918 struct amdgpu_ring *ring; 919 uint32_t tmp; 920 921 /* disable register anti-hang mechanism */ 922 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, 923 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 924 /* enable dynamic power gating mode */ 925 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS); 926 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 927 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 928 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp); 929 930 if (indirect) 931 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 932 933 /* enable clock gating */ 934 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 935 936 /* enable VCPU clock */ 937 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 938 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 941 942 /* disable master interupt */ 943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 944 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); 945 946 /* setup regUVD_LMI_CTRL */ 947 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 948 UVD_LMI_CTRL__REQ_MODE_MASK | 949 UVD_LMI_CTRL__CRC_RESET_MASK | 950 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 951 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 952 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 953 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 954 0x00100000L); 955 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 956 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect); 957 958 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 959 VCN, inst_idx, regUVD_MPC_CNTL), 960 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 961 962 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 963 VCN, inst_idx, regUVD_MPC_SET_MUXA0), 964 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 965 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 966 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 967 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 968 969 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 970 VCN, inst_idx, regUVD_MPC_SET_MUXB0), 971 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 972 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 973 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 974 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 975 976 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 977 VCN, inst_idx, regUVD_MPC_SET_MUX), 978 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 979 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 980 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 981 982 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 983 984 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 985 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); 988 989 /* enable LMI MC and UMC channels */ 990 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; 991 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 992 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect); 993 994 vcn_v4_0_enable_ras(adev, inst_idx, indirect); 995 996 /* enable master interrupt */ 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, regUVD_MASTINT_EN), 999 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1000 1001 1002 if (indirect) 1003 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1004 1005 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1006 1007 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); 1008 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1009 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); 1010 1011 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1012 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1013 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1014 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1015 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0); 1016 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0); 1017 1018 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR); 1019 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp); 1020 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1021 1022 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); 1023 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1024 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); 1025 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1026 1027 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL, 1028 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1029 VCN_RB1_DB_CTRL__EN_MASK); 1030 1031 return 0; 1032 } 1033 1034 1035 /** 1036 * vcn_v4_0_start - VCN start 1037 * 1038 * @adev: amdgpu_device pointer 1039 * 1040 * Start VCN block 1041 */ 1042 static int vcn_v4_0_start(struct amdgpu_device *adev) 1043 { 1044 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1045 struct amdgpu_ring *ring; 1046 uint32_t tmp; 1047 int i, j, k, r; 1048 1049 if (adev->pm.dpm_enabled) 1050 amdgpu_dpm_enable_uvd(adev, true); 1051 1052 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1053 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1054 1055 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1056 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1057 continue; 1058 } 1059 1060 /* disable VCN power gating */ 1061 vcn_v4_0_disable_static_power_gating(adev, i); 1062 1063 /* set VCN status busy */ 1064 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1065 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); 1066 1067 /*SW clock gating */ 1068 vcn_v4_0_disable_clock_gating(adev, i); 1069 1070 /* enable VCPU clock */ 1071 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1072 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1073 1074 /* disable master interrupt */ 1075 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, 1076 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1077 1078 /* enable LMI MC and UMC channels */ 1079 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, 1080 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1081 1082 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1083 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1084 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1085 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1086 1087 /* setup regUVD_LMI_CTRL */ 1088 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL); 1089 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp | 1090 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1091 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1092 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1093 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1094 1095 /* setup regUVD_MPC_CNTL */ 1096 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL); 1097 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1098 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1099 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp); 1100 1101 /* setup UVD_MPC_SET_MUXA0 */ 1102 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0, 1103 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1104 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1105 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1106 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1107 1108 /* setup UVD_MPC_SET_MUXB0 */ 1109 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0, 1110 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1111 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1112 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1113 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1114 1115 /* setup UVD_MPC_SET_MUX */ 1116 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, 1117 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1118 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1119 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1120 1121 vcn_v4_0_mc_resume(adev, i); 1122 1123 /* VCN global tiling registers */ 1124 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG, 1125 adev->gfx.config.gb_addr_config); 1126 1127 /* unblock VCPU register access */ 1128 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, 1129 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1130 1131 /* release VCPU reset to boot */ 1132 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1133 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1134 1135 for (j = 0; j < 10; ++j) { 1136 uint32_t status; 1137 1138 for (k = 0; k < 100; ++k) { 1139 status = RREG32_SOC15(VCN, i, regUVD_STATUS); 1140 if (status & 2) 1141 break; 1142 mdelay(10); 1143 if (amdgpu_emu_mode == 1) 1144 msleep(1); 1145 } 1146 1147 if (amdgpu_emu_mode == 1) { 1148 r = -1; 1149 if (status & 2) { 1150 r = 0; 1151 break; 1152 } 1153 } else { 1154 r = 0; 1155 if (status & 2) 1156 break; 1157 1158 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); 1159 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1160 UVD_VCPU_CNTL__BLK_RST_MASK, 1161 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1162 mdelay(10); 1163 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1164 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1165 1166 mdelay(10); 1167 r = -1; 1168 } 1169 } 1170 1171 if (r) { 1172 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); 1173 return r; 1174 } 1175 1176 /* enable master interrupt */ 1177 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 1178 UVD_MASTINT_EN__VCPU_EN_MASK, 1179 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1180 1181 /* clear the busy bit of VCN_STATUS */ 1182 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, 1183 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1184 1185 ring = &adev->vcn.inst[i].ring_enc[0]; 1186 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, 1187 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | 1188 VCN_RB1_DB_CTRL__EN_MASK); 1189 1190 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); 1191 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1192 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); 1193 1194 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1195 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); 1196 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1197 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; 1198 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); 1199 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); 1200 1201 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR); 1202 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp); 1203 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR); 1204 1205 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); 1206 tmp |= VCN_RB_ENABLE__RB1_EN_MASK; 1207 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); 1208 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int vcn_v4_0_start_sriov(struct amdgpu_device *adev) 1215 { 1216 int i; 1217 struct amdgpu_ring *ring_enc; 1218 uint64_t cache_addr; 1219 uint64_t rb_enc_addr; 1220 uint64_t ctx_addr; 1221 uint32_t param, resp, expected; 1222 uint32_t offset, cache_size; 1223 uint32_t tmp, timeout; 1224 1225 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1226 uint32_t *table_loc; 1227 uint32_t table_size; 1228 uint32_t size, size_dw; 1229 uint32_t init_status; 1230 uint32_t enabled_vcn; 1231 1232 struct mmsch_v4_0_cmd_direct_write 1233 direct_wt = { {0} }; 1234 struct mmsch_v4_0_cmd_direct_read_modify_write 1235 direct_rd_mod_wt = { {0} }; 1236 struct mmsch_v4_0_cmd_end end = { {0} }; 1237 struct mmsch_v4_0_init_header header; 1238 1239 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1240 volatile struct amdgpu_fw_shared_rb_setup *rb_setup; 1241 1242 direct_wt.cmd_header.command_type = 1243 MMSCH_COMMAND__DIRECT_REG_WRITE; 1244 direct_rd_mod_wt.cmd_header.command_type = 1245 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1246 end.cmd_header.command_type = 1247 MMSCH_COMMAND__END; 1248 1249 header.version = MMSCH_VERSION; 1250 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2; 1251 for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) { 1252 header.inst[i].init_status = 0; 1253 header.inst[i].table_offset = 0; 1254 header.inst[i].table_size = 0; 1255 } 1256 1257 table_loc = (uint32_t *)table->cpu_addr; 1258 table_loc += header.total_size; 1259 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1260 if (adev->vcn.harvest_config & (1 << i)) 1261 continue; 1262 1263 table_size = 0; 1264 1265 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1266 regUVD_STATUS), 1267 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1268 1269 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1270 1271 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1272 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1273 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1274 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1275 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1276 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1277 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1278 offset = 0; 1279 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1280 regUVD_VCPU_CACHE_OFFSET0), 1281 0); 1282 } else { 1283 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1284 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1285 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1286 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1287 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1288 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1289 offset = cache_size; 1290 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1291 regUVD_VCPU_CACHE_OFFSET0), 1292 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1293 } 1294 1295 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1296 regUVD_VCPU_CACHE_SIZE0), 1297 cache_size); 1298 1299 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1300 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1301 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1302 lower_32_bits(cache_addr)); 1303 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1304 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1305 upper_32_bits(cache_addr)); 1306 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1307 regUVD_VCPU_CACHE_OFFSET1), 1308 0); 1309 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1310 regUVD_VCPU_CACHE_SIZE1), 1311 AMDGPU_VCN_STACK_SIZE); 1312 1313 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1314 AMDGPU_VCN_STACK_SIZE; 1315 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1316 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1317 lower_32_bits(cache_addr)); 1318 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1319 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1320 upper_32_bits(cache_addr)); 1321 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1322 regUVD_VCPU_CACHE_OFFSET2), 1323 0); 1324 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1325 regUVD_VCPU_CACHE_SIZE2), 1326 AMDGPU_VCN_CONTEXT_SIZE); 1327 1328 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1329 rb_setup = &fw_shared->rb_setup; 1330 1331 ring_enc = &adev->vcn.inst[i].ring_enc[0]; 1332 ring_enc->wptr = 0; 1333 rb_enc_addr = ring_enc->gpu_addr; 1334 1335 rb_setup->is_rb_enabled_flags |= RB_ENABLED; 1336 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); 1337 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); 1338 rb_setup->rb_size = ring_enc->ring_size / 4; 1339 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG); 1340 1341 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1342 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 1343 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1344 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1345 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 1346 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 1347 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1348 regUVD_VCPU_NONCACHE_SIZE0), 1349 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared))); 1350 1351 /* add end packet */ 1352 MMSCH_V4_0_INSERT_END(); 1353 1354 /* refine header */ 1355 header.inst[i].init_status = 0; 1356 header.inst[i].table_offset = header.total_size; 1357 header.inst[i].table_size = table_size; 1358 header.total_size += table_size; 1359 } 1360 1361 /* Update init table header in memory */ 1362 size = sizeof(struct mmsch_v4_0_init_header); 1363 table_loc = (uint32_t *)table->cpu_addr; 1364 memcpy((void *)table_loc, &header, size); 1365 1366 /* message MMSCH (in VCN[0]) to initialize this client 1367 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1368 * of memory descriptor location 1369 */ 1370 ctx_addr = table->gpu_addr; 1371 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1372 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1373 1374 /* 2, update vmid of descriptor */ 1375 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); 1376 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1377 /* use domain0 for MM scheduler */ 1378 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1379 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); 1380 1381 /* 3, notify mmsch about the size of this descriptor */ 1382 size = header.total_size; 1383 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); 1384 1385 /* 4, set resp to zero */ 1386 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); 1387 1388 /* 5, kick off the initialization and wait until 1389 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1390 */ 1391 param = 0x00000001; 1392 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); 1393 tmp = 0; 1394 timeout = 1000; 1395 resp = 0; 1396 expected = MMSCH_VF_MAILBOX_RESP__OK; 1397 while (resp != expected) { 1398 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); 1399 if (resp != 0) 1400 break; 1401 1402 udelay(10); 1403 tmp = tmp + 10; 1404 if (tmp >= timeout) { 1405 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1406 " waiting for regMMSCH_VF_MAILBOX_RESP "\ 1407 "(expected=0x%08x, readback=0x%08x)\n", 1408 tmp, expected, resp); 1409 return -EBUSY; 1410 } 1411 } 1412 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0; 1413 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status; 1414 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE 1415 && init_status != MMSCH_VF_ENGINE_STATUS__PASS) 1416 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\ 1417 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status); 1418 1419 return 0; 1420 } 1421 1422 /** 1423 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode 1424 * 1425 * @adev: amdgpu_device pointer 1426 * @inst_idx: instance number index 1427 * 1428 * Stop VCN block with dpg mode 1429 */ 1430 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1431 { 1432 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1433 uint32_t tmp; 1434 1435 vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state); 1436 /* Wait for power status to be 1 */ 1437 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1438 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1439 1440 /* wait for read ptr to be equal to write ptr */ 1441 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR); 1442 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1443 1444 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, 1445 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1446 1447 /* disable dynamic power gating mode */ 1448 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0, 1449 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1450 } 1451 1452 /** 1453 * vcn_v4_0_stop - VCN stop 1454 * 1455 * @adev: amdgpu_device pointer 1456 * 1457 * Stop VCN block 1458 */ 1459 static int vcn_v4_0_stop(struct amdgpu_device *adev) 1460 { 1461 volatile struct amdgpu_vcn4_fw_shared *fw_shared; 1462 uint32_t tmp; 1463 int i, r = 0; 1464 1465 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1466 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1467 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; 1468 1469 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1470 vcn_v4_0_stop_dpg_mode(adev, i); 1471 continue; 1472 } 1473 1474 /* wait for vcn idle */ 1475 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1476 if (r) 1477 return r; 1478 1479 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1480 UVD_LMI_STATUS__READ_CLEAN_MASK | 1481 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1482 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1483 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1484 if (r) 1485 return r; 1486 1487 /* disable LMI UMC channel */ 1488 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2); 1489 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1490 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp); 1491 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1492 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1493 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); 1494 if (r) 1495 return r; 1496 1497 /* block VCPU register access */ 1498 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 1499 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1500 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1501 1502 /* reset VCPU */ 1503 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 1504 UVD_VCPU_CNTL__BLK_RST_MASK, 1505 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1506 1507 /* disable VCPU clock */ 1508 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, 1509 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1510 1511 /* apply soft reset */ 1512 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1513 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1514 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1515 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET); 1516 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1517 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp); 1518 1519 /* clear status */ 1520 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); 1521 1522 /* apply HW clock gating */ 1523 vcn_v4_0_enable_clock_gating(adev, i); 1524 1525 /* enable VCN power gating */ 1526 vcn_v4_0_enable_static_power_gating(adev, i); 1527 } 1528 1529 if (adev->pm.dpm_enabled) 1530 amdgpu_dpm_enable_uvd(adev, false); 1531 1532 return 0; 1533 } 1534 1535 /** 1536 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode 1537 * 1538 * @adev: amdgpu_device pointer 1539 * @inst_idx: instance number index 1540 * @new_state: pause state 1541 * 1542 * Pause dpg mode for VCN block 1543 */ 1544 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, 1545 struct dpg_pause_state *new_state) 1546 { 1547 uint32_t reg_data = 0; 1548 int ret_code; 1549 1550 /* pause/unpause if state is changed */ 1551 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1552 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", 1553 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1554 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & 1555 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1556 1557 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1558 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, 1559 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1560 1561 if (!ret_code) { 1562 /* pause DPG */ 1563 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1564 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1565 1566 /* wait for ACK */ 1567 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, 1568 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1569 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1570 1571 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1572 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1573 } 1574 } else { 1575 /* unpause dpg, no need to wait */ 1576 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1577 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); 1578 } 1579 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1580 } 1581 1582 return 0; 1583 } 1584 1585 /** 1586 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer 1587 * 1588 * @ring: amdgpu_ring pointer 1589 * 1590 * Returns the current hardware unified read pointer 1591 */ 1592 static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring) 1593 { 1594 struct amdgpu_device *adev = ring->adev; 1595 1596 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1597 DRM_ERROR("wrong ring id is identified in %s", __func__); 1598 1599 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR); 1600 } 1601 1602 /** 1603 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer 1604 * 1605 * @ring: amdgpu_ring pointer 1606 * 1607 * Returns the current hardware unified write pointer 1608 */ 1609 static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring) 1610 { 1611 struct amdgpu_device *adev = ring->adev; 1612 1613 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1614 DRM_ERROR("wrong ring id is identified in %s", __func__); 1615 1616 if (ring->use_doorbell) 1617 return *ring->wptr_cpu_addr; 1618 else 1619 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR); 1620 } 1621 1622 /** 1623 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer 1624 * 1625 * @ring: amdgpu_ring pointer 1626 * 1627 * Commits the enc write pointer to the hardware 1628 */ 1629 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring) 1630 { 1631 struct amdgpu_device *adev = ring->adev; 1632 1633 if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) 1634 DRM_ERROR("wrong ring id is identified in %s", __func__); 1635 1636 if (ring->use_doorbell) { 1637 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1638 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1639 } else { 1640 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1641 } 1642 } 1643 1644 static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p, 1645 struct amdgpu_job *job) 1646 { 1647 struct drm_gpu_scheduler **scheds; 1648 1649 /* The create msg must be in the first IB submitted */ 1650 if (atomic_read(&job->base.entity->fence_seq)) 1651 return -EINVAL; 1652 1653 /* if VCN0 is harvested, we can't support AV1 */ 1654 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1655 return -EINVAL; 1656 1657 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] 1658 [AMDGPU_RING_PRIO_0].sched; 1659 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1660 return 0; 1661 } 1662 1663 static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1664 uint64_t addr) 1665 { 1666 struct ttm_operation_ctx ctx = { false, false }; 1667 struct amdgpu_bo_va_mapping *map; 1668 uint32_t *msg, num_buffers; 1669 struct amdgpu_bo *bo; 1670 uint64_t start, end; 1671 unsigned int i; 1672 void *ptr; 1673 int r; 1674 1675 addr &= AMDGPU_GMC_HOLE_MASK; 1676 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1677 if (r) { 1678 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); 1679 return r; 1680 } 1681 1682 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1683 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1684 if (addr & 0x7) { 1685 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1686 return -EINVAL; 1687 } 1688 1689 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1690 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1691 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1692 if (r) { 1693 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1694 return r; 1695 } 1696 1697 r = amdgpu_bo_kmap(bo, &ptr); 1698 if (r) { 1699 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1700 return r; 1701 } 1702 1703 msg = ptr + addr - start; 1704 1705 /* Check length */ 1706 if (msg[1] > end - addr) { 1707 r = -EINVAL; 1708 goto out; 1709 } 1710 1711 if (msg[3] != RDECODE_MSG_CREATE) 1712 goto out; 1713 1714 num_buffers = msg[2]; 1715 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1716 uint32_t offset, size, *create; 1717 1718 if (msg[0] != RDECODE_MESSAGE_CREATE) 1719 continue; 1720 1721 offset = msg[1]; 1722 size = msg[2]; 1723 1724 if (offset + size > end) { 1725 r = -EINVAL; 1726 goto out; 1727 } 1728 1729 create = ptr + addr + offset - start; 1730 1731 /* H264, HEVC and VP9 can run on any instance */ 1732 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1733 continue; 1734 1735 r = vcn_v4_0_limit_sched(p, job); 1736 if (r) 1737 goto out; 1738 } 1739 1740 out: 1741 amdgpu_bo_kunmap(bo); 1742 return r; 1743 } 1744 1745 #define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) 1746 #define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) 1747 1748 #define RADEON_VCN_ENGINE_INFO (0x30000001) 1749 #define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 1750 1751 #define RENCODE_ENCODE_STANDARD_AV1 2 1752 #define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 1753 #define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 1754 1755 /* return the offset in ib if id is found, -1 otherwise 1756 * to speed up the searching we only search upto max_offset 1757 */ 1758 static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) 1759 { 1760 int i; 1761 1762 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { 1763 if (ib->ptr[i + 1] == id) 1764 return i; 1765 } 1766 return -1; 1767 } 1768 1769 static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1770 struct amdgpu_job *job, 1771 struct amdgpu_ib *ib) 1772 { 1773 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1774 struct amdgpu_vcn_decode_buffer *decode_buffer; 1775 uint64_t addr; 1776 uint32_t val; 1777 int idx; 1778 1779 /* The first instance can decode anything */ 1780 if (!ring->me) 1781 return 0; 1782 1783 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ 1784 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, 1785 RADEON_VCN_ENGINE_INFO_MAX_OFFSET); 1786 if (idx < 0) /* engine info is missing */ 1787 return 0; 1788 1789 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ 1790 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { 1791 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; 1792 1793 if (!(decode_buffer->valid_buf_flag & 0x1)) 1794 return 0; 1795 1796 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | 1797 decode_buffer->msg_buffer_address_lo; 1798 return vcn_v4_0_dec_msg(p, job, addr); 1799 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { 1800 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, 1801 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); 1802 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) 1803 return vcn_v4_0_limit_sched(p, job); 1804 } 1805 return 0; 1806 } 1807 1808 static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { 1809 .type = AMDGPU_RING_TYPE_VCN_ENC, 1810 .align_mask = 0x3f, 1811 .nop = VCN_ENC_CMD_NO_OP, 1812 .get_rptr = vcn_v4_0_unified_ring_get_rptr, 1813 .get_wptr = vcn_v4_0_unified_ring_get_wptr, 1814 .set_wptr = vcn_v4_0_unified_ring_set_wptr, 1815 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place, 1816 .emit_frame_size = 1817 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1818 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1819 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1820 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1821 1, /* vcn_v2_0_enc_ring_insert_end */ 1822 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1823 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1824 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1825 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1826 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1827 .test_ib = amdgpu_vcn_unified_ring_test_ib, 1828 .insert_nop = amdgpu_ring_insert_nop, 1829 .insert_end = vcn_v2_0_enc_ring_insert_end, 1830 .pad_ib = amdgpu_ring_generic_pad_ib, 1831 .begin_use = amdgpu_vcn_ring_begin_use, 1832 .end_use = amdgpu_vcn_ring_end_use, 1833 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1834 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1835 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1836 }; 1837 1838 /** 1839 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions 1840 * 1841 * @adev: amdgpu_device pointer 1842 * 1843 * Set unified ring functions 1844 */ 1845 static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev) 1846 { 1847 int i; 1848 1849 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1850 if (adev->vcn.harvest_config & (1 << i)) 1851 continue; 1852 1853 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 2)) 1854 vcn_v4_0_unified_ring_vm_funcs.secure_submission_supported = true; 1855 1856 adev->vcn.inst[i].ring_enc[0].funcs = 1857 (const struct amdgpu_ring_funcs *)&vcn_v4_0_unified_ring_vm_funcs; 1858 adev->vcn.inst[i].ring_enc[0].me = i; 1859 1860 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i); 1861 } 1862 } 1863 1864 /** 1865 * vcn_v4_0_is_idle - check VCN block is idle 1866 * 1867 * @handle: amdgpu_device pointer 1868 * 1869 * Check whether VCN block is idle 1870 */ 1871 static bool vcn_v4_0_is_idle(void *handle) 1872 { 1873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1874 int i, ret = 1; 1875 1876 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1877 if (adev->vcn.harvest_config & (1 << i)) 1878 continue; 1879 1880 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); 1881 } 1882 1883 return ret; 1884 } 1885 1886 /** 1887 * vcn_v4_0_wait_for_idle - wait for VCN block idle 1888 * 1889 * @handle: amdgpu_device pointer 1890 * 1891 * Wait for VCN block idle 1892 */ 1893 static int vcn_v4_0_wait_for_idle(void *handle) 1894 { 1895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1896 int i, ret = 0; 1897 1898 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1899 if (adev->vcn.harvest_config & (1 << i)) 1900 continue; 1901 1902 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 1903 UVD_STATUS__IDLE); 1904 if (ret) 1905 return ret; 1906 } 1907 1908 return ret; 1909 } 1910 1911 /** 1912 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state 1913 * 1914 * @handle: amdgpu_device pointer 1915 * @state: clock gating state 1916 * 1917 * Set VCN block clockgating state 1918 */ 1919 static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) 1920 { 1921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1922 bool enable = state == AMD_CG_STATE_GATE; 1923 int i; 1924 1925 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1926 if (adev->vcn.harvest_config & (1 << i)) 1927 continue; 1928 1929 if (enable) { 1930 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) 1931 return -EBUSY; 1932 vcn_v4_0_enable_clock_gating(adev, i); 1933 } else { 1934 vcn_v4_0_disable_clock_gating(adev, i); 1935 } 1936 } 1937 1938 return 0; 1939 } 1940 1941 /** 1942 * vcn_v4_0_set_powergating_state - set VCN block powergating state 1943 * 1944 * @handle: amdgpu_device pointer 1945 * @state: power gating state 1946 * 1947 * Set VCN block powergating state 1948 */ 1949 static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state) 1950 { 1951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1952 int ret; 1953 1954 /* for SRIOV, guest should not control VCN Power-gating 1955 * MMSCH FW should control Power-gating and clock-gating 1956 * guest should avoid touching CGC and PG 1957 */ 1958 if (amdgpu_sriov_vf(adev)) { 1959 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1960 return 0; 1961 } 1962 1963 if (state == adev->vcn.cur_state) 1964 return 0; 1965 1966 if (state == AMD_PG_STATE_GATE) 1967 ret = vcn_v4_0_stop(adev); 1968 else 1969 ret = vcn_v4_0_start(adev); 1970 1971 if (!ret) 1972 adev->vcn.cur_state = state; 1973 1974 return ret; 1975 } 1976 1977 /** 1978 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 1979 * 1980 * @adev: amdgpu_device pointer 1981 * @source: interrupt sources 1982 * @type: interrupt types 1983 * @state: interrupt states 1984 * 1985 * Set VCN block interrupt state 1986 */ 1987 static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1988 unsigned type, enum amdgpu_interrupt_state state) 1989 { 1990 return 0; 1991 } 1992 1993 /** 1994 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state 1995 * 1996 * @adev: amdgpu_device pointer 1997 * @source: interrupt sources 1998 * @type: interrupt types 1999 * @state: interrupt states 2000 * 2001 * Set VCN block RAS interrupt state 2002 */ 2003 static int vcn_v4_0_set_ras_interrupt_state(struct amdgpu_device *adev, 2004 struct amdgpu_irq_src *source, 2005 unsigned int type, 2006 enum amdgpu_interrupt_state state) 2007 { 2008 return 0; 2009 } 2010 2011 /** 2012 * vcn_v4_0_process_interrupt - process VCN block interrupt 2013 * 2014 * @adev: amdgpu_device pointer 2015 * @source: interrupt sources 2016 * @entry: interrupt entry from clients and sources 2017 * 2018 * Process VCN block interrupt 2019 */ 2020 static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2021 struct amdgpu_iv_entry *entry) 2022 { 2023 uint32_t ip_instance; 2024 2025 switch (entry->client_id) { 2026 case SOC15_IH_CLIENTID_VCN: 2027 ip_instance = 0; 2028 break; 2029 case SOC15_IH_CLIENTID_VCN1: 2030 ip_instance = 1; 2031 break; 2032 default: 2033 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2034 return 0; 2035 } 2036 2037 DRM_DEBUG("IH: VCN TRAP\n"); 2038 2039 switch (entry->src_id) { 2040 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2041 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2042 break; 2043 default: 2044 DRM_ERROR("Unhandled interrupt: %d %d\n", 2045 entry->src_id, entry->src_data[0]); 2046 break; 2047 } 2048 2049 return 0; 2050 } 2051 2052 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2053 .set = vcn_v4_0_set_interrupt_state, 2054 .process = vcn_v4_0_process_interrupt, 2055 }; 2056 2057 static const struct amdgpu_irq_src_funcs vcn_v4_0_ras_irq_funcs = { 2058 .set = vcn_v4_0_set_ras_interrupt_state, 2059 .process = amdgpu_vcn_process_poison_irq, 2060 }; 2061 2062 /** 2063 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions 2064 * 2065 * @adev: amdgpu_device pointer 2066 * 2067 * Set VCN block interrupt irq functions 2068 */ 2069 static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) 2070 { 2071 int i; 2072 2073 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2074 if (adev->vcn.harvest_config & (1 << i)) 2075 continue; 2076 2077 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2078 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs; 2079 2080 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; 2081 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v4_0_ras_irq_funcs; 2082 } 2083 } 2084 2085 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { 2086 .name = "vcn_v4_0", 2087 .early_init = vcn_v4_0_early_init, 2088 .late_init = NULL, 2089 .sw_init = vcn_v4_0_sw_init, 2090 .sw_fini = vcn_v4_0_sw_fini, 2091 .hw_init = vcn_v4_0_hw_init, 2092 .hw_fini = vcn_v4_0_hw_fini, 2093 .suspend = vcn_v4_0_suspend, 2094 .resume = vcn_v4_0_resume, 2095 .is_idle = vcn_v4_0_is_idle, 2096 .wait_for_idle = vcn_v4_0_wait_for_idle, 2097 .check_soft_reset = NULL, 2098 .pre_soft_reset = NULL, 2099 .soft_reset = NULL, 2100 .post_soft_reset = NULL, 2101 .set_clockgating_state = vcn_v4_0_set_clockgating_state, 2102 .set_powergating_state = vcn_v4_0_set_powergating_state, 2103 }; 2104 2105 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { 2106 .type = AMD_IP_BLOCK_TYPE_VCN, 2107 .major = 4, 2108 .minor = 0, 2109 .rev = 0, 2110 .funcs = &vcn_v4_0_ip_funcs, 2111 }; 2112 2113 static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev, 2114 uint32_t instance, uint32_t sub_block) 2115 { 2116 uint32_t poison_stat = 0, reg_value = 0; 2117 2118 switch (sub_block) { 2119 case AMDGPU_VCN_V4_0_VCPU_VCODEC: 2120 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS); 2121 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2122 break; 2123 default: 2124 break; 2125 } 2126 2127 if (poison_stat) 2128 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2129 instance, sub_block); 2130 2131 return poison_stat; 2132 } 2133 2134 static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev) 2135 { 2136 uint32_t inst, sub; 2137 uint32_t poison_stat = 0; 2138 2139 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2140 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++) 2141 poison_stat += 2142 vcn_v4_0_query_poison_by_instance(adev, inst, sub); 2143 2144 return !!poison_stat; 2145 } 2146 2147 const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = { 2148 .query_poison_status = vcn_v4_0_query_ras_poison_status, 2149 }; 2150 2151 static struct amdgpu_vcn_ras vcn_v4_0_ras = { 2152 .ras_block = { 2153 .hw_ops = &vcn_v4_0_ras_hw_ops, 2154 .ras_late_init = amdgpu_vcn_ras_late_init, 2155 }, 2156 }; 2157 2158 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev) 2159 { 2160 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2161 case IP_VERSION(4, 0, 0): 2162 adev->vcn.ras = &vcn_v4_0_ras; 2163 break; 2164 default: 2165 break; 2166 } 2167 } 2168