1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v3_0.h" 33 #include "vcn_sw_ring.h" 34 35 #include "vcn/vcn_3_0_0_offset.h" 36 #include "vcn/vcn_3_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 56 57 #define VCN_INSTANCES_SIENNA_CICHLID 2 58 #define DEC_SW_RING_ENABLED FALSE 59 60 #define RDECODE_MSG_CREATE 0x00000000 61 #define RDECODE_MESSAGE_CREATE 0x00000001 62 63 static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_RPTR), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_WPTR), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_RBC_IB_VMID), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC_VMIDS_MULTI), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET), 97 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET2), 98 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_GATE), 99 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_STATUS), 100 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_CTRL), 101 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_GATE), 102 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_STATUS), 103 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_CTRL), 104 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 105 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 106 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 107 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 108 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 109 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_STATUS2), 110 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_GATE2), 111 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 112 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW), 113 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH), 114 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW), 115 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH), 116 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW), 117 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH), 118 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_REF_64BIT_BAR_LOW), 119 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_REF_64BIT_BAR_HIGH), 120 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_DBW_64BIT_BAR_LOW), 121 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_DBW_64BIT_BAR_HIGH), 122 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW), 123 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH), 124 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP0_64BIT_BAR_LOW), 125 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH), 126 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP1_64BIT_BAR_LOW), 127 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH), 128 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP2_64BIT_BAR_LOW), 129 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH), 130 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP3_64BIT_BAR_LOW), 131 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH), 132 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD0_64BIT_BAR_LOW), 133 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH), 134 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD1_64BIT_BAR_LOW), 135 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH), 136 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD2_64BIT_BAR_LOW), 137 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH), 138 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD3_64BIT_BAR_LOW), 139 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH), 140 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD4_64BIT_BAR_LOW), 141 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH), 142 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 143 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 144 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW), 145 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH), 146 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW), 147 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH), 148 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW), 149 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH), 150 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW), 151 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH), 152 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW), 153 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH), 154 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_SCLR_64BIT_BAR_LOW), 155 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH), 156 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW), 157 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH), 158 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW), 159 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH), 160 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW), 161 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH), 162 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW), 163 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH), 164 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW), 165 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH), 166 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_STATUS), 167 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_LOW), 168 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_MIF_REF_LUMA_64BIT_BAR_HIGH), 169 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SCRATCH1) 170 }; 171 172 static int amdgpu_ih_clientid_vcns[] = { 173 SOC15_IH_CLIENTID_VCN, 174 SOC15_IH_CLIENTID_VCN1 175 }; 176 177 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 178 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 179 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 180 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 181 static int vcn_v3_0_set_powergating_state(void *handle, 182 enum amd_powergating_state state); 183 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 184 int inst_idx, struct dpg_pause_state *new_state); 185 186 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 187 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 188 189 /** 190 * vcn_v3_0_early_init - set function pointers and load microcode 191 * 192 * @handle: amdgpu_device pointer 193 * 194 * Set ring and irq function pointers 195 * Load microcode from filesystem 196 */ 197 static int vcn_v3_0_early_init(void *handle) 198 { 199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 200 201 if (amdgpu_sriov_vf(adev)) { 202 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 203 adev->vcn.harvest_config = 0; 204 adev->vcn.num_enc_rings = 1; 205 206 } else { 207 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 208 AMDGPU_VCN_HARVEST_VCN1)) 209 /* both instances are harvested, disable the block */ 210 return -ENOENT; 211 212 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 213 IP_VERSION(3, 0, 33)) 214 adev->vcn.num_enc_rings = 0; 215 else 216 adev->vcn.num_enc_rings = 2; 217 } 218 219 vcn_v3_0_set_dec_ring_funcs(adev); 220 vcn_v3_0_set_enc_ring_funcs(adev); 221 vcn_v3_0_set_irq_funcs(adev); 222 223 return amdgpu_vcn_early_init(adev); 224 } 225 226 /** 227 * vcn_v3_0_sw_init - sw init for VCN block 228 * 229 * @handle: amdgpu_device pointer 230 * 231 * Load firmware and sw initialization 232 */ 233 static int vcn_v3_0_sw_init(void *handle) 234 { 235 struct amdgpu_ring *ring; 236 int i, j, r; 237 int vcn_doorbell_index = 0; 238 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 239 uint32_t *ptr; 240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 241 242 r = amdgpu_vcn_sw_init(adev); 243 if (r) 244 return r; 245 246 amdgpu_vcn_setup_ucode(adev); 247 248 r = amdgpu_vcn_resume(adev); 249 if (r) 250 return r; 251 252 /* 253 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 254 * Formula: 255 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 256 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 257 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 258 */ 259 if (amdgpu_sriov_vf(adev)) { 260 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 261 /* get DWORD offset */ 262 vcn_doorbell_index = vcn_doorbell_index << 1; 263 } 264 265 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 266 volatile struct amdgpu_fw_shared *fw_shared; 267 268 if (adev->vcn.harvest_config & (1 << i)) 269 continue; 270 271 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 272 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 273 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 274 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 275 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 276 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 277 278 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 279 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 280 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 281 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 282 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 283 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 284 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 285 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 286 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 287 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 288 289 /* VCN DEC TRAP */ 290 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 291 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 292 if (r) 293 return r; 294 295 atomic_set(&adev->vcn.inst[i].sched_score, 0); 296 297 ring = &adev->vcn.inst[i].ring_dec; 298 ring->use_doorbell = true; 299 if (amdgpu_sriov_vf(adev)) { 300 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 301 } else { 302 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 303 } 304 ring->vm_hub = AMDGPU_MMHUB0(0); 305 sprintf(ring->name, "vcn_dec_%d", i); 306 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 307 AMDGPU_RING_PRIO_DEFAULT, 308 &adev->vcn.inst[i].sched_score); 309 if (r) 310 return r; 311 312 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 313 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 314 315 /* VCN ENC TRAP */ 316 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 317 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 318 if (r) 319 return r; 320 321 ring = &adev->vcn.inst[i].ring_enc[j]; 322 ring->use_doorbell = true; 323 if (amdgpu_sriov_vf(adev)) { 324 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 325 } else { 326 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 327 } 328 ring->vm_hub = AMDGPU_MMHUB0(0); 329 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 330 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 331 hw_prio, &adev->vcn.inst[i].sched_score); 332 if (r) 333 return r; 334 } 335 336 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 337 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 338 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 339 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 340 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 341 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 342 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) 343 fw_shared->smu_interface_info.smu_interface_type = 2; 344 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 345 IP_VERSION(3, 1, 1)) 346 fw_shared->smu_interface_info.smu_interface_type = 1; 347 348 if (amdgpu_vcnfw_log) 349 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 350 } 351 352 if (amdgpu_sriov_vf(adev)) { 353 r = amdgpu_virt_alloc_mm_table(adev); 354 if (r) 355 return r; 356 } 357 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 358 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 359 360 /* Allocate memory for VCN IP Dump buffer */ 361 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 362 if (ptr == NULL) { 363 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 364 adev->vcn.ip_dump = NULL; 365 } else { 366 adev->vcn.ip_dump = ptr; 367 } 368 369 return 0; 370 } 371 372 /** 373 * vcn_v3_0_sw_fini - sw fini for VCN block 374 * 375 * @handle: amdgpu_device pointer 376 * 377 * VCN suspend and free up sw allocation 378 */ 379 static int vcn_v3_0_sw_fini(void *handle) 380 { 381 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 382 int i, r, idx; 383 384 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 385 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 386 volatile struct amdgpu_fw_shared *fw_shared; 387 388 if (adev->vcn.harvest_config & (1 << i)) 389 continue; 390 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 391 fw_shared->present_flag_0 = 0; 392 fw_shared->sw_ring.is_enabled = false; 393 } 394 395 drm_dev_exit(idx); 396 } 397 398 if (amdgpu_sriov_vf(adev)) 399 amdgpu_virt_free_mm_table(adev); 400 401 r = amdgpu_vcn_suspend(adev); 402 if (r) 403 return r; 404 405 r = amdgpu_vcn_sw_fini(adev); 406 407 kfree(adev->vcn.ip_dump); 408 return r; 409 } 410 411 /** 412 * vcn_v3_0_hw_init - start and test VCN block 413 * 414 * @handle: amdgpu_device pointer 415 * 416 * Initialize the hardware, boot up the VCPU and do some testing 417 */ 418 static int vcn_v3_0_hw_init(void *handle) 419 { 420 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 421 struct amdgpu_ring *ring; 422 int i, j, r; 423 424 if (amdgpu_sriov_vf(adev)) { 425 r = vcn_v3_0_start_sriov(adev); 426 if (r) 427 return r; 428 429 /* initialize VCN dec and enc ring buffers */ 430 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 431 if (adev->vcn.harvest_config & (1 << i)) 432 continue; 433 434 ring = &adev->vcn.inst[i].ring_dec; 435 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 436 ring->sched.ready = false; 437 ring->no_scheduler = true; 438 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 439 } else { 440 ring->wptr = 0; 441 ring->wptr_old = 0; 442 vcn_v3_0_dec_ring_set_wptr(ring); 443 ring->sched.ready = true; 444 } 445 446 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 447 ring = &adev->vcn.inst[i].ring_enc[j]; 448 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 449 ring->sched.ready = false; 450 ring->no_scheduler = true; 451 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 452 } else { 453 ring->wptr = 0; 454 ring->wptr_old = 0; 455 vcn_v3_0_enc_ring_set_wptr(ring); 456 ring->sched.ready = true; 457 } 458 } 459 } 460 } else { 461 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 462 if (adev->vcn.harvest_config & (1 << i)) 463 continue; 464 465 ring = &adev->vcn.inst[i].ring_dec; 466 467 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 468 ring->doorbell_index, i); 469 470 r = amdgpu_ring_test_helper(ring); 471 if (r) 472 return r; 473 474 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 475 ring = &adev->vcn.inst[i].ring_enc[j]; 476 r = amdgpu_ring_test_helper(ring); 477 if (r) 478 return r; 479 } 480 } 481 } 482 483 return 0; 484 } 485 486 /** 487 * vcn_v3_0_hw_fini - stop the hardware block 488 * 489 * @handle: amdgpu_device pointer 490 * 491 * Stop the VCN block, mark ring as not ready any more 492 */ 493 static int vcn_v3_0_hw_fini(void *handle) 494 { 495 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 496 int i; 497 498 cancel_delayed_work_sync(&adev->vcn.idle_work); 499 500 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 501 if (adev->vcn.harvest_config & (1 << i)) 502 continue; 503 504 if (!amdgpu_sriov_vf(adev)) { 505 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 506 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 507 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 508 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 509 } 510 } 511 } 512 513 return 0; 514 } 515 516 /** 517 * vcn_v3_0_suspend - suspend VCN block 518 * 519 * @handle: amdgpu_device pointer 520 * 521 * HW fini and suspend VCN block 522 */ 523 static int vcn_v3_0_suspend(void *handle) 524 { 525 int r; 526 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 527 528 r = vcn_v3_0_hw_fini(adev); 529 if (r) 530 return r; 531 532 r = amdgpu_vcn_suspend(adev); 533 534 return r; 535 } 536 537 /** 538 * vcn_v3_0_resume - resume VCN block 539 * 540 * @handle: amdgpu_device pointer 541 * 542 * Resume firmware and hw init VCN block 543 */ 544 static int vcn_v3_0_resume(void *handle) 545 { 546 int r; 547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 548 549 r = amdgpu_vcn_resume(adev); 550 if (r) 551 return r; 552 553 r = vcn_v3_0_hw_init(adev); 554 555 return r; 556 } 557 558 /** 559 * vcn_v3_0_mc_resume - memory controller programming 560 * 561 * @adev: amdgpu_device pointer 562 * @inst: instance number 563 * 564 * Let the VCN memory controller know it's offsets 565 */ 566 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 567 { 568 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst]->size + 4); 569 uint32_t offset; 570 571 /* cache window 0: fw */ 572 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 573 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 574 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 575 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 576 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 577 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 578 offset = 0; 579 } else { 580 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 581 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 582 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 583 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 584 offset = size; 585 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 586 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 587 } 588 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 589 590 /* cache window 1: stack */ 591 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 592 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 593 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 594 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 595 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 596 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 597 598 /* cache window 2: context */ 599 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 600 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 601 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 602 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 603 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 604 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 605 606 /* non-cache window */ 607 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 608 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 609 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 610 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 611 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 612 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 613 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 614 } 615 616 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 617 { 618 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[inst_idx]->size + 4); 619 uint32_t offset; 620 621 /* cache window 0: fw */ 622 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 623 if (!indirect) { 624 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 625 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 626 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 627 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 628 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 629 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 630 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 631 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 632 } else { 633 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 634 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 635 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 636 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 637 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 638 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 639 } 640 offset = 0; 641 } else { 642 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 643 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 644 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 645 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 646 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 647 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 648 offset = size; 649 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 650 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 651 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 652 } 653 654 if (!indirect) 655 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 656 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 657 else 658 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 659 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 660 661 /* cache window 1: stack */ 662 if (!indirect) { 663 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 664 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 665 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 666 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 667 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 668 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 669 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 670 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 671 } else { 672 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 673 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 674 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 675 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 676 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 677 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 678 } 679 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 680 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 681 682 /* cache window 2: context */ 683 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 684 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 685 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 686 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 687 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 688 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 689 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 690 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 691 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 692 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 693 694 /* non-cache window */ 695 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 696 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 697 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 698 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 699 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 700 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 701 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 702 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 703 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 704 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 705 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 706 707 /* VCN global tiling registers */ 708 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 709 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 710 } 711 712 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 713 { 714 uint32_t data = 0; 715 716 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 717 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 718 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 719 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 720 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 721 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 722 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 724 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 725 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 726 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 727 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 728 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 729 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 730 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 731 732 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 733 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 734 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 735 } else { 736 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 737 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 738 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 739 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 740 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 741 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 742 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 743 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 744 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 745 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 746 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 747 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 748 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 749 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 750 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 751 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 752 } 753 754 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 755 data &= ~0x103; 756 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 757 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 758 UVD_POWER_STATUS__UVD_PG_EN_MASK; 759 760 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 761 } 762 763 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 764 { 765 uint32_t data; 766 767 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 768 /* Before power off, this indicator has to be turned on */ 769 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 770 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 771 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 772 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 773 774 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 775 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 776 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 777 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 778 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 779 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 780 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 781 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 782 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 783 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 784 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 785 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 786 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 787 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 788 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 789 790 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 791 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 792 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 793 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 794 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 795 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 796 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 797 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 798 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 799 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 800 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 801 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 802 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 803 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 804 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 805 } 806 } 807 808 /** 809 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 810 * 811 * @adev: amdgpu_device pointer 812 * @inst: instance number 813 * 814 * Disable clock gating for VCN block 815 */ 816 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 817 { 818 uint32_t data; 819 820 /* VCN disable CGC */ 821 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 822 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 823 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 824 else 825 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 826 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 827 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 828 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 829 830 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 831 data &= ~(UVD_CGC_GATE__SYS_MASK 832 | UVD_CGC_GATE__UDEC_MASK 833 | UVD_CGC_GATE__MPEG2_MASK 834 | UVD_CGC_GATE__REGS_MASK 835 | UVD_CGC_GATE__RBC_MASK 836 | UVD_CGC_GATE__LMI_MC_MASK 837 | UVD_CGC_GATE__LMI_UMC_MASK 838 | UVD_CGC_GATE__IDCT_MASK 839 | UVD_CGC_GATE__MPRD_MASK 840 | UVD_CGC_GATE__MPC_MASK 841 | UVD_CGC_GATE__LBSI_MASK 842 | UVD_CGC_GATE__LRBBM_MASK 843 | UVD_CGC_GATE__UDEC_RE_MASK 844 | UVD_CGC_GATE__UDEC_CM_MASK 845 | UVD_CGC_GATE__UDEC_IT_MASK 846 | UVD_CGC_GATE__UDEC_DB_MASK 847 | UVD_CGC_GATE__UDEC_MP_MASK 848 | UVD_CGC_GATE__WCB_MASK 849 | UVD_CGC_GATE__VCPU_MASK 850 | UVD_CGC_GATE__MMSCH_MASK); 851 852 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 853 854 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 855 856 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 857 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 858 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 859 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 860 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 861 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 862 | UVD_CGC_CTRL__SYS_MODE_MASK 863 | UVD_CGC_CTRL__UDEC_MODE_MASK 864 | UVD_CGC_CTRL__MPEG2_MODE_MASK 865 | UVD_CGC_CTRL__REGS_MODE_MASK 866 | UVD_CGC_CTRL__RBC_MODE_MASK 867 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 868 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 869 | UVD_CGC_CTRL__IDCT_MODE_MASK 870 | UVD_CGC_CTRL__MPRD_MODE_MASK 871 | UVD_CGC_CTRL__MPC_MODE_MASK 872 | UVD_CGC_CTRL__LBSI_MODE_MASK 873 | UVD_CGC_CTRL__LRBBM_MODE_MASK 874 | UVD_CGC_CTRL__WCB_MODE_MASK 875 | UVD_CGC_CTRL__VCPU_MODE_MASK 876 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 877 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 878 879 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 880 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 881 | UVD_SUVD_CGC_GATE__SIT_MASK 882 | UVD_SUVD_CGC_GATE__SMP_MASK 883 | UVD_SUVD_CGC_GATE__SCM_MASK 884 | UVD_SUVD_CGC_GATE__SDB_MASK 885 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 886 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 887 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 888 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 889 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 890 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 891 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 892 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 893 | UVD_SUVD_CGC_GATE__SCLR_MASK 894 | UVD_SUVD_CGC_GATE__ENT_MASK 895 | UVD_SUVD_CGC_GATE__IME_MASK 896 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 897 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 898 | UVD_SUVD_CGC_GATE__SITE_MASK 899 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 900 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 901 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 902 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 903 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 904 | UVD_SUVD_CGC_GATE__EFC_MASK 905 | UVD_SUVD_CGC_GATE__SAOE_MASK 906 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 907 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 908 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 909 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 910 | UVD_SUVD_CGC_GATE__SMPA_MASK); 911 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 912 913 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 914 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 915 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 916 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 917 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 918 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 919 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 920 921 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 922 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 938 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 939 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 940 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 941 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 942 } 943 944 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 945 uint8_t sram_sel, int inst_idx, uint8_t indirect) 946 { 947 uint32_t reg_data = 0; 948 949 /* enable sw clock gating control */ 950 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 951 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 952 else 953 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 954 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 955 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 956 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 957 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 958 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 959 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 960 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 961 UVD_CGC_CTRL__SYS_MODE_MASK | 962 UVD_CGC_CTRL__UDEC_MODE_MASK | 963 UVD_CGC_CTRL__MPEG2_MODE_MASK | 964 UVD_CGC_CTRL__REGS_MODE_MASK | 965 UVD_CGC_CTRL__RBC_MODE_MASK | 966 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 967 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 968 UVD_CGC_CTRL__IDCT_MODE_MASK | 969 UVD_CGC_CTRL__MPRD_MODE_MASK | 970 UVD_CGC_CTRL__MPC_MODE_MASK | 971 UVD_CGC_CTRL__LBSI_MODE_MASK | 972 UVD_CGC_CTRL__LRBBM_MODE_MASK | 973 UVD_CGC_CTRL__WCB_MODE_MASK | 974 UVD_CGC_CTRL__VCPU_MODE_MASK | 975 UVD_CGC_CTRL__MMSCH_MODE_MASK); 976 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 977 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 978 979 /* turn off clock gating */ 980 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 981 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 982 983 /* turn on SUVD clock gating */ 984 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 985 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 986 987 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 988 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 989 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 990 } 991 992 /** 993 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 994 * 995 * @adev: amdgpu_device pointer 996 * @inst: instance number 997 * 998 * Enable clock gating for VCN block 999 */ 1000 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 1001 { 1002 uint32_t data; 1003 1004 /* enable VCN CGC */ 1005 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 1006 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 1007 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 1008 else 1009 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 1010 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 1011 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 1012 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 1013 1014 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 1015 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 1016 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 1017 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 1018 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 1019 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 1020 | UVD_CGC_CTRL__SYS_MODE_MASK 1021 | UVD_CGC_CTRL__UDEC_MODE_MASK 1022 | UVD_CGC_CTRL__MPEG2_MODE_MASK 1023 | UVD_CGC_CTRL__REGS_MODE_MASK 1024 | UVD_CGC_CTRL__RBC_MODE_MASK 1025 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 1026 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 1027 | UVD_CGC_CTRL__IDCT_MODE_MASK 1028 | UVD_CGC_CTRL__MPRD_MODE_MASK 1029 | UVD_CGC_CTRL__MPC_MODE_MASK 1030 | UVD_CGC_CTRL__LBSI_MODE_MASK 1031 | UVD_CGC_CTRL__LRBBM_MODE_MASK 1032 | UVD_CGC_CTRL__WCB_MODE_MASK 1033 | UVD_CGC_CTRL__VCPU_MODE_MASK 1034 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 1035 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 1036 1037 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 1038 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 1039 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 1040 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 1041 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 1042 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 1043 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 1044 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 1045 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 1046 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 1047 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 1048 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 1049 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 1050 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 1051 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 1052 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 1053 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 1054 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 1055 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 1056 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 1057 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 1058 } 1059 1060 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 1061 { 1062 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1063 struct amdgpu_ring *ring; 1064 uint32_t rb_bufsz, tmp; 1065 1066 /* disable register anti-hang mechanism */ 1067 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 1068 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1069 /* enable dynamic power gating mode */ 1070 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 1071 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1072 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1073 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 1074 1075 if (indirect) 1076 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1077 1078 /* enable clock gating */ 1079 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 1080 1081 /* enable VCPU clock */ 1082 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1083 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1084 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 1085 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1086 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1087 1088 /* disable master interupt */ 1089 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1090 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 1091 1092 /* setup mmUVD_LMI_CTRL */ 1093 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1094 UVD_LMI_CTRL__REQ_MODE_MASK | 1095 UVD_LMI_CTRL__CRC_RESET_MASK | 1096 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1097 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1098 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1099 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1100 0x00100000L); 1101 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1102 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 1103 1104 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1105 VCN, inst_idx, mmUVD_MPC_CNTL), 1106 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1107 1108 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1109 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1110 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1111 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1112 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1113 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1114 1115 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1116 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1117 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1118 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1119 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1120 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1121 1122 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1123 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1124 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1125 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1126 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1127 1128 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1129 1130 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1131 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1132 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1133 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1134 1135 /* enable LMI MC and UMC channels */ 1136 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1137 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1138 1139 /* unblock VCPU register access */ 1140 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1141 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1142 1143 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1144 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1145 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1146 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1147 1148 /* enable master interrupt */ 1149 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1150 VCN, inst_idx, mmUVD_MASTINT_EN), 1151 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1152 1153 /* add nop to workaround PSP size check */ 1154 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1155 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1156 1157 if (indirect) 1158 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1159 1160 ring = &adev->vcn.inst[inst_idx].ring_dec; 1161 /* force RBC into idle state */ 1162 rb_bufsz = order_base_2(ring->ring_size); 1163 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1164 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1165 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1166 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1167 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1168 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1169 1170 /* Stall DPG before WPTR/RPTR reset */ 1171 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1172 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1173 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1174 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1175 1176 /* set the write pointer delay */ 1177 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1178 1179 /* set the wb address */ 1180 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1181 (upper_32_bits(ring->gpu_addr) >> 2)); 1182 1183 /* programm the RB_BASE for ring buffer */ 1184 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1185 lower_32_bits(ring->gpu_addr)); 1186 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1187 upper_32_bits(ring->gpu_addr)); 1188 1189 /* Initialize the ring buffer's read and write pointers */ 1190 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1191 1192 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1193 1194 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1195 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1196 lower_32_bits(ring->wptr)); 1197 1198 /* Reset FW shared memory RBC WPTR/RPTR */ 1199 fw_shared->rb.rptr = 0; 1200 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1201 1202 /*resetting done, fw can check RB ring */ 1203 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1204 1205 /* Unstall DPG */ 1206 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1207 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1208 1209 return 0; 1210 } 1211 1212 static int vcn_v3_0_start(struct amdgpu_device *adev) 1213 { 1214 volatile struct amdgpu_fw_shared *fw_shared; 1215 struct amdgpu_ring *ring; 1216 uint32_t rb_bufsz, tmp; 1217 int i, j, k, r; 1218 1219 if (adev->pm.dpm_enabled) 1220 amdgpu_dpm_enable_uvd(adev, true); 1221 1222 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1223 if (adev->vcn.harvest_config & (1 << i)) 1224 continue; 1225 1226 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1227 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1228 continue; 1229 } 1230 1231 /* disable VCN power gating */ 1232 vcn_v3_0_disable_static_power_gating(adev, i); 1233 1234 /* set VCN status busy */ 1235 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1236 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1237 1238 /*SW clock gating */ 1239 vcn_v3_0_disable_clock_gating(adev, i); 1240 1241 /* enable VCPU clock */ 1242 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1243 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1244 1245 /* disable master interrupt */ 1246 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1247 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1248 1249 /* enable LMI MC and UMC channels */ 1250 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1251 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1252 1253 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1254 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1255 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1256 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1257 1258 /* setup mmUVD_LMI_CTRL */ 1259 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1260 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1261 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1262 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1263 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1264 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1265 1266 /* setup mmUVD_MPC_CNTL */ 1267 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1268 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1269 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1270 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1271 1272 /* setup UVD_MPC_SET_MUXA0 */ 1273 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1274 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1275 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1276 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1277 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1278 1279 /* setup UVD_MPC_SET_MUXB0 */ 1280 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1281 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1282 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1283 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1284 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1285 1286 /* setup mmUVD_MPC_SET_MUX */ 1287 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1288 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1289 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1290 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1291 1292 vcn_v3_0_mc_resume(adev, i); 1293 1294 /* VCN global tiling registers */ 1295 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1296 adev->gfx.config.gb_addr_config); 1297 1298 /* unblock VCPU register access */ 1299 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1300 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1301 1302 /* release VCPU reset to boot */ 1303 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1304 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1305 1306 for (j = 0; j < 10; ++j) { 1307 uint32_t status; 1308 1309 for (k = 0; k < 100; ++k) { 1310 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1311 if (status & 2) 1312 break; 1313 mdelay(10); 1314 } 1315 r = 0; 1316 if (status & 2) 1317 break; 1318 1319 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1320 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1321 UVD_VCPU_CNTL__BLK_RST_MASK, 1322 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1323 mdelay(10); 1324 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1325 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1326 1327 mdelay(10); 1328 r = -1; 1329 } 1330 1331 if (r) { 1332 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1333 return r; 1334 } 1335 1336 /* enable master interrupt */ 1337 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1338 UVD_MASTINT_EN__VCPU_EN_MASK, 1339 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1340 1341 /* clear the busy bit of VCN_STATUS */ 1342 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1343 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1344 1345 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1346 1347 ring = &adev->vcn.inst[i].ring_dec; 1348 /* force RBC into idle state */ 1349 rb_bufsz = order_base_2(ring->ring_size); 1350 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1351 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1352 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1353 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1354 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1355 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1356 1357 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1358 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1359 1360 /* programm the RB_BASE for ring buffer */ 1361 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1362 lower_32_bits(ring->gpu_addr)); 1363 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1364 upper_32_bits(ring->gpu_addr)); 1365 1366 /* Initialize the ring buffer's read and write pointers */ 1367 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1368 1369 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1370 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1371 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1372 lower_32_bits(ring->wptr)); 1373 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1374 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1375 1376 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1377 IP_VERSION(3, 0, 33)) { 1378 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1379 ring = &adev->vcn.inst[i].ring_enc[0]; 1380 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1381 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1382 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1383 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1384 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1385 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1386 1387 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1388 ring = &adev->vcn.inst[i].ring_enc[1]; 1389 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1390 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1391 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1392 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1393 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1394 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1395 } 1396 } 1397 1398 return 0; 1399 } 1400 1401 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1402 { 1403 int i, j; 1404 struct amdgpu_ring *ring; 1405 uint64_t cache_addr; 1406 uint64_t rb_addr; 1407 uint64_t ctx_addr; 1408 uint32_t param, resp, expected; 1409 uint32_t offset, cache_size; 1410 uint32_t tmp, timeout; 1411 1412 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1413 uint32_t *table_loc; 1414 uint32_t table_size; 1415 uint32_t size, size_dw; 1416 1417 struct mmsch_v3_0_cmd_direct_write 1418 direct_wt = { {0} }; 1419 struct mmsch_v3_0_cmd_direct_read_modify_write 1420 direct_rd_mod_wt = { {0} }; 1421 struct mmsch_v3_0_cmd_end end = { {0} }; 1422 struct mmsch_v3_0_init_header header; 1423 1424 direct_wt.cmd_header.command_type = 1425 MMSCH_COMMAND__DIRECT_REG_WRITE; 1426 direct_rd_mod_wt.cmd_header.command_type = 1427 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1428 end.cmd_header.command_type = 1429 MMSCH_COMMAND__END; 1430 1431 header.version = MMSCH_VERSION; 1432 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1433 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) { 1434 header.inst[i].init_status = 0; 1435 header.inst[i].table_offset = 0; 1436 header.inst[i].table_size = 0; 1437 } 1438 1439 table_loc = (uint32_t *)table->cpu_addr; 1440 table_loc += header.total_size; 1441 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1442 if (adev->vcn.harvest_config & (1 << i)) 1443 continue; 1444 1445 table_size = 0; 1446 1447 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1448 mmUVD_STATUS), 1449 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1450 1451 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4); 1452 1453 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1454 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1455 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1456 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1457 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1458 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1459 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1460 offset = 0; 1461 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1462 mmUVD_VCPU_CACHE_OFFSET0), 1463 0); 1464 } else { 1465 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1466 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1467 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1468 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1469 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1470 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1471 offset = cache_size; 1472 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1473 mmUVD_VCPU_CACHE_OFFSET0), 1474 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1475 } 1476 1477 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1478 mmUVD_VCPU_CACHE_SIZE0), 1479 cache_size); 1480 1481 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1482 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1483 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1484 lower_32_bits(cache_addr)); 1485 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1486 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1487 upper_32_bits(cache_addr)); 1488 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1489 mmUVD_VCPU_CACHE_OFFSET1), 1490 0); 1491 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1492 mmUVD_VCPU_CACHE_SIZE1), 1493 AMDGPU_VCN_STACK_SIZE); 1494 1495 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1496 AMDGPU_VCN_STACK_SIZE; 1497 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1498 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1499 lower_32_bits(cache_addr)); 1500 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1501 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1502 upper_32_bits(cache_addr)); 1503 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1504 mmUVD_VCPU_CACHE_OFFSET2), 1505 0); 1506 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1507 mmUVD_VCPU_CACHE_SIZE2), 1508 AMDGPU_VCN_CONTEXT_SIZE); 1509 1510 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1511 ring = &adev->vcn.inst[i].ring_enc[j]; 1512 ring->wptr = 0; 1513 rb_addr = ring->gpu_addr; 1514 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1515 mmUVD_RB_BASE_LO), 1516 lower_32_bits(rb_addr)); 1517 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1518 mmUVD_RB_BASE_HI), 1519 upper_32_bits(rb_addr)); 1520 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1521 mmUVD_RB_SIZE), 1522 ring->ring_size / 4); 1523 } 1524 1525 ring = &adev->vcn.inst[i].ring_dec; 1526 ring->wptr = 0; 1527 rb_addr = ring->gpu_addr; 1528 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1529 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1530 lower_32_bits(rb_addr)); 1531 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1532 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1533 upper_32_bits(rb_addr)); 1534 /* force RBC into idle state */ 1535 tmp = order_base_2(ring->ring_size); 1536 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1537 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1538 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1539 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1540 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1541 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1542 mmUVD_RBC_RB_CNTL), 1543 tmp); 1544 1545 /* add end packet */ 1546 MMSCH_V3_0_INSERT_END(); 1547 1548 /* refine header */ 1549 header.inst[i].init_status = 0; 1550 header.inst[i].table_offset = header.total_size; 1551 header.inst[i].table_size = table_size; 1552 header.total_size += table_size; 1553 } 1554 1555 /* Update init table header in memory */ 1556 size = sizeof(struct mmsch_v3_0_init_header); 1557 table_loc = (uint32_t *)table->cpu_addr; 1558 memcpy((void *)table_loc, &header, size); 1559 1560 /* message MMSCH (in VCN[0]) to initialize this client 1561 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1562 * of memory descriptor location 1563 */ 1564 ctx_addr = table->gpu_addr; 1565 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1566 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1567 1568 /* 2, update vmid of descriptor */ 1569 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1570 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1571 /* use domain0 for MM scheduler */ 1572 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1573 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1574 1575 /* 3, notify mmsch about the size of this descriptor */ 1576 size = header.total_size; 1577 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1578 1579 /* 4, set resp to zero */ 1580 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1581 1582 /* 5, kick off the initialization and wait until 1583 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1584 */ 1585 param = 0x10000001; 1586 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1587 tmp = 0; 1588 timeout = 1000; 1589 resp = 0; 1590 expected = param + 1; 1591 while (resp != expected) { 1592 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1593 if (resp == expected) 1594 break; 1595 1596 udelay(10); 1597 tmp = tmp + 10; 1598 if (tmp >= timeout) { 1599 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1600 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1601 "(expected=0x%08x, readback=0x%08x)\n", 1602 tmp, expected, resp); 1603 return -EBUSY; 1604 } 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1611 { 1612 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1613 uint32_t tmp; 1614 1615 vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state); 1616 1617 /* Wait for power status to be 1 */ 1618 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1619 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1620 1621 /* wait for read ptr to be equal to write ptr */ 1622 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1623 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1624 1625 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1626 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1627 1628 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1629 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1630 1631 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1632 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1633 1634 /* disable dynamic power gating mode */ 1635 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1636 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1637 1638 return 0; 1639 } 1640 1641 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1642 { 1643 uint32_t tmp; 1644 int i, r = 0; 1645 1646 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1647 if (adev->vcn.harvest_config & (1 << i)) 1648 continue; 1649 1650 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1651 r = vcn_v3_0_stop_dpg_mode(adev, i); 1652 continue; 1653 } 1654 1655 /* wait for vcn idle */ 1656 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1657 if (r) 1658 return r; 1659 1660 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1661 UVD_LMI_STATUS__READ_CLEAN_MASK | 1662 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1663 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1664 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1665 if (r) 1666 return r; 1667 1668 /* disable LMI UMC channel */ 1669 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1670 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1671 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1672 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1673 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1674 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1675 if (r) 1676 return r; 1677 1678 /* block VCPU register access */ 1679 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1680 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1681 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1682 1683 /* reset VCPU */ 1684 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1685 UVD_VCPU_CNTL__BLK_RST_MASK, 1686 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1687 1688 /* disable VCPU clock */ 1689 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1690 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1691 1692 /* apply soft reset */ 1693 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1694 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1695 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1696 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1697 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1698 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1699 1700 /* clear status */ 1701 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1702 1703 /* apply HW clock gating */ 1704 vcn_v3_0_enable_clock_gating(adev, i); 1705 1706 /* enable VCN power gating */ 1707 vcn_v3_0_enable_static_power_gating(adev, i); 1708 } 1709 1710 if (adev->pm.dpm_enabled) 1711 amdgpu_dpm_enable_uvd(adev, false); 1712 1713 return 0; 1714 } 1715 1716 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1717 int inst_idx, struct dpg_pause_state *new_state) 1718 { 1719 volatile struct amdgpu_fw_shared *fw_shared; 1720 struct amdgpu_ring *ring; 1721 uint32_t reg_data = 0; 1722 int ret_code; 1723 1724 /* pause/unpause if state is changed */ 1725 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1726 DRM_DEBUG("dpg pause state changed %d -> %d", 1727 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1728 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1729 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1730 1731 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1732 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1733 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1734 1735 if (!ret_code) { 1736 /* pause DPG */ 1737 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1738 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1739 1740 /* wait for ACK */ 1741 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1742 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1743 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1744 1745 /* Stall DPG before WPTR/RPTR reset */ 1746 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1747 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1748 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1749 1750 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1751 IP_VERSION(3, 0, 33)) { 1752 /* Restore */ 1753 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1754 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1755 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1756 ring->wptr = 0; 1757 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1758 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1759 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1760 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1761 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1762 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1763 1764 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1765 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1766 ring->wptr = 0; 1767 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1768 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1769 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1770 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1771 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1772 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1773 1774 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1775 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1776 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1777 } 1778 1779 /* Unstall DPG */ 1780 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1781 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1782 1783 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1784 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1785 } 1786 } else { 1787 /* unpause dpg, no need to wait */ 1788 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1789 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1790 } 1791 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1792 } 1793 1794 return 0; 1795 } 1796 1797 /** 1798 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1799 * 1800 * @ring: amdgpu_ring pointer 1801 * 1802 * Returns the current hardware read pointer 1803 */ 1804 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1805 { 1806 struct amdgpu_device *adev = ring->adev; 1807 1808 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1809 } 1810 1811 /** 1812 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1813 * 1814 * @ring: amdgpu_ring pointer 1815 * 1816 * Returns the current hardware write pointer 1817 */ 1818 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1819 { 1820 struct amdgpu_device *adev = ring->adev; 1821 1822 if (ring->use_doorbell) 1823 return *ring->wptr_cpu_addr; 1824 else 1825 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1826 } 1827 1828 /** 1829 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1830 * 1831 * @ring: amdgpu_ring pointer 1832 * 1833 * Commits the write pointer to the hardware 1834 */ 1835 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1836 { 1837 struct amdgpu_device *adev = ring->adev; 1838 volatile struct amdgpu_fw_shared *fw_shared; 1839 1840 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1841 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1842 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1843 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1844 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1845 lower_32_bits(ring->wptr)); 1846 } 1847 1848 if (ring->use_doorbell) { 1849 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1850 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1851 } else { 1852 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1853 } 1854 } 1855 1856 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1857 .type = AMDGPU_RING_TYPE_VCN_DEC, 1858 .align_mask = 0x3f, 1859 .nop = VCN_DEC_SW_CMD_NO_OP, 1860 .secure_submission_supported = true, 1861 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1862 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1863 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1864 .emit_frame_size = 1865 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1866 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1867 VCN_SW_RING_EMIT_FRAME_SIZE, 1868 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1869 .emit_ib = vcn_dec_sw_ring_emit_ib, 1870 .emit_fence = vcn_dec_sw_ring_emit_fence, 1871 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1872 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1873 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1874 .insert_nop = amdgpu_ring_insert_nop, 1875 .insert_end = vcn_dec_sw_ring_insert_end, 1876 .pad_ib = amdgpu_ring_generic_pad_ib, 1877 .begin_use = amdgpu_vcn_ring_begin_use, 1878 .end_use = amdgpu_vcn_ring_end_use, 1879 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1880 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1881 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1882 }; 1883 1884 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1885 struct amdgpu_job *job) 1886 { 1887 struct drm_gpu_scheduler **scheds; 1888 1889 /* The create msg must be in the first IB submitted */ 1890 if (atomic_read(&job->base.entity->fence_seq)) 1891 return -EINVAL; 1892 1893 /* if VCN0 is harvested, we can't support AV1 */ 1894 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1895 return -EINVAL; 1896 1897 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1898 [AMDGPU_RING_PRIO_DEFAULT].sched; 1899 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1900 return 0; 1901 } 1902 1903 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1904 uint64_t addr) 1905 { 1906 struct ttm_operation_ctx ctx = { false, false }; 1907 struct amdgpu_bo_va_mapping *map; 1908 uint32_t *msg, num_buffers; 1909 struct amdgpu_bo *bo; 1910 uint64_t start, end; 1911 unsigned int i; 1912 void *ptr; 1913 int r; 1914 1915 addr &= AMDGPU_GMC_HOLE_MASK; 1916 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1917 if (r) { 1918 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1919 return r; 1920 } 1921 1922 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1923 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1924 if (addr & 0x7) { 1925 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1926 return -EINVAL; 1927 } 1928 1929 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1930 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1931 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1932 if (r) { 1933 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1934 return r; 1935 } 1936 1937 r = amdgpu_bo_kmap(bo, &ptr); 1938 if (r) { 1939 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1940 return r; 1941 } 1942 1943 msg = ptr + addr - start; 1944 1945 /* Check length */ 1946 if (msg[1] > end - addr) { 1947 r = -EINVAL; 1948 goto out; 1949 } 1950 1951 if (msg[3] != RDECODE_MSG_CREATE) 1952 goto out; 1953 1954 num_buffers = msg[2]; 1955 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1956 uint32_t offset, size, *create; 1957 1958 if (msg[0] != RDECODE_MESSAGE_CREATE) 1959 continue; 1960 1961 offset = msg[1]; 1962 size = msg[2]; 1963 1964 if (offset + size > end) { 1965 r = -EINVAL; 1966 goto out; 1967 } 1968 1969 create = ptr + addr + offset - start; 1970 1971 /* H246, HEVC and VP9 can run on any instance */ 1972 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1973 continue; 1974 1975 r = vcn_v3_0_limit_sched(p, job); 1976 if (r) 1977 goto out; 1978 } 1979 1980 out: 1981 amdgpu_bo_kunmap(bo); 1982 return r; 1983 } 1984 1985 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1986 struct amdgpu_job *job, 1987 struct amdgpu_ib *ib) 1988 { 1989 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1990 uint32_t msg_lo = 0, msg_hi = 0; 1991 unsigned i; 1992 int r; 1993 1994 /* The first instance can decode anything */ 1995 if (!ring->me) 1996 return 0; 1997 1998 for (i = 0; i < ib->length_dw; i += 2) { 1999 uint32_t reg = amdgpu_ib_get_value(ib, i); 2000 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 2001 2002 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 2003 msg_lo = val; 2004 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 2005 msg_hi = val; 2006 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 2007 val == 0) { 2008 r = vcn_v3_0_dec_msg(p, job, 2009 ((u64)msg_hi) << 32 | msg_lo); 2010 if (r) 2011 return r; 2012 } 2013 } 2014 return 0; 2015 } 2016 2017 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 2018 .type = AMDGPU_RING_TYPE_VCN_DEC, 2019 .align_mask = 0xf, 2020 .secure_submission_supported = true, 2021 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 2022 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 2023 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 2024 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 2025 .emit_frame_size = 2026 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2027 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2028 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2029 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2030 6, 2031 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2032 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2033 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2034 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2035 .test_ring = vcn_v2_0_dec_ring_test_ring, 2036 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2037 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2038 .insert_start = vcn_v2_0_dec_ring_insert_start, 2039 .insert_end = vcn_v2_0_dec_ring_insert_end, 2040 .pad_ib = amdgpu_ring_generic_pad_ib, 2041 .begin_use = amdgpu_vcn_ring_begin_use, 2042 .end_use = amdgpu_vcn_ring_end_use, 2043 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2044 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2045 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2046 }; 2047 2048 /** 2049 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2050 * 2051 * @ring: amdgpu_ring pointer 2052 * 2053 * Returns the current hardware enc read pointer 2054 */ 2055 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2056 { 2057 struct amdgpu_device *adev = ring->adev; 2058 2059 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2060 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2061 else 2062 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2063 } 2064 2065 /** 2066 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2067 * 2068 * @ring: amdgpu_ring pointer 2069 * 2070 * Returns the current hardware enc write pointer 2071 */ 2072 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2073 { 2074 struct amdgpu_device *adev = ring->adev; 2075 2076 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2077 if (ring->use_doorbell) 2078 return *ring->wptr_cpu_addr; 2079 else 2080 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2081 } else { 2082 if (ring->use_doorbell) 2083 return *ring->wptr_cpu_addr; 2084 else 2085 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2086 } 2087 } 2088 2089 /** 2090 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2091 * 2092 * @ring: amdgpu_ring pointer 2093 * 2094 * Commits the enc write pointer to the hardware 2095 */ 2096 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2097 { 2098 struct amdgpu_device *adev = ring->adev; 2099 2100 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2101 if (ring->use_doorbell) { 2102 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2103 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2104 } else { 2105 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2106 } 2107 } else { 2108 if (ring->use_doorbell) { 2109 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2110 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2111 } else { 2112 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2113 } 2114 } 2115 } 2116 2117 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2118 .type = AMDGPU_RING_TYPE_VCN_ENC, 2119 .align_mask = 0x3f, 2120 .nop = VCN_ENC_CMD_NO_OP, 2121 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2122 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2123 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2124 .emit_frame_size = 2125 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2126 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2127 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2128 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2129 1, /* vcn_v2_0_enc_ring_insert_end */ 2130 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2131 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2132 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2133 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2134 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2135 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2136 .insert_nop = amdgpu_ring_insert_nop, 2137 .insert_end = vcn_v2_0_enc_ring_insert_end, 2138 .pad_ib = amdgpu_ring_generic_pad_ib, 2139 .begin_use = amdgpu_vcn_ring_begin_use, 2140 .end_use = amdgpu_vcn_ring_end_use, 2141 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2142 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2143 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2144 }; 2145 2146 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2147 { 2148 int i; 2149 2150 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2151 if (adev->vcn.harvest_config & (1 << i)) 2152 continue; 2153 2154 if (!DEC_SW_RING_ENABLED) 2155 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2156 else 2157 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2158 adev->vcn.inst[i].ring_dec.me = i; 2159 } 2160 } 2161 2162 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2163 { 2164 int i, j; 2165 2166 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2167 if (adev->vcn.harvest_config & (1 << i)) 2168 continue; 2169 2170 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2171 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2172 adev->vcn.inst[i].ring_enc[j].me = i; 2173 } 2174 } 2175 } 2176 2177 static bool vcn_v3_0_is_idle(void *handle) 2178 { 2179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2180 int i, ret = 1; 2181 2182 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2183 if (adev->vcn.harvest_config & (1 << i)) 2184 continue; 2185 2186 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2187 } 2188 2189 return ret; 2190 } 2191 2192 static int vcn_v3_0_wait_for_idle(void *handle) 2193 { 2194 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2195 int i, ret = 0; 2196 2197 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2198 if (adev->vcn.harvest_config & (1 << i)) 2199 continue; 2200 2201 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2202 UVD_STATUS__IDLE); 2203 if (ret) 2204 return ret; 2205 } 2206 2207 return ret; 2208 } 2209 2210 static int vcn_v3_0_set_clockgating_state(void *handle, 2211 enum amd_clockgating_state state) 2212 { 2213 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2214 bool enable = state == AMD_CG_STATE_GATE; 2215 int i; 2216 2217 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2218 if (adev->vcn.harvest_config & (1 << i)) 2219 continue; 2220 2221 if (enable) { 2222 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2223 return -EBUSY; 2224 vcn_v3_0_enable_clock_gating(adev, i); 2225 } else { 2226 vcn_v3_0_disable_clock_gating(adev, i); 2227 } 2228 } 2229 2230 return 0; 2231 } 2232 2233 static int vcn_v3_0_set_powergating_state(void *handle, 2234 enum amd_powergating_state state) 2235 { 2236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2237 int ret; 2238 2239 /* for SRIOV, guest should not control VCN Power-gating 2240 * MMSCH FW should control Power-gating and clock-gating 2241 * guest should avoid touching CGC and PG 2242 */ 2243 if (amdgpu_sriov_vf(adev)) { 2244 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2245 return 0; 2246 } 2247 2248 if (state == adev->vcn.cur_state) 2249 return 0; 2250 2251 if (state == AMD_PG_STATE_GATE) 2252 ret = vcn_v3_0_stop(adev); 2253 else 2254 ret = vcn_v3_0_start(adev); 2255 2256 if (!ret) 2257 adev->vcn.cur_state = state; 2258 2259 return ret; 2260 } 2261 2262 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2263 struct amdgpu_irq_src *source, 2264 unsigned type, 2265 enum amdgpu_interrupt_state state) 2266 { 2267 return 0; 2268 } 2269 2270 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2271 struct amdgpu_irq_src *source, 2272 struct amdgpu_iv_entry *entry) 2273 { 2274 uint32_t ip_instance; 2275 2276 switch (entry->client_id) { 2277 case SOC15_IH_CLIENTID_VCN: 2278 ip_instance = 0; 2279 break; 2280 case SOC15_IH_CLIENTID_VCN1: 2281 ip_instance = 1; 2282 break; 2283 default: 2284 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2285 return 0; 2286 } 2287 2288 DRM_DEBUG("IH: VCN TRAP\n"); 2289 2290 switch (entry->src_id) { 2291 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2292 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2293 break; 2294 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2295 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2296 break; 2297 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2298 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2299 break; 2300 default: 2301 DRM_ERROR("Unhandled interrupt: %d %d\n", 2302 entry->src_id, entry->src_data[0]); 2303 break; 2304 } 2305 2306 return 0; 2307 } 2308 2309 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2310 .set = vcn_v3_0_set_interrupt_state, 2311 .process = vcn_v3_0_process_interrupt, 2312 }; 2313 2314 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2315 { 2316 int i; 2317 2318 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2319 if (adev->vcn.harvest_config & (1 << i)) 2320 continue; 2321 2322 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2323 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2324 } 2325 } 2326 2327 static void vcn_v3_0_print_ip_state(void *handle, struct drm_printer *p) 2328 { 2329 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2330 int i, j; 2331 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 2332 uint32_t inst_off, is_powered; 2333 2334 if (!adev->vcn.ip_dump) 2335 return; 2336 2337 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2338 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2339 if (adev->vcn.harvest_config & (1 << i)) { 2340 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2341 continue; 2342 } 2343 2344 inst_off = i * reg_count; 2345 is_powered = (adev->vcn.ip_dump[inst_off] & 2346 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2347 2348 if (is_powered) { 2349 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2350 for (j = 0; j < reg_count; j++) 2351 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name, 2352 adev->vcn.ip_dump[inst_off + j]); 2353 } else { 2354 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2355 } 2356 } 2357 } 2358 2359 static void vcn_v3_0_dump_ip_state(void *handle) 2360 { 2361 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2362 int i, j; 2363 bool is_powered; 2364 uint32_t inst_off; 2365 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); 2366 2367 if (!adev->vcn.ip_dump) 2368 return; 2369 2370 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2371 if (adev->vcn.harvest_config & (1 << i)) 2372 continue; 2373 2374 inst_off = i * reg_count; 2375 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2376 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 2377 is_powered = (adev->vcn.ip_dump[inst_off] & 2378 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2379 2380 if (is_powered) 2381 for (j = 1; j < reg_count; j++) 2382 adev->vcn.ip_dump[inst_off + j] = 2383 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i)); 2384 } 2385 } 2386 2387 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2388 .name = "vcn_v3_0", 2389 .early_init = vcn_v3_0_early_init, 2390 .late_init = NULL, 2391 .sw_init = vcn_v3_0_sw_init, 2392 .sw_fini = vcn_v3_0_sw_fini, 2393 .hw_init = vcn_v3_0_hw_init, 2394 .hw_fini = vcn_v3_0_hw_fini, 2395 .suspend = vcn_v3_0_suspend, 2396 .resume = vcn_v3_0_resume, 2397 .is_idle = vcn_v3_0_is_idle, 2398 .wait_for_idle = vcn_v3_0_wait_for_idle, 2399 .check_soft_reset = NULL, 2400 .pre_soft_reset = NULL, 2401 .soft_reset = NULL, 2402 .post_soft_reset = NULL, 2403 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2404 .set_powergating_state = vcn_v3_0_set_powergating_state, 2405 .dump_ip_state = vcn_v3_0_dump_ip_state, 2406 .print_ip_state = vcn_v3_0_print_ip_state, 2407 }; 2408 2409 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { 2410 .type = AMD_IP_BLOCK_TYPE_VCN, 2411 .major = 3, 2412 .minor = 0, 2413 .rev = 0, 2414 .funcs = &vcn_v3_0_ip_funcs, 2415 }; 2416