1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 #define DEC_SW_RING_ENABLED FALSE 52 53 #define RDECODE_MSG_CREATE 0x00000000 54 #define RDECODE_MESSAGE_CREATE 0x00000001 55 56 static int amdgpu_ih_clientid_vcns[] = { 57 SOC15_IH_CLIENTID_VCN, 58 SOC15_IH_CLIENTID_VCN1 59 }; 60 61 static int amdgpu_ucode_id_vcns[] = { 62 AMDGPU_UCODE_ID_VCN, 63 AMDGPU_UCODE_ID_VCN1 64 }; 65 66 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 67 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 68 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 69 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 70 static int vcn_v3_0_set_powergating_state(void *handle, 71 enum amd_powergating_state state); 72 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 73 int inst_idx, struct dpg_pause_state *new_state); 74 75 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 76 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 77 78 /** 79 * vcn_v3_0_early_init - set function pointers 80 * 81 * @handle: amdgpu_device pointer 82 * 83 * Set ring and irq function pointers 84 */ 85 static int vcn_v3_0_early_init(void *handle) 86 { 87 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 88 89 if (amdgpu_sriov_vf(adev)) { 90 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 91 adev->vcn.harvest_config = 0; 92 adev->vcn.num_enc_rings = 1; 93 94 } else { 95 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 96 u32 harvest; 97 int i; 98 99 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 101 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 102 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 103 adev->vcn.harvest_config |= 1 << i; 104 } 105 106 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 107 AMDGPU_VCN_HARVEST_VCN1)) 108 /* both instances are harvested, disable the block */ 109 return -ENOENT; 110 } else 111 adev->vcn.num_vcn_inst = 1; 112 113 adev->vcn.num_enc_rings = 2; 114 } 115 116 vcn_v3_0_set_dec_ring_funcs(adev); 117 vcn_v3_0_set_enc_ring_funcs(adev); 118 vcn_v3_0_set_irq_funcs(adev); 119 120 return 0; 121 } 122 123 /** 124 * vcn_v3_0_sw_init - sw init for VCN block 125 * 126 * @handle: amdgpu_device pointer 127 * 128 * Load firmware and sw initialization 129 */ 130 static int vcn_v3_0_sw_init(void *handle) 131 { 132 struct amdgpu_ring *ring; 133 int i, j, r; 134 int vcn_doorbell_index = 0; 135 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 136 137 r = amdgpu_vcn_sw_init(adev); 138 if (r) 139 return r; 140 141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 142 const struct common_firmware_header *hdr; 143 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 144 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 146 adev->firmware.fw_size += 147 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 148 149 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 152 adev->firmware.fw_size += 153 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 154 } 155 DRM_INFO("PSP loading VCN firmware\n"); 156 } 157 158 r = amdgpu_vcn_resume(adev); 159 if (r) 160 return r; 161 162 /* 163 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 164 * Formula: 165 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 166 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 167 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 168 */ 169 if (amdgpu_sriov_vf(adev)) { 170 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 171 /* get DWORD offset */ 172 vcn_doorbell_index = vcn_doorbell_index << 1; 173 } 174 175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 176 volatile struct amdgpu_fw_shared *fw_shared; 177 178 if (adev->vcn.harvest_config & (1 << i)) 179 continue; 180 181 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 182 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 183 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 184 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 185 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 186 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 187 188 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 189 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 190 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 191 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 192 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 193 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 194 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 195 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 196 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 197 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 198 199 /* VCN DEC TRAP */ 200 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 201 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 202 if (r) 203 return r; 204 205 atomic_set(&adev->vcn.inst[i].sched_score, 0); 206 207 ring = &adev->vcn.inst[i].ring_dec; 208 ring->use_doorbell = true; 209 if (amdgpu_sriov_vf(adev)) { 210 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1); 211 } else { 212 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 213 } 214 sprintf(ring->name, "vcn_dec_%d", i); 215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 216 AMDGPU_RING_PRIO_DEFAULT, 217 &adev->vcn.inst[i].sched_score); 218 if (r) 219 return r; 220 221 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 222 /* VCN ENC TRAP */ 223 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 224 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 225 if (r) 226 return r; 227 228 ring = &adev->vcn.inst[i].ring_enc[j]; 229 ring->use_doorbell = true; 230 if (amdgpu_sriov_vf(adev)) { 231 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j; 232 } else { 233 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 234 } 235 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 236 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 237 AMDGPU_RING_PRIO_DEFAULT, 238 &adev->vcn.inst[i].sched_score); 239 if (r) 240 return r; 241 } 242 243 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 244 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 245 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 246 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 247 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 248 } 249 250 if (amdgpu_sriov_vf(adev)) { 251 r = amdgpu_virt_alloc_mm_table(adev); 252 if (r) 253 return r; 254 } 255 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 256 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 257 258 return 0; 259 } 260 261 /** 262 * vcn_v3_0_sw_fini - sw fini for VCN block 263 * 264 * @handle: amdgpu_device pointer 265 * 266 * VCN suspend and free up sw allocation 267 */ 268 static int vcn_v3_0_sw_fini(void *handle) 269 { 270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 271 int i, r; 272 273 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 274 volatile struct amdgpu_fw_shared *fw_shared; 275 276 if (adev->vcn.harvest_config & (1 << i)) 277 continue; 278 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 279 fw_shared->present_flag_0 = 0; 280 fw_shared->sw_ring.is_enabled = false; 281 } 282 283 if (amdgpu_sriov_vf(adev)) 284 amdgpu_virt_free_mm_table(adev); 285 286 r = amdgpu_vcn_suspend(adev); 287 if (r) 288 return r; 289 290 r = amdgpu_vcn_sw_fini(adev); 291 292 return r; 293 } 294 295 /** 296 * vcn_v3_0_hw_init - start and test VCN block 297 * 298 * @handle: amdgpu_device pointer 299 * 300 * Initialize the hardware, boot up the VCPU and do some testing 301 */ 302 static int vcn_v3_0_hw_init(void *handle) 303 { 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 struct amdgpu_ring *ring; 306 int i, j, r; 307 308 if (amdgpu_sriov_vf(adev)) { 309 r = vcn_v3_0_start_sriov(adev); 310 if (r) 311 goto done; 312 313 /* initialize VCN dec and enc ring buffers */ 314 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 315 if (adev->vcn.harvest_config & (1 << i)) 316 continue; 317 318 ring = &adev->vcn.inst[i].ring_dec; 319 if (ring->sched.ready) { 320 ring->wptr = 0; 321 ring->wptr_old = 0; 322 vcn_v3_0_dec_ring_set_wptr(ring); 323 } 324 325 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 326 ring = &adev->vcn.inst[i].ring_enc[j]; 327 if (ring->sched.ready) { 328 ring->wptr = 0; 329 ring->wptr_old = 0; 330 vcn_v3_0_enc_ring_set_wptr(ring); 331 } 332 } 333 } 334 } else { 335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 336 if (adev->vcn.harvest_config & (1 << i)) 337 continue; 338 339 ring = &adev->vcn.inst[i].ring_dec; 340 341 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 342 ring->doorbell_index, i); 343 344 r = amdgpu_ring_test_helper(ring); 345 if (r) 346 goto done; 347 348 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 349 ring = &adev->vcn.inst[i].ring_enc[j]; 350 r = amdgpu_ring_test_helper(ring); 351 if (r) 352 goto done; 353 } 354 } 355 } 356 357 done: 358 if (!r) 359 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 360 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 361 362 return r; 363 } 364 365 /** 366 * vcn_v3_0_hw_fini - stop the hardware block 367 * 368 * @handle: amdgpu_device pointer 369 * 370 * Stop the VCN block, mark ring as not ready any more 371 */ 372 static int vcn_v3_0_hw_fini(void *handle) 373 { 374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 375 struct amdgpu_ring *ring; 376 int i, j; 377 378 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 379 if (adev->vcn.harvest_config & (1 << i)) 380 continue; 381 382 ring = &adev->vcn.inst[i].ring_dec; 383 384 if (!amdgpu_sriov_vf(adev)) { 385 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 386 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 387 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 388 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 389 } 390 } 391 ring->sched.ready = false; 392 393 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 394 ring = &adev->vcn.inst[i].ring_enc[j]; 395 ring->sched.ready = false; 396 } 397 } 398 399 return 0; 400 } 401 402 /** 403 * vcn_v3_0_suspend - suspend VCN block 404 * 405 * @handle: amdgpu_device pointer 406 * 407 * HW fini and suspend VCN block 408 */ 409 static int vcn_v3_0_suspend(void *handle) 410 { 411 int r; 412 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 413 414 r = vcn_v3_0_hw_fini(adev); 415 if (r) 416 return r; 417 418 r = amdgpu_vcn_suspend(adev); 419 420 return r; 421 } 422 423 /** 424 * vcn_v3_0_resume - resume VCN block 425 * 426 * @handle: amdgpu_device pointer 427 * 428 * Resume firmware and hw init VCN block 429 */ 430 static int vcn_v3_0_resume(void *handle) 431 { 432 int r; 433 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 434 435 r = amdgpu_vcn_resume(adev); 436 if (r) 437 return r; 438 439 r = vcn_v3_0_hw_init(adev); 440 441 return r; 442 } 443 444 /** 445 * vcn_v3_0_mc_resume - memory controller programming 446 * 447 * @adev: amdgpu_device pointer 448 * @inst: instance number 449 * 450 * Let the VCN memory controller know it's offsets 451 */ 452 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 453 { 454 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 455 uint32_t offset; 456 457 /* cache window 0: fw */ 458 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 461 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 463 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 464 offset = 0; 465 } else { 466 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 467 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 468 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 469 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 470 offset = size; 471 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 472 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 473 } 474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 475 476 /* cache window 1: stack */ 477 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 478 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 479 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 480 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 481 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 482 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 483 484 /* cache window 2: context */ 485 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 486 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 487 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 488 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 489 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 490 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 491 492 /* non-cache window */ 493 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 494 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 495 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 496 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr)); 497 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 498 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 499 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 500 } 501 502 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 503 { 504 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 505 uint32_t offset; 506 507 /* cache window 0: fw */ 508 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 509 if (!indirect) { 510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 511 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 512 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 515 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 517 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 518 } else { 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 524 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 525 } 526 offset = 0; 527 } else { 528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 529 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 530 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 532 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 533 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 534 offset = size; 535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 536 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 537 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 538 } 539 540 if (!indirect) 541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 542 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 543 else 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 546 547 /* cache window 1: stack */ 548 if (!indirect) { 549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 550 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 551 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 554 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 557 } else { 558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 559 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 563 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 564 } 565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 566 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 567 568 /* cache window 2: context */ 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 571 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 573 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 574 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 576 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 578 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 579 580 /* non-cache window */ 581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 582 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 583 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 585 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 586 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect); 587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 588 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 590 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 591 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 592 } 593 594 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 595 { 596 uint32_t data = 0; 597 598 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 599 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 600 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 601 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 602 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 603 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 604 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 605 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 606 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 607 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 608 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 609 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 610 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 613 614 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 615 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 616 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 617 } else { 618 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 619 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 620 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 621 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 622 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 623 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 624 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 625 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 626 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 627 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 628 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 629 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 630 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 631 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 632 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 633 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 634 } 635 636 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 637 data &= ~0x103; 638 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 639 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 640 UVD_POWER_STATUS__UVD_PG_EN_MASK; 641 642 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 643 } 644 645 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 646 { 647 uint32_t data; 648 649 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 650 /* Before power off, this indicator has to be turned on */ 651 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 652 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 653 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 654 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 655 656 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 657 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 658 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 659 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 660 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 661 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 662 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 663 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 664 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 665 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 666 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 667 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 668 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 669 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 670 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 671 672 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 673 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 674 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 675 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 676 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 677 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 678 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 679 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 680 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 681 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 682 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 683 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 684 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 685 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 686 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 687 } 688 } 689 690 /** 691 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 692 * 693 * @adev: amdgpu_device pointer 694 * @inst: instance number 695 * 696 * Disable clock gating for VCN block 697 */ 698 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 699 { 700 uint32_t data; 701 702 /* VCN disable CGC */ 703 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 704 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 705 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 706 else 707 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 708 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 709 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 710 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 711 712 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 713 data &= ~(UVD_CGC_GATE__SYS_MASK 714 | UVD_CGC_GATE__UDEC_MASK 715 | UVD_CGC_GATE__MPEG2_MASK 716 | UVD_CGC_GATE__REGS_MASK 717 | UVD_CGC_GATE__RBC_MASK 718 | UVD_CGC_GATE__LMI_MC_MASK 719 | UVD_CGC_GATE__LMI_UMC_MASK 720 | UVD_CGC_GATE__IDCT_MASK 721 | UVD_CGC_GATE__MPRD_MASK 722 | UVD_CGC_GATE__MPC_MASK 723 | UVD_CGC_GATE__LBSI_MASK 724 | UVD_CGC_GATE__LRBBM_MASK 725 | UVD_CGC_GATE__UDEC_RE_MASK 726 | UVD_CGC_GATE__UDEC_CM_MASK 727 | UVD_CGC_GATE__UDEC_IT_MASK 728 | UVD_CGC_GATE__UDEC_DB_MASK 729 | UVD_CGC_GATE__UDEC_MP_MASK 730 | UVD_CGC_GATE__WCB_MASK 731 | UVD_CGC_GATE__VCPU_MASK 732 | UVD_CGC_GATE__MMSCH_MASK); 733 734 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 735 736 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 737 738 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 739 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 740 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 741 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 742 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 743 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 744 | UVD_CGC_CTRL__SYS_MODE_MASK 745 | UVD_CGC_CTRL__UDEC_MODE_MASK 746 | UVD_CGC_CTRL__MPEG2_MODE_MASK 747 | UVD_CGC_CTRL__REGS_MODE_MASK 748 | UVD_CGC_CTRL__RBC_MODE_MASK 749 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 750 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 751 | UVD_CGC_CTRL__IDCT_MODE_MASK 752 | UVD_CGC_CTRL__MPRD_MODE_MASK 753 | UVD_CGC_CTRL__MPC_MODE_MASK 754 | UVD_CGC_CTRL__LBSI_MODE_MASK 755 | UVD_CGC_CTRL__LRBBM_MODE_MASK 756 | UVD_CGC_CTRL__WCB_MODE_MASK 757 | UVD_CGC_CTRL__VCPU_MODE_MASK 758 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 759 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 760 761 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 762 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 763 | UVD_SUVD_CGC_GATE__SIT_MASK 764 | UVD_SUVD_CGC_GATE__SMP_MASK 765 | UVD_SUVD_CGC_GATE__SCM_MASK 766 | UVD_SUVD_CGC_GATE__SDB_MASK 767 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 768 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 769 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 770 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 771 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 772 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 773 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 774 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 775 | UVD_SUVD_CGC_GATE__SCLR_MASK 776 | UVD_SUVD_CGC_GATE__ENT_MASK 777 | UVD_SUVD_CGC_GATE__IME_MASK 778 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 779 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 780 | UVD_SUVD_CGC_GATE__SITE_MASK 781 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 782 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 783 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 784 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 785 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 786 | UVD_SUVD_CGC_GATE__EFC_MASK 787 | UVD_SUVD_CGC_GATE__SAOE_MASK 788 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 789 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 790 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 791 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 792 | UVD_SUVD_CGC_GATE__SMPA_MASK); 793 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 794 795 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 796 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 797 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 798 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 799 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 800 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 801 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 802 803 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 804 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 805 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 806 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 807 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 808 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 809 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 810 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 811 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 812 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 813 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 814 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 815 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 816 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 817 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 818 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 819 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 822 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 823 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 824 } 825 826 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 827 uint8_t sram_sel, int inst_idx, uint8_t indirect) 828 { 829 uint32_t reg_data = 0; 830 831 /* enable sw clock gating control */ 832 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 833 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 834 else 835 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 836 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 837 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 838 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 839 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 840 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 841 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 842 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 843 UVD_CGC_CTRL__SYS_MODE_MASK | 844 UVD_CGC_CTRL__UDEC_MODE_MASK | 845 UVD_CGC_CTRL__MPEG2_MODE_MASK | 846 UVD_CGC_CTRL__REGS_MODE_MASK | 847 UVD_CGC_CTRL__RBC_MODE_MASK | 848 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 849 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 850 UVD_CGC_CTRL__IDCT_MODE_MASK | 851 UVD_CGC_CTRL__MPRD_MODE_MASK | 852 UVD_CGC_CTRL__MPC_MODE_MASK | 853 UVD_CGC_CTRL__LBSI_MODE_MASK | 854 UVD_CGC_CTRL__LRBBM_MODE_MASK | 855 UVD_CGC_CTRL__WCB_MODE_MASK | 856 UVD_CGC_CTRL__VCPU_MODE_MASK | 857 UVD_CGC_CTRL__MMSCH_MODE_MASK); 858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 860 861 /* turn off clock gating */ 862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 863 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 864 865 /* turn on SUVD clock gating */ 866 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 867 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 868 869 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 870 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 871 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 872 } 873 874 /** 875 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 876 * 877 * @adev: amdgpu_device pointer 878 * @inst: instance number 879 * 880 * Enable clock gating for VCN block 881 */ 882 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 883 { 884 uint32_t data; 885 886 /* enable VCN CGC */ 887 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 888 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 889 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 890 else 891 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 892 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 893 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 894 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 895 896 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 897 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 898 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 899 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 900 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 901 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 902 | UVD_CGC_CTRL__SYS_MODE_MASK 903 | UVD_CGC_CTRL__UDEC_MODE_MASK 904 | UVD_CGC_CTRL__MPEG2_MODE_MASK 905 | UVD_CGC_CTRL__REGS_MODE_MASK 906 | UVD_CGC_CTRL__RBC_MODE_MASK 907 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 908 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 909 | UVD_CGC_CTRL__IDCT_MODE_MASK 910 | UVD_CGC_CTRL__MPRD_MODE_MASK 911 | UVD_CGC_CTRL__MPC_MODE_MASK 912 | UVD_CGC_CTRL__LBSI_MODE_MASK 913 | UVD_CGC_CTRL__LRBBM_MODE_MASK 914 | UVD_CGC_CTRL__WCB_MODE_MASK 915 | UVD_CGC_CTRL__VCPU_MODE_MASK 916 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 917 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 918 919 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 920 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 921 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 922 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 923 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 924 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 925 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 926 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 927 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 928 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 929 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 930 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 931 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 932 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 933 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 934 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 935 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 936 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 937 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 938 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 939 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 940 } 941 942 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 943 { 944 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 945 struct amdgpu_ring *ring; 946 uint32_t rb_bufsz, tmp; 947 948 /* disable register anti-hang mechanism */ 949 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 950 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 951 /* enable dynamic power gating mode */ 952 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 953 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 954 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 955 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 956 957 if (indirect) 958 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 959 960 /* enable clock gating */ 961 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 962 963 /* enable VCPU clock */ 964 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 965 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 966 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 969 970 /* disable master interupt */ 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 973 974 /* setup mmUVD_LMI_CTRL */ 975 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 976 UVD_LMI_CTRL__REQ_MODE_MASK | 977 UVD_LMI_CTRL__CRC_RESET_MASK | 978 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 979 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 980 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 981 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 982 0x00100000L); 983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 984 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 985 986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 987 VCN, inst_idx, mmUVD_MPC_CNTL), 988 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 989 990 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 991 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 992 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 993 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 994 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 995 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 996 997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 998 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 999 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1000 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1001 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1002 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1003 1004 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1005 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1006 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1007 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1008 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1009 1010 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 1011 1012 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1013 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1015 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1016 1017 /* enable LMI MC and UMC channels */ 1018 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1019 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1020 1021 /* unblock VCPU register access */ 1022 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1023 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1024 1025 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1026 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1028 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1029 1030 /* enable master interrupt */ 1031 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1032 VCN, inst_idx, mmUVD_MASTINT_EN), 1033 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1034 1035 /* add nop to workaround PSP size check */ 1036 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1037 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1038 1039 if (indirect) 1040 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 1041 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 1042 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 1043 1044 ring = &adev->vcn.inst[inst_idx].ring_dec; 1045 /* force RBC into idle state */ 1046 rb_bufsz = order_base_2(ring->ring_size); 1047 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1048 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1052 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1053 1054 /* Stall DPG before WPTR/RPTR reset */ 1055 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1056 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1057 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1058 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1059 1060 /* set the write pointer delay */ 1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1062 1063 /* set the wb address */ 1064 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1065 (upper_32_bits(ring->gpu_addr) >> 2)); 1066 1067 /* programm the RB_BASE for ring buffer */ 1068 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1069 lower_32_bits(ring->gpu_addr)); 1070 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1071 upper_32_bits(ring->gpu_addr)); 1072 1073 /* Initialize the ring buffer's read and write pointers */ 1074 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1075 1076 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1077 1078 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1079 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1080 lower_32_bits(ring->wptr)); 1081 1082 /* Reset FW shared memory RBC WPTR/RPTR */ 1083 fw_shared->rb.rptr = 0; 1084 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1085 1086 /*resetting done, fw can check RB ring */ 1087 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1088 1089 /* Unstall DPG */ 1090 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1091 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1092 1093 return 0; 1094 } 1095 1096 static int vcn_v3_0_start(struct amdgpu_device *adev) 1097 { 1098 volatile struct amdgpu_fw_shared *fw_shared; 1099 struct amdgpu_ring *ring; 1100 uint32_t rb_bufsz, tmp; 1101 int i, j, k, r; 1102 1103 if (adev->pm.dpm_enabled) 1104 amdgpu_dpm_enable_uvd(adev, true); 1105 1106 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1107 if (adev->vcn.harvest_config & (1 << i)) 1108 continue; 1109 1110 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1111 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1112 continue; 1113 } 1114 1115 /* disable VCN power gating */ 1116 vcn_v3_0_disable_static_power_gating(adev, i); 1117 1118 /* set VCN status busy */ 1119 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1120 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1121 1122 /*SW clock gating */ 1123 vcn_v3_0_disable_clock_gating(adev, i); 1124 1125 /* enable VCPU clock */ 1126 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1127 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1128 1129 /* disable master interrupt */ 1130 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1131 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1132 1133 /* enable LMI MC and UMC channels */ 1134 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1135 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1136 1137 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1138 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1139 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1140 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1141 1142 /* setup mmUVD_LMI_CTRL */ 1143 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1144 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1145 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1146 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1147 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1148 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1149 1150 /* setup mmUVD_MPC_CNTL */ 1151 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1152 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1153 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1154 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1155 1156 /* setup UVD_MPC_SET_MUXA0 */ 1157 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1158 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1159 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1160 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1161 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1162 1163 /* setup UVD_MPC_SET_MUXB0 */ 1164 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1165 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1166 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1167 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1168 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1169 1170 /* setup mmUVD_MPC_SET_MUX */ 1171 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1172 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1173 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1174 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1175 1176 vcn_v3_0_mc_resume(adev, i); 1177 1178 /* VCN global tiling registers */ 1179 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1180 adev->gfx.config.gb_addr_config); 1181 1182 /* unblock VCPU register access */ 1183 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1184 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1185 1186 /* release VCPU reset to boot */ 1187 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1188 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1189 1190 for (j = 0; j < 10; ++j) { 1191 uint32_t status; 1192 1193 for (k = 0; k < 100; ++k) { 1194 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1195 if (status & 2) 1196 break; 1197 mdelay(10); 1198 } 1199 r = 0; 1200 if (status & 2) 1201 break; 1202 1203 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1204 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1205 UVD_VCPU_CNTL__BLK_RST_MASK, 1206 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1207 mdelay(10); 1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1209 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1210 1211 mdelay(10); 1212 r = -1; 1213 } 1214 1215 if (r) { 1216 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1217 return r; 1218 } 1219 1220 /* enable master interrupt */ 1221 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1222 UVD_MASTINT_EN__VCPU_EN_MASK, 1223 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1224 1225 /* clear the busy bit of VCN_STATUS */ 1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1227 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1228 1229 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1230 1231 ring = &adev->vcn.inst[i].ring_dec; 1232 /* force RBC into idle state */ 1233 rb_bufsz = order_base_2(ring->ring_size); 1234 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1235 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1236 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1237 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1238 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1239 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1240 1241 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr; 1242 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1243 1244 /* programm the RB_BASE for ring buffer */ 1245 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1246 lower_32_bits(ring->gpu_addr)); 1247 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1248 upper_32_bits(ring->gpu_addr)); 1249 1250 /* Initialize the ring buffer's read and write pointers */ 1251 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1252 1253 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1254 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1255 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1256 lower_32_bits(ring->wptr)); 1257 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1258 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1259 1260 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1261 ring = &adev->vcn.inst[i].ring_enc[0]; 1262 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1263 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1264 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1265 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1266 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1267 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1268 1269 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1270 ring = &adev->vcn.inst[i].ring_enc[1]; 1271 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1272 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1273 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1274 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1275 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1276 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1283 { 1284 int i, j; 1285 struct amdgpu_ring *ring; 1286 uint64_t cache_addr; 1287 uint64_t rb_addr; 1288 uint64_t ctx_addr; 1289 uint32_t param, resp, expected; 1290 uint32_t offset, cache_size; 1291 uint32_t tmp, timeout; 1292 uint32_t id; 1293 1294 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1295 uint32_t *table_loc; 1296 uint32_t table_size; 1297 uint32_t size, size_dw; 1298 1299 bool is_vcn_ready; 1300 1301 struct mmsch_v3_0_cmd_direct_write 1302 direct_wt = { {0} }; 1303 struct mmsch_v3_0_cmd_direct_read_modify_write 1304 direct_rd_mod_wt = { {0} }; 1305 struct mmsch_v3_0_cmd_end end = { {0} }; 1306 struct mmsch_v3_0_init_header header; 1307 1308 direct_wt.cmd_header.command_type = 1309 MMSCH_COMMAND__DIRECT_REG_WRITE; 1310 direct_rd_mod_wt.cmd_header.command_type = 1311 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1312 end.cmd_header.command_type = 1313 MMSCH_COMMAND__END; 1314 1315 header.version = MMSCH_VERSION; 1316 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1317 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1318 header.inst[i].init_status = 0; 1319 header.inst[i].table_offset = 0; 1320 header.inst[i].table_size = 0; 1321 } 1322 1323 table_loc = (uint32_t *)table->cpu_addr; 1324 table_loc += header.total_size; 1325 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1326 if (adev->vcn.harvest_config & (1 << i)) 1327 continue; 1328 1329 table_size = 0; 1330 1331 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1332 mmUVD_STATUS), 1333 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1334 1335 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1336 1337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1338 id = amdgpu_ucode_id_vcns[i]; 1339 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1340 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1341 adev->firmware.ucode[id].tmr_mc_addr_lo); 1342 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1343 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1344 adev->firmware.ucode[id].tmr_mc_addr_hi); 1345 offset = 0; 1346 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1347 mmUVD_VCPU_CACHE_OFFSET0), 1348 0); 1349 } else { 1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1351 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1352 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1354 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1355 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1356 offset = cache_size; 1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1358 mmUVD_VCPU_CACHE_OFFSET0), 1359 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1360 } 1361 1362 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1363 mmUVD_VCPU_CACHE_SIZE0), 1364 cache_size); 1365 1366 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1367 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1368 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1369 lower_32_bits(cache_addr)); 1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1371 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1372 upper_32_bits(cache_addr)); 1373 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1374 mmUVD_VCPU_CACHE_OFFSET1), 1375 0); 1376 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1377 mmUVD_VCPU_CACHE_SIZE1), 1378 AMDGPU_VCN_STACK_SIZE); 1379 1380 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1381 AMDGPU_VCN_STACK_SIZE; 1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1383 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1384 lower_32_bits(cache_addr)); 1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1386 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1387 upper_32_bits(cache_addr)); 1388 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1389 mmUVD_VCPU_CACHE_OFFSET2), 1390 0); 1391 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1392 mmUVD_VCPU_CACHE_SIZE2), 1393 AMDGPU_VCN_CONTEXT_SIZE); 1394 1395 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1396 ring = &adev->vcn.inst[i].ring_enc[j]; 1397 ring->wptr = 0; 1398 rb_addr = ring->gpu_addr; 1399 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1400 mmUVD_RB_BASE_LO), 1401 lower_32_bits(rb_addr)); 1402 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1403 mmUVD_RB_BASE_HI), 1404 upper_32_bits(rb_addr)); 1405 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1406 mmUVD_RB_SIZE), 1407 ring->ring_size / 4); 1408 } 1409 1410 ring = &adev->vcn.inst[i].ring_dec; 1411 ring->wptr = 0; 1412 rb_addr = ring->gpu_addr; 1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1414 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1415 lower_32_bits(rb_addr)); 1416 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1417 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1418 upper_32_bits(rb_addr)); 1419 /* force RBC into idle state */ 1420 tmp = order_base_2(ring->ring_size); 1421 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1424 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1425 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1426 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1427 mmUVD_RBC_RB_CNTL), 1428 tmp); 1429 1430 /* add end packet */ 1431 MMSCH_V3_0_INSERT_END(); 1432 1433 /* refine header */ 1434 header.inst[i].init_status = 0; 1435 header.inst[i].table_offset = header.total_size; 1436 header.inst[i].table_size = table_size; 1437 header.total_size += table_size; 1438 } 1439 1440 /* Update init table header in memory */ 1441 size = sizeof(struct mmsch_v3_0_init_header); 1442 table_loc = (uint32_t *)table->cpu_addr; 1443 memcpy((void *)table_loc, &header, size); 1444 1445 /* message MMSCH (in VCN[0]) to initialize this client 1446 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1447 * of memory descriptor location 1448 */ 1449 ctx_addr = table->gpu_addr; 1450 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1451 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1452 1453 /* 2, update vmid of descriptor */ 1454 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1455 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1456 /* use domain0 for MM scheduler */ 1457 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1458 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1459 1460 /* 3, notify mmsch about the size of this descriptor */ 1461 size = header.total_size; 1462 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1463 1464 /* 4, set resp to zero */ 1465 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1466 1467 /* 5, kick off the initialization and wait until 1468 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1469 */ 1470 param = 0x10000001; 1471 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1472 tmp = 0; 1473 timeout = 1000; 1474 resp = 0; 1475 expected = param + 1; 1476 while (resp != expected) { 1477 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1478 if (resp == expected) 1479 break; 1480 1481 udelay(10); 1482 tmp = tmp + 10; 1483 if (tmp >= timeout) { 1484 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1485 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1486 "(expected=0x%08x, readback=0x%08x)\n", 1487 tmp, expected, resp); 1488 return -EBUSY; 1489 } 1490 } 1491 1492 /* 6, check each VCN's init_status 1493 * if it remains as 0, then this VCN is not assigned to current VF 1494 * do not start ring for this VCN 1495 */ 1496 size = sizeof(struct mmsch_v3_0_init_header); 1497 table_loc = (uint32_t *)table->cpu_addr; 1498 memcpy(&header, (void *)table_loc, size); 1499 1500 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1501 if (adev->vcn.harvest_config & (1 << i)) 1502 continue; 1503 1504 is_vcn_ready = (header.inst[i].init_status == 1); 1505 if (!is_vcn_ready) 1506 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i); 1507 1508 ring = &adev->vcn.inst[i].ring_dec; 1509 ring->sched.ready = is_vcn_ready; 1510 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1511 ring = &adev->vcn.inst[i].ring_enc[j]; 1512 ring->sched.ready = is_vcn_ready; 1513 } 1514 } 1515 1516 return 0; 1517 } 1518 1519 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1520 { 1521 uint32_t tmp; 1522 1523 /* Wait for power status to be 1 */ 1524 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1525 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1526 1527 /* wait for read ptr to be equal to write ptr */ 1528 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1529 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1530 1531 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1532 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1533 1534 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1535 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1536 1537 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1538 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1539 1540 /* disable dynamic power gating mode */ 1541 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1542 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1543 1544 return 0; 1545 } 1546 1547 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1548 { 1549 uint32_t tmp; 1550 int i, r = 0; 1551 1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1553 if (adev->vcn.harvest_config & (1 << i)) 1554 continue; 1555 1556 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1557 r = vcn_v3_0_stop_dpg_mode(adev, i); 1558 continue; 1559 } 1560 1561 /* wait for vcn idle */ 1562 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1563 if (r) 1564 return r; 1565 1566 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1567 UVD_LMI_STATUS__READ_CLEAN_MASK | 1568 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1569 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1570 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1571 if (r) 1572 return r; 1573 1574 /* disable LMI UMC channel */ 1575 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1576 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1577 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1578 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1579 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1580 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1581 if (r) 1582 return r; 1583 1584 /* block VCPU register access */ 1585 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1586 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1587 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1588 1589 /* reset VCPU */ 1590 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1591 UVD_VCPU_CNTL__BLK_RST_MASK, 1592 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1593 1594 /* disable VCPU clock */ 1595 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1596 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1597 1598 /* apply soft reset */ 1599 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1600 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1601 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1602 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1603 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1604 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1605 1606 /* clear status */ 1607 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1608 1609 /* apply HW clock gating */ 1610 vcn_v3_0_enable_clock_gating(adev, i); 1611 1612 /* enable VCN power gating */ 1613 vcn_v3_0_enable_static_power_gating(adev, i); 1614 } 1615 1616 if (adev->pm.dpm_enabled) 1617 amdgpu_dpm_enable_uvd(adev, false); 1618 1619 return 0; 1620 } 1621 1622 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1623 int inst_idx, struct dpg_pause_state *new_state) 1624 { 1625 volatile struct amdgpu_fw_shared *fw_shared; 1626 struct amdgpu_ring *ring; 1627 uint32_t reg_data = 0; 1628 int ret_code; 1629 1630 /* pause/unpause if state is changed */ 1631 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1632 DRM_DEBUG("dpg pause state changed %d -> %d", 1633 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1634 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1635 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1636 1637 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1638 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1639 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1640 1641 if (!ret_code) { 1642 /* pause DPG */ 1643 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1644 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1645 1646 /* wait for ACK */ 1647 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1648 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1649 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1650 1651 /* Stall DPG before WPTR/RPTR reset */ 1652 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1653 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1654 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1655 1656 /* Restore */ 1657 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr; 1658 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1659 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1660 ring->wptr = 0; 1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1662 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1663 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1664 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1665 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1666 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1667 1668 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1669 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1670 ring->wptr = 0; 1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1672 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1673 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1674 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1675 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1676 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1677 1678 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1679 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1680 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1681 1682 /* Unstall DPG */ 1683 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1684 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1685 1686 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1687 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1688 } 1689 } else { 1690 /* unpause dpg, no need to wait */ 1691 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1692 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1693 } 1694 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1695 } 1696 1697 return 0; 1698 } 1699 1700 /** 1701 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1702 * 1703 * @ring: amdgpu_ring pointer 1704 * 1705 * Returns the current hardware read pointer 1706 */ 1707 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1708 { 1709 struct amdgpu_device *adev = ring->adev; 1710 1711 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1712 } 1713 1714 /** 1715 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1716 * 1717 * @ring: amdgpu_ring pointer 1718 * 1719 * Returns the current hardware write pointer 1720 */ 1721 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1722 { 1723 struct amdgpu_device *adev = ring->adev; 1724 1725 if (ring->use_doorbell) 1726 return adev->wb.wb[ring->wptr_offs]; 1727 else 1728 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1729 } 1730 1731 /** 1732 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1733 * 1734 * @ring: amdgpu_ring pointer 1735 * 1736 * Commits the write pointer to the hardware 1737 */ 1738 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1739 { 1740 struct amdgpu_device *adev = ring->adev; 1741 volatile struct amdgpu_fw_shared *fw_shared; 1742 1743 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1744 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1745 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr; 1746 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1747 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1748 lower_32_bits(ring->wptr)); 1749 } 1750 1751 if (ring->use_doorbell) { 1752 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1753 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1754 } else { 1755 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1756 } 1757 } 1758 1759 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1760 u64 seq, uint32_t flags) 1761 { 1762 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1763 1764 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE); 1765 amdgpu_ring_write(ring, addr); 1766 amdgpu_ring_write(ring, upper_32_bits(addr)); 1767 amdgpu_ring_write(ring, seq); 1768 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP); 1769 } 1770 1771 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring) 1772 { 1773 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END); 1774 } 1775 1776 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, 1777 struct amdgpu_job *job, 1778 struct amdgpu_ib *ib, 1779 uint32_t flags) 1780 { 1781 uint32_t vmid = AMDGPU_JOB_GET_VMID(job); 1782 1783 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB); 1784 amdgpu_ring_write(ring, vmid); 1785 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1786 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1787 amdgpu_ring_write(ring, ib->length_dw); 1788 } 1789 1790 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1791 uint32_t val, uint32_t mask) 1792 { 1793 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT); 1794 amdgpu_ring_write(ring, reg << 2); 1795 amdgpu_ring_write(ring, mask); 1796 amdgpu_ring_write(ring, val); 1797 } 1798 1799 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring, 1800 uint32_t vmid, uint64_t pd_addr) 1801 { 1802 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1803 uint32_t data0, data1, mask; 1804 1805 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1806 1807 /* wait for register write */ 1808 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1809 data1 = lower_32_bits(pd_addr); 1810 mask = 0xffffffff; 1811 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask); 1812 } 1813 1814 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1815 { 1816 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE); 1817 amdgpu_ring_write(ring, reg << 2); 1818 amdgpu_ring_write(ring, val); 1819 } 1820 1821 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1822 .type = AMDGPU_RING_TYPE_VCN_DEC, 1823 .align_mask = 0x3f, 1824 .nop = VCN_DEC_SW_CMD_NO_OP, 1825 .vmhub = AMDGPU_MMHUB_0, 1826 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1827 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1828 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1829 .emit_frame_size = 1830 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1831 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1832 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */ 1833 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */ 1834 1, /* vcn_v3_0_dec_sw_ring_insert_end */ 1835 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */ 1836 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib, 1837 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence, 1838 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush, 1839 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1840 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1841 .insert_nop = amdgpu_ring_insert_nop, 1842 .insert_end = vcn_v3_0_dec_sw_ring_insert_end, 1843 .pad_ib = amdgpu_ring_generic_pad_ib, 1844 .begin_use = amdgpu_vcn_ring_begin_use, 1845 .end_use = amdgpu_vcn_ring_end_use, 1846 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg, 1847 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait, 1848 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1849 }; 1850 1851 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p) 1852 { 1853 struct drm_gpu_scheduler **scheds; 1854 1855 /* The create msg must be in the first IB submitted */ 1856 if (atomic_read(&p->entity->fence_seq)) 1857 return -EINVAL; 1858 1859 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1860 [AMDGPU_RING_PRIO_DEFAULT].sched; 1861 drm_sched_entity_modify_sched(p->entity, scheds, 1); 1862 return 0; 1863 } 1864 1865 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr) 1866 { 1867 struct ttm_operation_ctx ctx = { false, false }; 1868 struct amdgpu_bo_va_mapping *map; 1869 uint32_t *msg, num_buffers; 1870 struct amdgpu_bo *bo; 1871 uint64_t start, end; 1872 unsigned int i; 1873 void * ptr; 1874 int r; 1875 1876 addr &= AMDGPU_GMC_HOLE_MASK; 1877 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1878 if (r) { 1879 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1880 return r; 1881 } 1882 1883 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1884 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1885 if (addr & 0x7) { 1886 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1887 return -EINVAL; 1888 } 1889 1890 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1891 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1892 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1893 if (r) { 1894 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1895 return r; 1896 } 1897 1898 r = amdgpu_bo_kmap(bo, &ptr); 1899 if (r) { 1900 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1901 return r; 1902 } 1903 1904 msg = ptr + addr - start; 1905 1906 /* Check length */ 1907 if (msg[1] > end - addr) { 1908 r = -EINVAL; 1909 goto out; 1910 } 1911 1912 if (msg[3] != RDECODE_MSG_CREATE) 1913 goto out; 1914 1915 num_buffers = msg[2]; 1916 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1917 uint32_t offset, size, *create; 1918 1919 if (msg[0] != RDECODE_MESSAGE_CREATE) 1920 continue; 1921 1922 offset = msg[1]; 1923 size = msg[2]; 1924 1925 if (offset + size > end) { 1926 r = -EINVAL; 1927 goto out; 1928 } 1929 1930 create = ptr + addr + offset - start; 1931 1932 /* H246, HEVC and VP9 can run on any instance */ 1933 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1934 continue; 1935 1936 r = vcn_v3_0_limit_sched(p); 1937 if (r) 1938 goto out; 1939 } 1940 1941 out: 1942 amdgpu_bo_kunmap(bo); 1943 return r; 1944 } 1945 1946 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1947 uint32_t ib_idx) 1948 { 1949 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1950 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1951 uint32_t msg_lo = 0, msg_hi = 0; 1952 unsigned i; 1953 int r; 1954 1955 /* The first instance can decode anything */ 1956 if (!ring->me) 1957 return 0; 1958 1959 for (i = 0; i < ib->length_dw; i += 2) { 1960 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1961 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1); 1962 1963 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1964 msg_lo = val; 1965 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1966 msg_hi = val; 1967 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) && 1968 val == 0) { 1969 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo); 1970 if (r) 1971 return r; 1972 } 1973 } 1974 return 0; 1975 } 1976 1977 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1978 .type = AMDGPU_RING_TYPE_VCN_DEC, 1979 .align_mask = 0xf, 1980 .vmhub = AMDGPU_MMHUB_0, 1981 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1982 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1983 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1984 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 1985 .emit_frame_size = 1986 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1987 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1988 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1989 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1990 6, 1991 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1992 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1993 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1994 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1995 .test_ring = vcn_v2_0_dec_ring_test_ring, 1996 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1997 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1998 .insert_start = vcn_v2_0_dec_ring_insert_start, 1999 .insert_end = vcn_v2_0_dec_ring_insert_end, 2000 .pad_ib = amdgpu_ring_generic_pad_ib, 2001 .begin_use = amdgpu_vcn_ring_begin_use, 2002 .end_use = amdgpu_vcn_ring_end_use, 2003 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2004 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2005 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2006 }; 2007 2008 /** 2009 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2010 * 2011 * @ring: amdgpu_ring pointer 2012 * 2013 * Returns the current hardware enc read pointer 2014 */ 2015 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2016 { 2017 struct amdgpu_device *adev = ring->adev; 2018 2019 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2020 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2021 else 2022 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2023 } 2024 2025 /** 2026 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2027 * 2028 * @ring: amdgpu_ring pointer 2029 * 2030 * Returns the current hardware enc write pointer 2031 */ 2032 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2033 { 2034 struct amdgpu_device *adev = ring->adev; 2035 2036 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2037 if (ring->use_doorbell) 2038 return adev->wb.wb[ring->wptr_offs]; 2039 else 2040 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2041 } else { 2042 if (ring->use_doorbell) 2043 return adev->wb.wb[ring->wptr_offs]; 2044 else 2045 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2046 } 2047 } 2048 2049 /** 2050 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2051 * 2052 * @ring: amdgpu_ring pointer 2053 * 2054 * Commits the enc write pointer to the hardware 2055 */ 2056 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2057 { 2058 struct amdgpu_device *adev = ring->adev; 2059 2060 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2061 if (ring->use_doorbell) { 2062 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2063 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2064 } else { 2065 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2066 } 2067 } else { 2068 if (ring->use_doorbell) { 2069 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 2070 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2071 } else { 2072 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2073 } 2074 } 2075 } 2076 2077 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2078 .type = AMDGPU_RING_TYPE_VCN_ENC, 2079 .align_mask = 0x3f, 2080 .nop = VCN_ENC_CMD_NO_OP, 2081 .vmhub = AMDGPU_MMHUB_0, 2082 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2083 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2084 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2085 .emit_frame_size = 2086 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2087 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2088 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2089 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2090 1, /* vcn_v2_0_enc_ring_insert_end */ 2091 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2092 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2093 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2094 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2095 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2096 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2097 .insert_nop = amdgpu_ring_insert_nop, 2098 .insert_end = vcn_v2_0_enc_ring_insert_end, 2099 .pad_ib = amdgpu_ring_generic_pad_ib, 2100 .begin_use = amdgpu_vcn_ring_begin_use, 2101 .end_use = amdgpu_vcn_ring_end_use, 2102 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2103 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2104 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2105 }; 2106 2107 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2108 { 2109 int i; 2110 2111 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2112 if (adev->vcn.harvest_config & (1 << i)) 2113 continue; 2114 2115 if (!DEC_SW_RING_ENABLED) 2116 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2117 else 2118 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2119 adev->vcn.inst[i].ring_dec.me = i; 2120 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i, 2121 DEC_SW_RING_ENABLED?"(Software Ring)":""); 2122 } 2123 } 2124 2125 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2126 { 2127 int i, j; 2128 2129 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2130 if (adev->vcn.harvest_config & (1 << i)) 2131 continue; 2132 2133 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 2134 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2135 adev->vcn.inst[i].ring_enc[j].me = i; 2136 } 2137 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 2138 } 2139 } 2140 2141 static bool vcn_v3_0_is_idle(void *handle) 2142 { 2143 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2144 int i, ret = 1; 2145 2146 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2147 if (adev->vcn.harvest_config & (1 << i)) 2148 continue; 2149 2150 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2151 } 2152 2153 return ret; 2154 } 2155 2156 static int vcn_v3_0_wait_for_idle(void *handle) 2157 { 2158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2159 int i, ret = 0; 2160 2161 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2162 if (adev->vcn.harvest_config & (1 << i)) 2163 continue; 2164 2165 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2166 UVD_STATUS__IDLE); 2167 if (ret) 2168 return ret; 2169 } 2170 2171 return ret; 2172 } 2173 2174 static int vcn_v3_0_set_clockgating_state(void *handle, 2175 enum amd_clockgating_state state) 2176 { 2177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2178 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 2179 int i; 2180 2181 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2182 if (adev->vcn.harvest_config & (1 << i)) 2183 continue; 2184 2185 if (enable) { 2186 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2187 return -EBUSY; 2188 vcn_v3_0_enable_clock_gating(adev, i); 2189 } else { 2190 vcn_v3_0_disable_clock_gating(adev, i); 2191 } 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int vcn_v3_0_set_powergating_state(void *handle, 2198 enum amd_powergating_state state) 2199 { 2200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2201 int ret; 2202 2203 /* for SRIOV, guest should not control VCN Power-gating 2204 * MMSCH FW should control Power-gating and clock-gating 2205 * guest should avoid touching CGC and PG 2206 */ 2207 if (amdgpu_sriov_vf(adev)) { 2208 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 2209 return 0; 2210 } 2211 2212 if(state == adev->vcn.cur_state) 2213 return 0; 2214 2215 if (state == AMD_PG_STATE_GATE) 2216 ret = vcn_v3_0_stop(adev); 2217 else 2218 ret = vcn_v3_0_start(adev); 2219 2220 if(!ret) 2221 adev->vcn.cur_state = state; 2222 2223 return ret; 2224 } 2225 2226 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2227 struct amdgpu_irq_src *source, 2228 unsigned type, 2229 enum amdgpu_interrupt_state state) 2230 { 2231 return 0; 2232 } 2233 2234 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2235 struct amdgpu_irq_src *source, 2236 struct amdgpu_iv_entry *entry) 2237 { 2238 uint32_t ip_instance; 2239 2240 switch (entry->client_id) { 2241 case SOC15_IH_CLIENTID_VCN: 2242 ip_instance = 0; 2243 break; 2244 case SOC15_IH_CLIENTID_VCN1: 2245 ip_instance = 1; 2246 break; 2247 default: 2248 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2249 return 0; 2250 } 2251 2252 DRM_DEBUG("IH: VCN TRAP\n"); 2253 2254 switch (entry->src_id) { 2255 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2256 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2257 break; 2258 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2259 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2260 break; 2261 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2262 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2263 break; 2264 default: 2265 DRM_ERROR("Unhandled interrupt: %d %d\n", 2266 entry->src_id, entry->src_data[0]); 2267 break; 2268 } 2269 2270 return 0; 2271 } 2272 2273 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2274 .set = vcn_v3_0_set_interrupt_state, 2275 .process = vcn_v3_0_process_interrupt, 2276 }; 2277 2278 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2279 { 2280 int i; 2281 2282 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2283 if (adev->vcn.harvest_config & (1 << i)) 2284 continue; 2285 2286 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 2287 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2288 } 2289 } 2290 2291 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2292 .name = "vcn_v3_0", 2293 .early_init = vcn_v3_0_early_init, 2294 .late_init = NULL, 2295 .sw_init = vcn_v3_0_sw_init, 2296 .sw_fini = vcn_v3_0_sw_fini, 2297 .hw_init = vcn_v3_0_hw_init, 2298 .hw_fini = vcn_v3_0_hw_fini, 2299 .suspend = vcn_v3_0_suspend, 2300 .resume = vcn_v3_0_resume, 2301 .is_idle = vcn_v3_0_is_idle, 2302 .wait_for_idle = vcn_v3_0_wait_for_idle, 2303 .check_soft_reset = NULL, 2304 .pre_soft_reset = NULL, 2305 .soft_reset = NULL, 2306 .post_soft_reset = NULL, 2307 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2308 .set_powergating_state = vcn_v3_0_set_powergating_state, 2309 }; 2310 2311 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 2312 { 2313 .type = AMD_IP_BLOCK_TYPE_VCN, 2314 .major = 3, 2315 .minor = 0, 2316 .rev = 0, 2317 .funcs = &vcn_v3_0_ip_funcs, 2318 }; 2319