1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v3_0.h" 33 #include "vcn_sw_ring.h" 34 35 #include "vcn/vcn_3_0_0_offset.h" 36 #include "vcn/vcn_3_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 44 45 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 46 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 47 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 48 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 49 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 50 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 51 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 52 53 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 55 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 56 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 57 58 #define VCN_INSTANCES_SIENNA_CICHLID 2 59 #define DEC_SW_RING_ENABLED FALSE 60 61 #define RDECODE_MSG_CREATE 0x00000000 62 #define RDECODE_MESSAGE_CREATE 0x00000001 63 64 static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 97 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 98 }; 99 100 static int amdgpu_ih_clientid_vcns[] = { 101 SOC15_IH_CLIENTID_VCN, 102 SOC15_IH_CLIENTID_VCN1 103 }; 104 105 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 106 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 107 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 108 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 109 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 110 enum amd_powergating_state state); 111 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 112 struct dpg_pause_state *new_state); 113 static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst); 114 115 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 116 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 117 118 /** 119 * vcn_v3_0_early_init - set function pointers and load microcode 120 * 121 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 122 * 123 * Set ring and irq function pointers 124 * Load microcode from filesystem 125 */ 126 static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block) 127 { 128 struct amdgpu_device *adev = ip_block->adev; 129 int i, r; 130 131 if (amdgpu_sriov_vf(adev)) { 132 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 133 adev->vcn.harvest_config = 0; 134 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 135 adev->vcn.inst[i].num_enc_rings = 1; 136 137 } else { 138 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 139 AMDGPU_VCN_HARVEST_VCN1)) 140 /* both instances are harvested, disable the block */ 141 return -ENOENT; 142 143 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 144 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 145 IP_VERSION(3, 0, 33)) 146 adev->vcn.inst[i].num_enc_rings = 0; 147 else 148 adev->vcn.inst[i].num_enc_rings = 2; 149 } 150 } 151 152 vcn_v3_0_set_dec_ring_funcs(adev); 153 vcn_v3_0_set_enc_ring_funcs(adev); 154 vcn_v3_0_set_irq_funcs(adev); 155 156 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 157 adev->vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state; 158 159 r = amdgpu_vcn_early_init(adev, i); 160 if (r) 161 return r; 162 } 163 return 0; 164 } 165 166 /** 167 * vcn_v3_0_sw_init - sw init for VCN block 168 * 169 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 170 * 171 * Load firmware and sw initialization 172 */ 173 static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 174 { 175 struct amdgpu_ring *ring; 176 int i, j, r; 177 int vcn_doorbell_index = 0; 178 struct amdgpu_device *adev = ip_block->adev; 179 180 /* 181 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 182 * Formula: 183 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 184 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 185 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 186 */ 187 if (amdgpu_sriov_vf(adev)) { 188 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 189 /* get DWORD offset */ 190 vcn_doorbell_index = vcn_doorbell_index << 1; 191 } 192 193 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 194 volatile struct amdgpu_fw_shared *fw_shared; 195 196 if (adev->vcn.harvest_config & (1 << i)) 197 continue; 198 199 r = amdgpu_vcn_sw_init(adev, i); 200 if (r) 201 return r; 202 203 amdgpu_vcn_setup_ucode(adev, i); 204 205 r = amdgpu_vcn_resume(adev, i); 206 if (r) 207 return r; 208 209 adev->vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 210 adev->vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 211 adev->vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 212 adev->vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 213 adev->vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 214 adev->vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 215 216 adev->vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 217 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 218 adev->vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 219 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 220 adev->vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 221 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 222 adev->vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 223 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 224 adev->vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 225 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 226 227 /* VCN DEC TRAP */ 228 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 229 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 230 if (r) 231 return r; 232 233 atomic_set(&adev->vcn.inst[i].sched_score, 0); 234 235 ring = &adev->vcn.inst[i].ring_dec; 236 ring->use_doorbell = true; 237 if (amdgpu_sriov_vf(adev)) { 238 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1); 239 } else { 240 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 241 } 242 ring->vm_hub = AMDGPU_MMHUB0(0); 243 sprintf(ring->name, "vcn_dec_%d", i); 244 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 245 AMDGPU_RING_PRIO_DEFAULT, 246 &adev->vcn.inst[i].sched_score); 247 if (r) 248 return r; 249 250 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 251 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 252 253 /* VCN ENC TRAP */ 254 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 255 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 256 if (r) 257 return r; 258 259 ring = &adev->vcn.inst[i].ring_enc[j]; 260 ring->use_doorbell = true; 261 if (amdgpu_sriov_vf(adev)) { 262 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1) + 1 + j; 263 } else { 264 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 265 } 266 ring->vm_hub = AMDGPU_MMHUB0(0); 267 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 268 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 269 hw_prio, &adev->vcn.inst[i].sched_score); 270 if (r) 271 return r; 272 } 273 274 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 275 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 276 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 277 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 278 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 279 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 280 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) 281 fw_shared->smu_interface_info.smu_interface_type = 2; 282 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 283 IP_VERSION(3, 1, 1)) 284 fw_shared->smu_interface_info.smu_interface_type = 1; 285 286 if (amdgpu_vcnfw_log) 287 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 288 289 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 290 adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 291 adev->vcn.inst[i].reset = vcn_v3_0_reset; 292 } 293 294 adev->vcn.supported_reset = 295 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 296 if (!amdgpu_sriov_vf(adev)) 297 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 298 299 if (amdgpu_sriov_vf(adev)) { 300 r = amdgpu_virt_alloc_mm_table(adev); 301 if (r) 302 return r; 303 } 304 305 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_3_0, ARRAY_SIZE(vcn_reg_list_3_0)); 306 if (r) 307 return r; 308 309 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 310 if (r) 311 return r; 312 313 return 0; 314 } 315 316 /** 317 * vcn_v3_0_sw_fini - sw fini for VCN block 318 * 319 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 320 * 321 * VCN suspend and free up sw allocation 322 */ 323 static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 324 { 325 struct amdgpu_device *adev = ip_block->adev; 326 int i, r, idx; 327 328 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 329 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 330 volatile struct amdgpu_fw_shared *fw_shared; 331 332 if (adev->vcn.harvest_config & (1 << i)) 333 continue; 334 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 335 fw_shared->present_flag_0 = 0; 336 fw_shared->sw_ring.is_enabled = false; 337 } 338 339 drm_dev_exit(idx); 340 } 341 342 if (amdgpu_sriov_vf(adev)) 343 amdgpu_virt_free_mm_table(adev); 344 345 amdgpu_vcn_sysfs_reset_mask_fini(adev); 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 348 r = amdgpu_vcn_suspend(adev, i); 349 if (r) 350 return r; 351 352 r = amdgpu_vcn_sw_fini(adev, i); 353 if (r) 354 return r; 355 } 356 357 return 0; 358 } 359 360 /** 361 * vcn_v3_0_hw_init - start and test VCN block 362 * 363 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 364 * 365 * Initialize the hardware, boot up the VCPU and do some testing 366 */ 367 static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 368 { 369 struct amdgpu_device *adev = ip_block->adev; 370 struct amdgpu_ring *ring; 371 int i, j, r; 372 373 if (amdgpu_sriov_vf(adev)) { 374 r = vcn_v3_0_start_sriov(adev); 375 if (r) 376 return r; 377 378 /* initialize VCN dec and enc ring buffers */ 379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 380 if (adev->vcn.harvest_config & (1 << i)) 381 continue; 382 383 ring = &adev->vcn.inst[i].ring_dec; 384 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 385 ring->sched.ready = false; 386 ring->no_scheduler = true; 387 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 388 } else { 389 ring->wptr = 0; 390 ring->wptr_old = 0; 391 vcn_v3_0_dec_ring_set_wptr(ring); 392 ring->sched.ready = true; 393 } 394 395 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 396 ring = &adev->vcn.inst[i].ring_enc[j]; 397 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 398 ring->sched.ready = false; 399 ring->no_scheduler = true; 400 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 401 } else { 402 ring->wptr = 0; 403 ring->wptr_old = 0; 404 vcn_v3_0_enc_ring_set_wptr(ring); 405 ring->sched.ready = true; 406 } 407 } 408 } 409 } else { 410 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 411 if (adev->vcn.harvest_config & (1 << i)) 412 continue; 413 414 ring = &adev->vcn.inst[i].ring_dec; 415 416 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 417 ring->doorbell_index, i); 418 419 r = amdgpu_ring_test_helper(ring); 420 if (r) 421 return r; 422 423 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 424 ring = &adev->vcn.inst[i].ring_enc[j]; 425 r = amdgpu_ring_test_helper(ring); 426 if (r) 427 return r; 428 } 429 } 430 } 431 432 return 0; 433 } 434 435 /** 436 * vcn_v3_0_hw_fini - stop the hardware block 437 * 438 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 439 * 440 * Stop the VCN block, mark ring as not ready any more 441 */ 442 static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 443 { 444 struct amdgpu_device *adev = ip_block->adev; 445 int i; 446 447 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 448 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 449 450 if (adev->vcn.harvest_config & (1 << i)) 451 continue; 452 453 cancel_delayed_work_sync(&vinst->idle_work); 454 455 if (!amdgpu_sriov_vf(adev)) { 456 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 457 (vinst->cur_state != AMD_PG_STATE_GATE && 458 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 459 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 460 } 461 } 462 } 463 464 return 0; 465 } 466 467 /** 468 * vcn_v3_0_suspend - suspend VCN block 469 * 470 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 471 * 472 * HW fini and suspend VCN block 473 */ 474 static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) 475 { 476 struct amdgpu_device *adev = ip_block->adev; 477 int r, i; 478 479 r = vcn_v3_0_hw_fini(ip_block); 480 if (r) 481 return r; 482 483 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 484 r = amdgpu_vcn_suspend(ip_block->adev, i); 485 if (r) 486 return r; 487 } 488 489 return 0; 490 } 491 492 /** 493 * vcn_v3_0_resume - resume VCN block 494 * 495 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 496 * 497 * Resume firmware and hw init VCN block 498 */ 499 static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block) 500 { 501 struct amdgpu_device *adev = ip_block->adev; 502 int r, i; 503 504 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 505 r = amdgpu_vcn_resume(ip_block->adev, i); 506 if (r) 507 return r; 508 } 509 510 r = vcn_v3_0_hw_init(ip_block); 511 512 return r; 513 } 514 515 /** 516 * vcn_v3_0_mc_resume - memory controller programming 517 * 518 * @vinst: VCN instance 519 * 520 * Let the VCN memory controller know it's offsets 521 */ 522 static void vcn_v3_0_mc_resume(struct amdgpu_vcn_inst *vinst) 523 { 524 struct amdgpu_device *adev = vinst->adev; 525 int inst = vinst->inst; 526 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4); 527 uint32_t offset; 528 529 /* cache window 0: fw */ 530 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 531 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 532 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 533 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 534 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 535 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 536 offset = 0; 537 } else { 538 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 539 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 540 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 541 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 542 offset = size; 543 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 544 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 545 } 546 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 547 548 /* cache window 1: stack */ 549 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 550 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 551 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 552 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 553 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 554 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 555 556 /* cache window 2: context */ 557 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 558 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 559 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 560 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 561 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 562 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 563 564 /* non-cache window */ 565 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 566 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 567 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 568 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 569 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 570 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 571 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 572 } 573 574 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 575 bool indirect) 576 { 577 struct amdgpu_device *adev = vinst->adev; 578 int inst_idx = vinst->inst; 579 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); 580 uint32_t offset; 581 582 /* cache window 0: fw */ 583 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 584 if (!indirect) { 585 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 586 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 587 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 590 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 591 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 592 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 593 } else { 594 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 595 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 596 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 597 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 599 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 600 } 601 offset = 0; 602 } else { 603 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 604 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 605 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 606 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 607 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 608 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 609 offset = size; 610 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 611 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 612 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 613 } 614 615 if (!indirect) 616 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 617 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 618 else 619 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 620 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 621 622 /* cache window 1: stack */ 623 if (!indirect) { 624 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 625 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 626 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 627 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 628 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 629 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 630 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 631 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 632 } else { 633 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 634 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 635 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 636 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 637 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 638 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 639 } 640 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 641 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 642 643 /* cache window 2: context */ 644 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 645 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 646 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 647 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 648 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 649 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 650 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 651 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 652 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 653 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 654 655 /* non-cache window */ 656 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 657 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 658 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 659 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 660 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 661 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 662 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 663 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 664 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 665 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 666 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 667 668 /* VCN global tiling registers */ 669 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 670 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 671 } 672 673 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 674 { 675 struct amdgpu_device *adev = vinst->adev; 676 int inst = vinst->inst; 677 uint32_t data = 0; 678 679 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 680 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 681 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 682 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 686 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 687 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 689 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 692 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 694 695 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 696 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 697 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 698 } else { 699 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 700 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 709 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 710 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 713 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 714 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 715 } 716 717 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 718 data &= ~0x103; 719 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 720 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 721 UVD_POWER_STATUS__UVD_PG_EN_MASK; 722 723 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 724 } 725 726 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 727 { 728 struct amdgpu_device *adev = vinst->adev; 729 int inst = vinst->inst; 730 uint32_t data; 731 732 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 733 /* Before power off, this indicator has to be turned on */ 734 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 735 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 736 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 737 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 738 739 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 740 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 747 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 748 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 749 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 752 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 753 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 754 755 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 756 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 761 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 762 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 763 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 766 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 767 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 768 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 769 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 770 } 771 } 772 773 /** 774 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 775 * 776 * @vinst: Pointer to the VCN instance structure 777 * 778 * Disable clock gating for VCN block 779 */ 780 static void vcn_v3_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 781 { 782 struct amdgpu_device *adev = vinst->adev; 783 int inst = vinst->inst; 784 uint32_t data; 785 786 /* VCN disable CGC */ 787 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 788 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 789 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 790 else 791 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 792 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 793 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 794 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 795 796 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 797 data &= ~(UVD_CGC_GATE__SYS_MASK 798 | UVD_CGC_GATE__UDEC_MASK 799 | UVD_CGC_GATE__MPEG2_MASK 800 | UVD_CGC_GATE__REGS_MASK 801 | UVD_CGC_GATE__RBC_MASK 802 | UVD_CGC_GATE__LMI_MC_MASK 803 | UVD_CGC_GATE__LMI_UMC_MASK 804 | UVD_CGC_GATE__IDCT_MASK 805 | UVD_CGC_GATE__MPRD_MASK 806 | UVD_CGC_GATE__MPC_MASK 807 | UVD_CGC_GATE__LBSI_MASK 808 | UVD_CGC_GATE__LRBBM_MASK 809 | UVD_CGC_GATE__UDEC_RE_MASK 810 | UVD_CGC_GATE__UDEC_CM_MASK 811 | UVD_CGC_GATE__UDEC_IT_MASK 812 | UVD_CGC_GATE__UDEC_DB_MASK 813 | UVD_CGC_GATE__UDEC_MP_MASK 814 | UVD_CGC_GATE__WCB_MASK 815 | UVD_CGC_GATE__VCPU_MASK 816 | UVD_CGC_GATE__MMSCH_MASK); 817 818 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 819 820 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 821 822 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 823 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 824 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 825 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 826 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 827 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 828 | UVD_CGC_CTRL__SYS_MODE_MASK 829 | UVD_CGC_CTRL__UDEC_MODE_MASK 830 | UVD_CGC_CTRL__MPEG2_MODE_MASK 831 | UVD_CGC_CTRL__REGS_MODE_MASK 832 | UVD_CGC_CTRL__RBC_MODE_MASK 833 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 834 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 835 | UVD_CGC_CTRL__IDCT_MODE_MASK 836 | UVD_CGC_CTRL__MPRD_MODE_MASK 837 | UVD_CGC_CTRL__MPC_MODE_MASK 838 | UVD_CGC_CTRL__LBSI_MODE_MASK 839 | UVD_CGC_CTRL__LRBBM_MODE_MASK 840 | UVD_CGC_CTRL__WCB_MODE_MASK 841 | UVD_CGC_CTRL__VCPU_MODE_MASK 842 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 843 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 844 845 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 846 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 847 | UVD_SUVD_CGC_GATE__SIT_MASK 848 | UVD_SUVD_CGC_GATE__SMP_MASK 849 | UVD_SUVD_CGC_GATE__SCM_MASK 850 | UVD_SUVD_CGC_GATE__SDB_MASK 851 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 852 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 853 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 854 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 855 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 856 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 857 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 858 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 859 | UVD_SUVD_CGC_GATE__SCLR_MASK 860 | UVD_SUVD_CGC_GATE__ENT_MASK 861 | UVD_SUVD_CGC_GATE__IME_MASK 862 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 863 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 864 | UVD_SUVD_CGC_GATE__SITE_MASK 865 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 866 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 867 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 868 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 869 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 870 | UVD_SUVD_CGC_GATE__EFC_MASK 871 | UVD_SUVD_CGC_GATE__SAOE_MASK 872 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 873 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 874 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 875 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 876 | UVD_SUVD_CGC_GATE__SMPA_MASK); 877 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 878 879 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 880 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 881 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 882 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 883 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 884 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 885 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 886 887 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 888 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 897 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 898 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 899 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 900 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 901 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 902 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 903 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 904 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 905 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 906 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 907 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 908 } 909 910 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 911 uint8_t sram_sel, 912 uint8_t indirect) 913 { 914 struct amdgpu_device *adev = vinst->adev; 915 int inst_idx = vinst->inst; 916 uint32_t reg_data = 0; 917 918 /* enable sw clock gating control */ 919 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 920 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 921 else 922 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 923 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 924 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 925 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 926 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 927 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 928 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 929 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 930 UVD_CGC_CTRL__SYS_MODE_MASK | 931 UVD_CGC_CTRL__UDEC_MODE_MASK | 932 UVD_CGC_CTRL__MPEG2_MODE_MASK | 933 UVD_CGC_CTRL__REGS_MODE_MASK | 934 UVD_CGC_CTRL__RBC_MODE_MASK | 935 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 936 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 937 UVD_CGC_CTRL__IDCT_MODE_MASK | 938 UVD_CGC_CTRL__MPRD_MODE_MASK | 939 UVD_CGC_CTRL__MPC_MODE_MASK | 940 UVD_CGC_CTRL__LBSI_MODE_MASK | 941 UVD_CGC_CTRL__LRBBM_MODE_MASK | 942 UVD_CGC_CTRL__WCB_MODE_MASK | 943 UVD_CGC_CTRL__VCPU_MODE_MASK | 944 UVD_CGC_CTRL__MMSCH_MODE_MASK); 945 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 946 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 947 948 /* turn off clock gating */ 949 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 950 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 951 952 /* turn on SUVD clock gating */ 953 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 954 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 955 956 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 959 } 960 961 /** 962 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 963 * 964 * @vinst: Pointer to the VCN instance structure 965 * 966 * Enable clock gating for VCN block 967 */ 968 static void vcn_v3_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 969 { 970 struct amdgpu_device *adev = vinst->adev; 971 int inst = vinst->inst; 972 uint32_t data; 973 974 /* enable VCN CGC */ 975 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 976 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 977 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 978 else 979 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 980 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 981 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 982 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 983 984 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 985 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 986 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 987 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 988 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 989 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 990 | UVD_CGC_CTRL__SYS_MODE_MASK 991 | UVD_CGC_CTRL__UDEC_MODE_MASK 992 | UVD_CGC_CTRL__MPEG2_MODE_MASK 993 | UVD_CGC_CTRL__REGS_MODE_MASK 994 | UVD_CGC_CTRL__RBC_MODE_MASK 995 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 996 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 997 | UVD_CGC_CTRL__IDCT_MODE_MASK 998 | UVD_CGC_CTRL__MPRD_MODE_MASK 999 | UVD_CGC_CTRL__MPC_MODE_MASK 1000 | UVD_CGC_CTRL__LBSI_MODE_MASK 1001 | UVD_CGC_CTRL__LRBBM_MODE_MASK 1002 | UVD_CGC_CTRL__WCB_MODE_MASK 1003 | UVD_CGC_CTRL__VCPU_MODE_MASK 1004 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 1005 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 1006 1007 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 1008 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 1009 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 1010 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 1011 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 1012 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 1013 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 1014 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 1015 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 1016 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 1017 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 1018 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 1019 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 1020 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 1021 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 1022 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 1023 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 1024 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 1025 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 1026 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 1027 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 1028 } 1029 1030 static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 1031 { 1032 struct amdgpu_device *adev = vinst->adev; 1033 int inst_idx = vinst->inst; 1034 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1035 struct amdgpu_ring *ring; 1036 uint32_t rb_bufsz, tmp; 1037 int ret; 1038 1039 /* disable register anti-hang mechanism */ 1040 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 1041 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1042 /* enable dynamic power gating mode */ 1043 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 1044 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1045 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1046 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 1047 1048 if (indirect) 1049 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1050 1051 /* enable clock gating */ 1052 vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect); 1053 1054 /* enable VCPU clock */ 1055 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1056 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1057 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 1058 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1059 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1060 1061 /* disable master interupt */ 1062 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1063 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 1064 1065 /* setup mmUVD_LMI_CTRL */ 1066 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1067 UVD_LMI_CTRL__REQ_MODE_MASK | 1068 UVD_LMI_CTRL__CRC_RESET_MASK | 1069 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1070 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1071 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1072 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1073 0x00100000L); 1074 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1075 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 1076 1077 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1078 VCN, inst_idx, mmUVD_MPC_CNTL), 1079 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1080 1081 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1082 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1083 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1084 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1085 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1086 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1087 1088 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1089 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1090 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1091 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1092 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1093 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1094 1095 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1096 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1097 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1098 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1099 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1100 1101 vcn_v3_0_mc_resume_dpg_mode(vinst, indirect); 1102 1103 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1104 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1105 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1106 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1107 1108 /* enable LMI MC and UMC channels */ 1109 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1110 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1111 1112 /* unblock VCPU register access */ 1113 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1114 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1115 1116 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1117 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1118 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1119 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1120 1121 /* enable master interrupt */ 1122 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1123 VCN, inst_idx, mmUVD_MASTINT_EN), 1124 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1125 1126 /* add nop to workaround PSP size check */ 1127 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1128 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1129 1130 if (indirect) { 1131 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1132 if (ret) { 1133 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 1134 return ret; 1135 } 1136 } 1137 1138 ring = &adev->vcn.inst[inst_idx].ring_dec; 1139 /* force RBC into idle state */ 1140 rb_bufsz = order_base_2(ring->ring_size); 1141 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1142 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1143 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1144 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1145 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1146 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1147 1148 /* Stall DPG before WPTR/RPTR reset */ 1149 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1150 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1151 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1152 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1153 1154 /* set the write pointer delay */ 1155 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1156 1157 /* set the wb address */ 1158 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1159 (upper_32_bits(ring->gpu_addr) >> 2)); 1160 1161 /* programm the RB_BASE for ring buffer */ 1162 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1163 lower_32_bits(ring->gpu_addr)); 1164 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1165 upper_32_bits(ring->gpu_addr)); 1166 1167 /* Initialize the ring buffer's read and write pointers */ 1168 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1169 1170 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1171 1172 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1173 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1174 lower_32_bits(ring->wptr)); 1175 1176 /* Reset FW shared memory RBC WPTR/RPTR */ 1177 fw_shared->rb.rptr = 0; 1178 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1179 1180 /*resetting done, fw can check RB ring */ 1181 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1182 1183 /* Unstall DPG */ 1184 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1185 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1186 1187 /* Keeping one read-back to ensure all register writes are done, 1188 * otherwise it may introduce race conditions. 1189 */ 1190 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1191 1192 return 0; 1193 } 1194 1195 static int vcn_v3_0_start(struct amdgpu_vcn_inst *vinst) 1196 { 1197 struct amdgpu_device *adev = vinst->adev; 1198 int i = vinst->inst; 1199 volatile struct amdgpu_fw_shared *fw_shared; 1200 struct amdgpu_ring *ring; 1201 uint32_t rb_bufsz, tmp; 1202 int j, k, r; 1203 1204 if (adev->vcn.harvest_config & (1 << i)) 1205 return 0; 1206 1207 if (adev->pm.dpm_enabled) 1208 amdgpu_dpm_enable_vcn(adev, true, i); 1209 1210 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1211 return vcn_v3_0_start_dpg_mode(vinst, vinst->indirect_sram); 1212 1213 /* disable VCN power gating */ 1214 vcn_v3_0_disable_static_power_gating(vinst); 1215 1216 /* set VCN status busy */ 1217 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1218 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1219 1220 /* SW clock gating */ 1221 vcn_v3_0_disable_clock_gating(vinst); 1222 1223 /* enable VCPU clock */ 1224 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1225 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1226 1227 /* disable master interrupt */ 1228 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1229 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1230 1231 /* enable LMI MC and UMC channels */ 1232 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1233 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1234 1235 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1236 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1237 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1238 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1239 1240 /* setup mmUVD_LMI_CTRL */ 1241 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1242 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1243 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1244 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1245 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1246 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1247 1248 /* setup mmUVD_MPC_CNTL */ 1249 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1250 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1251 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1252 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1253 1254 /* setup UVD_MPC_SET_MUXA0 */ 1255 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1256 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1257 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1258 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1259 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1260 1261 /* setup UVD_MPC_SET_MUXB0 */ 1262 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1263 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1264 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1265 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1266 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1267 1268 /* setup mmUVD_MPC_SET_MUX */ 1269 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1270 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1271 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1272 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1273 1274 vcn_v3_0_mc_resume(vinst); 1275 1276 /* VCN global tiling registers */ 1277 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1278 adev->gfx.config.gb_addr_config); 1279 1280 /* unblock VCPU register access */ 1281 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1282 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1283 1284 /* release VCPU reset to boot */ 1285 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1286 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1287 1288 for (j = 0; j < 10; ++j) { 1289 uint32_t status; 1290 1291 for (k = 0; k < 100; ++k) { 1292 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1293 if (status & 2) 1294 break; 1295 mdelay(10); 1296 } 1297 r = 0; 1298 if (status & 2) 1299 break; 1300 1301 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1302 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1303 UVD_VCPU_CNTL__BLK_RST_MASK, 1304 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1305 mdelay(10); 1306 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1307 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1308 1309 mdelay(10); 1310 r = -1; 1311 } 1312 1313 if (r) { 1314 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1315 return r; 1316 } 1317 1318 /* enable master interrupt */ 1319 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1320 UVD_MASTINT_EN__VCPU_EN_MASK, 1321 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1322 1323 /* clear the busy bit of VCN_STATUS */ 1324 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1325 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1326 1327 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1328 1329 ring = &adev->vcn.inst[i].ring_dec; 1330 /* force RBC into idle state */ 1331 rb_bufsz = order_base_2(ring->ring_size); 1332 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1333 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1334 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1335 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1336 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1337 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1338 1339 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1340 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1341 1342 /* programm the RB_BASE for ring buffer */ 1343 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1344 lower_32_bits(ring->gpu_addr)); 1345 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1346 upper_32_bits(ring->gpu_addr)); 1347 1348 /* Initialize the ring buffer's read and write pointers */ 1349 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1350 1351 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1352 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1353 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1354 lower_32_bits(ring->wptr)); 1355 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1356 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1357 1358 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1359 IP_VERSION(3, 0, 33)) { 1360 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1361 ring = &adev->vcn.inst[i].ring_enc[0]; 1362 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1363 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1364 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1365 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1366 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1367 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1368 1369 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1370 ring = &adev->vcn.inst[i].ring_enc[1]; 1371 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1372 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1373 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1374 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1375 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1376 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1377 } 1378 1379 /* Keeping one read-back to ensure all register writes are done, 1380 * otherwise it may introduce race conditions. 1381 */ 1382 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1383 1384 return 0; 1385 } 1386 1387 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1388 { 1389 int i, j; 1390 struct amdgpu_ring *ring; 1391 uint64_t cache_addr; 1392 uint64_t rb_addr; 1393 uint64_t ctx_addr; 1394 uint32_t param, resp, expected; 1395 uint32_t offset, cache_size; 1396 uint32_t tmp, timeout; 1397 1398 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1399 uint32_t *table_loc; 1400 uint32_t table_size; 1401 uint32_t size, size_dw; 1402 1403 struct mmsch_v3_0_cmd_direct_write 1404 direct_wt = { {0} }; 1405 struct mmsch_v3_0_cmd_direct_read_modify_write 1406 direct_rd_mod_wt = { {0} }; 1407 struct mmsch_v3_0_cmd_end end = { {0} }; 1408 struct mmsch_v3_0_init_header header; 1409 1410 direct_wt.cmd_header.command_type = 1411 MMSCH_COMMAND__DIRECT_REG_WRITE; 1412 direct_rd_mod_wt.cmd_header.command_type = 1413 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1414 end.cmd_header.command_type = 1415 MMSCH_COMMAND__END; 1416 1417 header.version = MMSCH_VERSION; 1418 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1419 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) { 1420 header.inst[i].init_status = 0; 1421 header.inst[i].table_offset = 0; 1422 header.inst[i].table_size = 0; 1423 } 1424 1425 table_loc = (uint32_t *)table->cpu_addr; 1426 table_loc += header.total_size; 1427 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1428 if (adev->vcn.harvest_config & (1 << i)) 1429 continue; 1430 1431 table_size = 0; 1432 1433 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1434 mmUVD_STATUS), 1435 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1436 1437 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1438 1439 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1440 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1441 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1442 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1443 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1444 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1445 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1446 offset = 0; 1447 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1448 mmUVD_VCPU_CACHE_OFFSET0), 1449 0); 1450 } else { 1451 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1452 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1453 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1454 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1455 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1456 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1457 offset = cache_size; 1458 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1459 mmUVD_VCPU_CACHE_OFFSET0), 1460 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1461 } 1462 1463 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1464 mmUVD_VCPU_CACHE_SIZE0), 1465 cache_size); 1466 1467 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1468 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1469 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1470 lower_32_bits(cache_addr)); 1471 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1472 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1473 upper_32_bits(cache_addr)); 1474 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1475 mmUVD_VCPU_CACHE_OFFSET1), 1476 0); 1477 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1478 mmUVD_VCPU_CACHE_SIZE1), 1479 AMDGPU_VCN_STACK_SIZE); 1480 1481 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1482 AMDGPU_VCN_STACK_SIZE; 1483 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1484 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1485 lower_32_bits(cache_addr)); 1486 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1487 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1488 upper_32_bits(cache_addr)); 1489 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1490 mmUVD_VCPU_CACHE_OFFSET2), 1491 0); 1492 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1493 mmUVD_VCPU_CACHE_SIZE2), 1494 AMDGPU_VCN_CONTEXT_SIZE); 1495 1496 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 1497 ring = &adev->vcn.inst[i].ring_enc[j]; 1498 ring->wptr = 0; 1499 rb_addr = ring->gpu_addr; 1500 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1501 mmUVD_RB_BASE_LO), 1502 lower_32_bits(rb_addr)); 1503 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1504 mmUVD_RB_BASE_HI), 1505 upper_32_bits(rb_addr)); 1506 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1507 mmUVD_RB_SIZE), 1508 ring->ring_size / 4); 1509 } 1510 1511 ring = &adev->vcn.inst[i].ring_dec; 1512 ring->wptr = 0; 1513 rb_addr = ring->gpu_addr; 1514 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1515 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1516 lower_32_bits(rb_addr)); 1517 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1518 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1519 upper_32_bits(rb_addr)); 1520 /* force RBC into idle state */ 1521 tmp = order_base_2(ring->ring_size); 1522 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1523 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1524 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1525 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1526 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1527 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1528 mmUVD_RBC_RB_CNTL), 1529 tmp); 1530 1531 /* add end packet */ 1532 MMSCH_V3_0_INSERT_END(); 1533 1534 /* refine header */ 1535 header.inst[i].init_status = 0; 1536 header.inst[i].table_offset = header.total_size; 1537 header.inst[i].table_size = table_size; 1538 header.total_size += table_size; 1539 } 1540 1541 /* Update init table header in memory */ 1542 size = sizeof(struct mmsch_v3_0_init_header); 1543 table_loc = (uint32_t *)table->cpu_addr; 1544 memcpy((void *)table_loc, &header, size); 1545 1546 /* message MMSCH (in VCN[0]) to initialize this client 1547 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1548 * of memory descriptor location 1549 */ 1550 ctx_addr = table->gpu_addr; 1551 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1552 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1553 1554 /* 2, update vmid of descriptor */ 1555 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1556 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1557 /* use domain0 for MM scheduler */ 1558 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1559 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1560 1561 /* 3, notify mmsch about the size of this descriptor */ 1562 size = header.total_size; 1563 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1564 1565 /* 4, set resp to zero */ 1566 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1567 1568 /* 5, kick off the initialization and wait until 1569 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1570 */ 1571 param = 0x10000001; 1572 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1573 tmp = 0; 1574 timeout = 1000; 1575 resp = 0; 1576 expected = param + 1; 1577 while (resp != expected) { 1578 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1579 if (resp == expected) 1580 break; 1581 1582 udelay(10); 1583 tmp = tmp + 10; 1584 if (tmp >= timeout) { 1585 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1586 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1587 "(expected=0x%08x, readback=0x%08x)\n", 1588 tmp, expected, resp); 1589 return -EBUSY; 1590 } 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1597 { 1598 struct amdgpu_device *adev = vinst->adev; 1599 int inst_idx = vinst->inst; 1600 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1601 uint32_t tmp; 1602 1603 vcn_v3_0_pause_dpg_mode(vinst, &state); 1604 1605 /* Wait for power status to be 1 */ 1606 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1607 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1608 1609 /* wait for read ptr to be equal to write ptr */ 1610 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1611 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1612 1613 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1614 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1615 1616 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1617 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1618 1619 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1620 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1621 1622 /* disable dynamic power gating mode */ 1623 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1624 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1625 1626 /* Keeping one read-back to ensure all register writes are done, 1627 * otherwise it may introduce race conditions. 1628 */ 1629 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1630 1631 return 0; 1632 } 1633 1634 static int vcn_v3_0_stop(struct amdgpu_vcn_inst *vinst) 1635 { 1636 struct amdgpu_device *adev = vinst->adev; 1637 int i = vinst->inst; 1638 uint32_t tmp; 1639 int r = 0; 1640 1641 if (adev->vcn.harvest_config & (1 << i)) 1642 return 0; 1643 1644 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1645 r = vcn_v3_0_stop_dpg_mode(vinst); 1646 goto done; 1647 } 1648 1649 /* wait for vcn idle */ 1650 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1651 if (r) 1652 goto done; 1653 1654 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1655 UVD_LMI_STATUS__READ_CLEAN_MASK | 1656 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1657 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1658 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1659 if (r) 1660 goto done; 1661 1662 /* disable LMI UMC channel */ 1663 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1664 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1665 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1666 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1667 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1668 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1669 if (r) 1670 goto done; 1671 1672 /* block VCPU register access */ 1673 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1674 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1675 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1676 1677 /* reset VCPU */ 1678 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1679 UVD_VCPU_CNTL__BLK_RST_MASK, 1680 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1681 1682 /* disable VCPU clock */ 1683 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1684 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1685 1686 /* apply soft reset */ 1687 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1688 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1689 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1690 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1691 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1692 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1693 1694 /* clear status */ 1695 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1696 1697 /* apply HW clock gating */ 1698 vcn_v3_0_enable_clock_gating(vinst); 1699 1700 /* enable VCN power gating */ 1701 vcn_v3_0_enable_static_power_gating(vinst); 1702 1703 /* Keeping one read-back to ensure all register writes are done, 1704 * otherwise it may introduce race conditions. 1705 */ 1706 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1707 1708 done: 1709 if (adev->pm.dpm_enabled) 1710 amdgpu_dpm_enable_vcn(adev, false, i); 1711 1712 return r; 1713 } 1714 1715 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1716 struct dpg_pause_state *new_state) 1717 { 1718 struct amdgpu_device *adev = vinst->adev; 1719 int inst_idx = vinst->inst; 1720 volatile struct amdgpu_fw_shared *fw_shared; 1721 struct amdgpu_ring *ring; 1722 uint32_t reg_data = 0; 1723 int ret_code; 1724 1725 /* pause/unpause if state is changed */ 1726 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1727 DRM_DEBUG("dpg pause state changed %d -> %d", 1728 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1729 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1730 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1731 1732 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1733 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1734 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1735 1736 if (!ret_code) { 1737 /* pause DPG */ 1738 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1739 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1740 1741 /* wait for ACK */ 1742 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1743 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1744 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1745 1746 /* Stall DPG before WPTR/RPTR reset */ 1747 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1748 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1749 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1750 1751 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1752 IP_VERSION(3, 0, 33)) { 1753 /* Restore */ 1754 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1755 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1756 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1757 ring->wptr = 0; 1758 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1759 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1760 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1761 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1762 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1763 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1764 1765 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1766 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1767 ring->wptr = 0; 1768 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1769 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1770 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1771 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1772 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1773 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1774 1775 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1776 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1777 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1778 } 1779 1780 /* Unstall DPG */ 1781 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1782 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1783 1784 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1785 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1786 } 1787 } else { 1788 /* unpause dpg, no need to wait */ 1789 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1790 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1791 } 1792 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1793 } 1794 1795 return 0; 1796 } 1797 1798 /** 1799 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1800 * 1801 * @ring: amdgpu_ring pointer 1802 * 1803 * Returns the current hardware read pointer 1804 */ 1805 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1806 { 1807 struct amdgpu_device *adev = ring->adev; 1808 1809 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1810 } 1811 1812 /** 1813 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1814 * 1815 * @ring: amdgpu_ring pointer 1816 * 1817 * Returns the current hardware write pointer 1818 */ 1819 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1820 { 1821 struct amdgpu_device *adev = ring->adev; 1822 1823 if (ring->use_doorbell) 1824 return *ring->wptr_cpu_addr; 1825 else 1826 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1827 } 1828 1829 /** 1830 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1831 * 1832 * @ring: amdgpu_ring pointer 1833 * 1834 * Commits the write pointer to the hardware 1835 */ 1836 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1837 { 1838 struct amdgpu_device *adev = ring->adev; 1839 volatile struct amdgpu_fw_shared *fw_shared; 1840 1841 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1842 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1843 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1844 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1845 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1846 lower_32_bits(ring->wptr)); 1847 } 1848 1849 if (ring->use_doorbell) { 1850 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1851 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1852 } else { 1853 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1854 } 1855 } 1856 1857 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1858 .type = AMDGPU_RING_TYPE_VCN_DEC, 1859 .align_mask = 0x3f, 1860 .nop = VCN_DEC_SW_CMD_NO_OP, 1861 .secure_submission_supported = true, 1862 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1863 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1864 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1865 .emit_frame_size = 1866 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1867 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1868 VCN_SW_RING_EMIT_FRAME_SIZE, 1869 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1870 .emit_ib = vcn_dec_sw_ring_emit_ib, 1871 .emit_fence = vcn_dec_sw_ring_emit_fence, 1872 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1873 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1874 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1875 .insert_nop = amdgpu_ring_insert_nop, 1876 .insert_end = vcn_dec_sw_ring_insert_end, 1877 .pad_ib = amdgpu_ring_generic_pad_ib, 1878 .begin_use = amdgpu_vcn_ring_begin_use, 1879 .end_use = amdgpu_vcn_ring_end_use, 1880 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1881 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1882 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1883 }; 1884 1885 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1886 struct amdgpu_job *job) 1887 { 1888 struct drm_gpu_scheduler **scheds; 1889 1890 /* The create msg must be in the first IB submitted */ 1891 if (atomic_read(&job->base.entity->fence_seq)) 1892 return -EINVAL; 1893 1894 /* if VCN0 is harvested, we can't support AV1 */ 1895 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1896 return -EINVAL; 1897 1898 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1899 [AMDGPU_RING_PRIO_DEFAULT].sched; 1900 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1901 return 0; 1902 } 1903 1904 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1905 uint64_t addr) 1906 { 1907 struct ttm_operation_ctx ctx = { false, false }; 1908 struct amdgpu_bo_va_mapping *map; 1909 uint32_t *msg, num_buffers; 1910 struct amdgpu_bo *bo; 1911 uint64_t start, end; 1912 unsigned int i; 1913 void *ptr; 1914 int r; 1915 1916 addr &= AMDGPU_GMC_HOLE_MASK; 1917 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1918 if (r) { 1919 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1920 return r; 1921 } 1922 1923 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1924 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1925 if (addr & 0x7) { 1926 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1927 return -EINVAL; 1928 } 1929 1930 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1931 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1932 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1933 if (r) { 1934 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1935 return r; 1936 } 1937 1938 r = amdgpu_bo_kmap(bo, &ptr); 1939 if (r) { 1940 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1941 return r; 1942 } 1943 1944 msg = ptr + addr - start; 1945 1946 /* Check length */ 1947 if (msg[1] > end - addr) { 1948 r = -EINVAL; 1949 goto out; 1950 } 1951 1952 if (msg[3] != RDECODE_MSG_CREATE) 1953 goto out; 1954 1955 num_buffers = msg[2]; 1956 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1957 uint32_t offset, size, *create; 1958 1959 if (msg[0] != RDECODE_MESSAGE_CREATE) 1960 continue; 1961 1962 offset = msg[1]; 1963 size = msg[2]; 1964 1965 if (offset + size > end) { 1966 r = -EINVAL; 1967 goto out; 1968 } 1969 1970 create = ptr + addr + offset - start; 1971 1972 /* H246, HEVC and VP9 can run on any instance */ 1973 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1974 continue; 1975 1976 r = vcn_v3_0_limit_sched(p, job); 1977 if (r) 1978 goto out; 1979 } 1980 1981 out: 1982 amdgpu_bo_kunmap(bo); 1983 return r; 1984 } 1985 1986 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1987 struct amdgpu_job *job, 1988 struct amdgpu_ib *ib) 1989 { 1990 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1991 uint32_t msg_lo = 0, msg_hi = 0; 1992 unsigned i; 1993 int r; 1994 1995 /* The first instance can decode anything */ 1996 if (!ring->me) 1997 return 0; 1998 1999 for (i = 0; i < ib->length_dw; i += 2) { 2000 uint32_t reg = amdgpu_ib_get_value(ib, i); 2001 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 2002 2003 if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) { 2004 msg_lo = val; 2005 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) { 2006 msg_hi = val; 2007 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) && 2008 val == 0) { 2009 r = vcn_v3_0_dec_msg(p, job, 2010 ((u64)msg_hi) << 32 | msg_lo); 2011 if (r) 2012 return r; 2013 } 2014 } 2015 return 0; 2016 } 2017 2018 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 2019 .type = AMDGPU_RING_TYPE_VCN_DEC, 2020 .align_mask = 0xf, 2021 .secure_submission_supported = true, 2022 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 2023 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 2024 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 2025 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 2026 .emit_frame_size = 2027 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2028 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2029 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2030 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2031 6, 2032 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2033 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2034 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2035 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2036 .test_ring = vcn_v2_0_dec_ring_test_ring, 2037 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2038 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2039 .insert_start = vcn_v2_0_dec_ring_insert_start, 2040 .insert_end = vcn_v2_0_dec_ring_insert_end, 2041 .pad_ib = amdgpu_ring_generic_pad_ib, 2042 .begin_use = amdgpu_vcn_ring_begin_use, 2043 .end_use = amdgpu_vcn_ring_end_use, 2044 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2045 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2046 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2047 .reset = amdgpu_vcn_ring_reset, 2048 }; 2049 2050 /** 2051 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2052 * 2053 * @ring: amdgpu_ring pointer 2054 * 2055 * Returns the current hardware enc read pointer 2056 */ 2057 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2058 { 2059 struct amdgpu_device *adev = ring->adev; 2060 2061 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2062 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2063 else 2064 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2065 } 2066 2067 /** 2068 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2069 * 2070 * @ring: amdgpu_ring pointer 2071 * 2072 * Returns the current hardware enc write pointer 2073 */ 2074 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2075 { 2076 struct amdgpu_device *adev = ring->adev; 2077 2078 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2079 if (ring->use_doorbell) 2080 return *ring->wptr_cpu_addr; 2081 else 2082 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2083 } else { 2084 if (ring->use_doorbell) 2085 return *ring->wptr_cpu_addr; 2086 else 2087 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2088 } 2089 } 2090 2091 /** 2092 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2093 * 2094 * @ring: amdgpu_ring pointer 2095 * 2096 * Commits the enc write pointer to the hardware 2097 */ 2098 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2099 { 2100 struct amdgpu_device *adev = ring->adev; 2101 2102 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2103 if (ring->use_doorbell) { 2104 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2105 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2106 } else { 2107 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2108 } 2109 } else { 2110 if (ring->use_doorbell) { 2111 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2112 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2113 } else { 2114 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2115 } 2116 } 2117 } 2118 2119 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2120 .type = AMDGPU_RING_TYPE_VCN_ENC, 2121 .align_mask = 0x3f, 2122 .nop = VCN_ENC_CMD_NO_OP, 2123 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2124 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2125 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2126 .emit_frame_size = 2127 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2128 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2129 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2130 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2131 1, /* vcn_v2_0_enc_ring_insert_end */ 2132 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2133 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2134 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2135 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2136 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2137 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2138 .insert_nop = amdgpu_ring_insert_nop, 2139 .insert_end = vcn_v2_0_enc_ring_insert_end, 2140 .pad_ib = amdgpu_ring_generic_pad_ib, 2141 .begin_use = amdgpu_vcn_ring_begin_use, 2142 .end_use = amdgpu_vcn_ring_end_use, 2143 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2144 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2145 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2146 .reset = amdgpu_vcn_ring_reset, 2147 }; 2148 2149 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2150 { 2151 int i; 2152 2153 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2154 if (adev->vcn.harvest_config & (1 << i)) 2155 continue; 2156 2157 if (!DEC_SW_RING_ENABLED) 2158 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2159 else 2160 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2161 adev->vcn.inst[i].ring_dec.me = i; 2162 } 2163 } 2164 2165 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2166 { 2167 int i, j; 2168 2169 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2170 if (adev->vcn.harvest_config & (1 << i)) 2171 continue; 2172 2173 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 2174 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2175 adev->vcn.inst[i].ring_enc[j].me = i; 2176 } 2177 } 2178 } 2179 2180 static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst) 2181 { 2182 int r; 2183 2184 r = vcn_v3_0_stop(vinst); 2185 if (r) 2186 return r; 2187 vcn_v3_0_enable_clock_gating(vinst); 2188 vcn_v3_0_enable_static_power_gating(vinst); 2189 return vcn_v3_0_start(vinst); 2190 } 2191 2192 static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 2193 { 2194 struct amdgpu_device *adev = ip_block->adev; 2195 int i, ret = 1; 2196 2197 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2198 if (adev->vcn.harvest_config & (1 << i)) 2199 continue; 2200 2201 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2202 } 2203 2204 return ret; 2205 } 2206 2207 static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2208 { 2209 struct amdgpu_device *adev = ip_block->adev; 2210 int i, ret = 0; 2211 2212 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2213 if (adev->vcn.harvest_config & (1 << i)) 2214 continue; 2215 2216 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2217 UVD_STATUS__IDLE); 2218 if (ret) 2219 return ret; 2220 } 2221 2222 return ret; 2223 } 2224 2225 static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2226 enum amd_clockgating_state state) 2227 { 2228 struct amdgpu_device *adev = ip_block->adev; 2229 bool enable = state == AMD_CG_STATE_GATE; 2230 int i; 2231 2232 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2233 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 2234 if (adev->vcn.harvest_config & (1 << i)) 2235 continue; 2236 2237 if (enable) { 2238 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2239 return -EBUSY; 2240 vcn_v3_0_enable_clock_gating(vinst); 2241 } else { 2242 vcn_v3_0_disable_clock_gating(vinst); 2243 } 2244 } 2245 2246 return 0; 2247 } 2248 2249 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 2250 enum amd_powergating_state state) 2251 { 2252 struct amdgpu_device *adev = vinst->adev; 2253 int ret = 0; 2254 2255 /* for SRIOV, guest should not control VCN Power-gating 2256 * MMSCH FW should control Power-gating and clock-gating 2257 * guest should avoid touching CGC and PG 2258 */ 2259 if (amdgpu_sriov_vf(adev)) { 2260 vinst->cur_state = AMD_PG_STATE_UNGATE; 2261 return 0; 2262 } 2263 2264 if (state == vinst->cur_state) 2265 return 0; 2266 2267 if (state == AMD_PG_STATE_GATE) 2268 ret = vcn_v3_0_stop(vinst); 2269 else 2270 ret = vcn_v3_0_start(vinst); 2271 2272 if (!ret) 2273 vinst->cur_state = state; 2274 2275 return ret; 2276 } 2277 2278 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2279 struct amdgpu_irq_src *source, 2280 unsigned type, 2281 enum amdgpu_interrupt_state state) 2282 { 2283 return 0; 2284 } 2285 2286 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2287 struct amdgpu_irq_src *source, 2288 struct amdgpu_iv_entry *entry) 2289 { 2290 uint32_t ip_instance; 2291 2292 switch (entry->client_id) { 2293 case SOC15_IH_CLIENTID_VCN: 2294 ip_instance = 0; 2295 break; 2296 case SOC15_IH_CLIENTID_VCN1: 2297 ip_instance = 1; 2298 break; 2299 default: 2300 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2301 return 0; 2302 } 2303 2304 DRM_DEBUG("IH: VCN TRAP\n"); 2305 2306 switch (entry->src_id) { 2307 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2308 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2309 break; 2310 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2311 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2312 break; 2313 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2314 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2315 break; 2316 default: 2317 DRM_ERROR("Unhandled interrupt: %d %d\n", 2318 entry->src_id, entry->src_data[0]); 2319 break; 2320 } 2321 2322 return 0; 2323 } 2324 2325 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2326 .set = vcn_v3_0_set_interrupt_state, 2327 .process = vcn_v3_0_process_interrupt, 2328 }; 2329 2330 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2331 { 2332 int i; 2333 2334 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2335 if (adev->vcn.harvest_config & (1 << i)) 2336 continue; 2337 2338 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2339 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2340 } 2341 } 2342 2343 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2344 .name = "vcn_v3_0", 2345 .early_init = vcn_v3_0_early_init, 2346 .sw_init = vcn_v3_0_sw_init, 2347 .sw_fini = vcn_v3_0_sw_fini, 2348 .hw_init = vcn_v3_0_hw_init, 2349 .hw_fini = vcn_v3_0_hw_fini, 2350 .suspend = vcn_v3_0_suspend, 2351 .resume = vcn_v3_0_resume, 2352 .is_idle = vcn_v3_0_is_idle, 2353 .wait_for_idle = vcn_v3_0_wait_for_idle, 2354 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2355 .set_powergating_state = vcn_set_powergating_state, 2356 .dump_ip_state = amdgpu_vcn_dump_ip_state, 2357 .print_ip_state = amdgpu_vcn_print_ip_state, 2358 }; 2359 2360 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { 2361 .type = AMD_IP_BLOCK_TYPE_VCN, 2362 .major = 3, 2363 .minor = 0, 2364 .rev = 0, 2365 .funcs = &vcn_v3_0_ip_funcs, 2366 }; 2367