1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "vcn_v2_0.h" 32 #include "mmsch_v3_0.h" 33 #include "vcn_sw_ring.h" 34 35 #include "vcn/vcn_3_0_0_offset.h" 36 #include "vcn/vcn_3_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #include <drm/drm_drv.h> 40 41 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 42 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 43 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 44 45 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 46 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 47 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 48 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 49 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 50 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 51 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 52 53 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 55 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 56 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 57 58 #define VCN_INSTANCES_SIENNA_CICHLID 2 59 #define DEC_SW_RING_ENABLED FALSE 60 61 #define RDECODE_MSG_CREATE 0x00000000 62 #define RDECODE_MESSAGE_CREATE 0x00000001 63 64 static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 94 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 96 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 97 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 98 }; 99 100 static int amdgpu_ih_clientid_vcns[] = { 101 SOC15_IH_CLIENTID_VCN, 102 SOC15_IH_CLIENTID_VCN1 103 }; 104 105 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 106 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 107 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 108 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 109 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 110 enum amd_powergating_state state); 111 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 112 struct dpg_pause_state *new_state); 113 static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst); 114 115 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 116 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 117 118 /** 119 * vcn_v3_0_early_init - set function pointers and load microcode 120 * 121 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 122 * 123 * Set ring and irq function pointers 124 * Load microcode from filesystem 125 */ 126 static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block) 127 { 128 struct amdgpu_device *adev = ip_block->adev; 129 int i, r; 130 131 if (amdgpu_sriov_vf(adev)) { 132 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 133 adev->vcn.harvest_config = 0; 134 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 135 adev->vcn.inst[i].num_enc_rings = 1; 136 137 } else { 138 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 139 AMDGPU_VCN_HARVEST_VCN1)) 140 /* both instances are harvested, disable the block */ 141 return -ENOENT; 142 143 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 144 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 145 IP_VERSION(3, 0, 33)) 146 adev->vcn.inst[i].num_enc_rings = 0; 147 else 148 adev->vcn.inst[i].num_enc_rings = 2; 149 } 150 } 151 152 vcn_v3_0_set_dec_ring_funcs(adev); 153 vcn_v3_0_set_enc_ring_funcs(adev); 154 vcn_v3_0_set_irq_funcs(adev); 155 156 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 157 adev->vcn.inst[i].set_pg_state = vcn_v3_0_set_pg_state; 158 159 r = amdgpu_vcn_early_init(adev, i); 160 if (r) 161 return r; 162 } 163 return 0; 164 } 165 166 /** 167 * vcn_v3_0_sw_init - sw init for VCN block 168 * 169 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 170 * 171 * Load firmware and sw initialization 172 */ 173 static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) 174 { 175 struct amdgpu_ring *ring; 176 int i, j, r; 177 int vcn_doorbell_index = 0; 178 struct amdgpu_device *adev = ip_block->adev; 179 180 /* 181 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines 182 * Formula: 183 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 184 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) 185 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j 186 */ 187 if (amdgpu_sriov_vf(adev)) { 188 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 189 /* get DWORD offset */ 190 vcn_doorbell_index = vcn_doorbell_index << 1; 191 } 192 193 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 194 volatile struct amdgpu_fw_shared *fw_shared; 195 196 if (adev->vcn.harvest_config & (1 << i)) 197 continue; 198 199 r = amdgpu_vcn_sw_init(adev, i); 200 if (r) 201 return r; 202 203 amdgpu_vcn_setup_ucode(adev, i); 204 205 r = amdgpu_vcn_resume(adev, i); 206 if (r) 207 return r; 208 209 adev->vcn.inst[i].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 210 adev->vcn.inst[i].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 211 adev->vcn.inst[i].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 212 adev->vcn.inst[i].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 213 adev->vcn.inst[i].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 214 adev->vcn.inst[i].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 215 216 adev->vcn.inst[i].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 217 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 218 adev->vcn.inst[i].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 219 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 220 adev->vcn.inst[i].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 221 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 222 adev->vcn.inst[i].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 223 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 224 adev->vcn.inst[i].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 225 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 226 227 /* VCN DEC TRAP */ 228 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 229 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 230 if (r) 231 return r; 232 233 atomic_set(&adev->vcn.inst[i].sched_score, 0); 234 235 ring = &adev->vcn.inst[i].ring_dec; 236 ring->use_doorbell = true; 237 if (amdgpu_sriov_vf(adev)) { 238 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1); 239 } else { 240 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 241 } 242 ring->vm_hub = AMDGPU_MMHUB0(0); 243 sprintf(ring->name, "vcn_dec_%d", i); 244 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 245 AMDGPU_RING_PRIO_DEFAULT, 246 &adev->vcn.inst[i].sched_score); 247 if (r) 248 return r; 249 250 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 251 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j); 252 253 /* VCN ENC TRAP */ 254 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 255 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 256 if (r) 257 return r; 258 259 ring = &adev->vcn.inst[i].ring_enc[j]; 260 ring->use_doorbell = true; 261 if (amdgpu_sriov_vf(adev)) { 262 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.inst[i].num_enc_rings + 1) + 1 + j; 263 } else { 264 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 265 } 266 ring->vm_hub = AMDGPU_MMHUB0(0); 267 sprintf(ring->name, "vcn_enc_%d.%d", i, j); 268 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 269 hw_prio, &adev->vcn.inst[i].sched_score); 270 if (r) 271 return r; 272 } 273 274 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 275 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) | 276 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) | 277 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB); 278 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED); 279 fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG; 280 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2)) 281 fw_shared->smu_interface_info.smu_interface_type = 2; 282 else if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 283 IP_VERSION(3, 1, 1)) 284 fw_shared->smu_interface_info.smu_interface_type = 1; 285 286 if (amdgpu_vcnfw_log) 287 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 288 289 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 290 adev->vcn.inst[i].pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 291 adev->vcn.inst[i].reset = vcn_v3_0_reset; 292 } 293 294 adev->vcn.supported_reset = 295 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 296 if (!amdgpu_sriov_vf(adev)) 297 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 298 299 if (amdgpu_sriov_vf(adev)) { 300 r = amdgpu_virt_alloc_mm_table(adev); 301 if (r) 302 return r; 303 } 304 305 r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_3_0, ARRAY_SIZE(vcn_reg_list_3_0)); 306 if (r) 307 return r; 308 309 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 310 if (r) 311 return r; 312 313 return 0; 314 } 315 316 /** 317 * vcn_v3_0_sw_fini - sw fini for VCN block 318 * 319 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 320 * 321 * VCN suspend and free up sw allocation 322 */ 323 static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) 324 { 325 struct amdgpu_device *adev = ip_block->adev; 326 int i, r, idx; 327 328 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 329 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 330 volatile struct amdgpu_fw_shared *fw_shared; 331 332 if (adev->vcn.harvest_config & (1 << i)) 333 continue; 334 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 335 fw_shared->present_flag_0 = 0; 336 fw_shared->sw_ring.is_enabled = false; 337 } 338 339 drm_dev_exit(idx); 340 } 341 342 if (amdgpu_sriov_vf(adev)) 343 amdgpu_virt_free_mm_table(adev); 344 345 amdgpu_vcn_sysfs_reset_mask_fini(adev); 346 347 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 348 r = amdgpu_vcn_suspend(adev, i); 349 if (r) 350 return r; 351 352 r = amdgpu_vcn_sw_fini(adev, i); 353 if (r) 354 return r; 355 } 356 357 kfree(adev->vcn.ip_dump); 358 return 0; 359 } 360 361 /** 362 * vcn_v3_0_hw_init - start and test VCN block 363 * 364 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 365 * 366 * Initialize the hardware, boot up the VCPU and do some testing 367 */ 368 static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block) 369 { 370 struct amdgpu_device *adev = ip_block->adev; 371 struct amdgpu_ring *ring; 372 int i, j, r; 373 374 if (amdgpu_sriov_vf(adev)) { 375 r = vcn_v3_0_start_sriov(adev); 376 if (r) 377 return r; 378 379 /* initialize VCN dec and enc ring buffers */ 380 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 381 if (adev->vcn.harvest_config & (1 << i)) 382 continue; 383 384 ring = &adev->vcn.inst[i].ring_dec; 385 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) { 386 ring->sched.ready = false; 387 ring->no_scheduler = true; 388 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 389 } else { 390 ring->wptr = 0; 391 ring->wptr_old = 0; 392 vcn_v3_0_dec_ring_set_wptr(ring); 393 ring->sched.ready = true; 394 } 395 396 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 397 ring = &adev->vcn.inst[i].ring_enc[j]; 398 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) { 399 ring->sched.ready = false; 400 ring->no_scheduler = true; 401 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name); 402 } else { 403 ring->wptr = 0; 404 ring->wptr_old = 0; 405 vcn_v3_0_enc_ring_set_wptr(ring); 406 ring->sched.ready = true; 407 } 408 } 409 } 410 } else { 411 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 412 if (adev->vcn.harvest_config & (1 << i)) 413 continue; 414 415 ring = &adev->vcn.inst[i].ring_dec; 416 417 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 418 ring->doorbell_index, i); 419 420 r = amdgpu_ring_test_helper(ring); 421 if (r) 422 return r; 423 424 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 425 ring = &adev->vcn.inst[i].ring_enc[j]; 426 r = amdgpu_ring_test_helper(ring); 427 if (r) 428 return r; 429 } 430 } 431 } 432 433 return 0; 434 } 435 436 /** 437 * vcn_v3_0_hw_fini - stop the hardware block 438 * 439 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 440 * 441 * Stop the VCN block, mark ring as not ready any more 442 */ 443 static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) 444 { 445 struct amdgpu_device *adev = ip_block->adev; 446 int i; 447 448 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 449 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 450 451 if (adev->vcn.harvest_config & (1 << i)) 452 continue; 453 454 cancel_delayed_work_sync(&vinst->idle_work); 455 456 if (!amdgpu_sriov_vf(adev)) { 457 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 458 (vinst->cur_state != AMD_PG_STATE_GATE && 459 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 460 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 461 } 462 } 463 } 464 465 return 0; 466 } 467 468 /** 469 * vcn_v3_0_suspend - suspend VCN block 470 * 471 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 472 * 473 * HW fini and suspend VCN block 474 */ 475 static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) 476 { 477 struct amdgpu_device *adev = ip_block->adev; 478 int r, i; 479 480 r = vcn_v3_0_hw_fini(ip_block); 481 if (r) 482 return r; 483 484 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 485 r = amdgpu_vcn_suspend(ip_block->adev, i); 486 if (r) 487 return r; 488 } 489 490 return 0; 491 } 492 493 /** 494 * vcn_v3_0_resume - resume VCN block 495 * 496 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 497 * 498 * Resume firmware and hw init VCN block 499 */ 500 static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block) 501 { 502 struct amdgpu_device *adev = ip_block->adev; 503 int r, i; 504 505 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 506 r = amdgpu_vcn_resume(ip_block->adev, i); 507 if (r) 508 return r; 509 } 510 511 r = vcn_v3_0_hw_init(ip_block); 512 513 return r; 514 } 515 516 /** 517 * vcn_v3_0_mc_resume - memory controller programming 518 * 519 * @vinst: VCN instance 520 * 521 * Let the VCN memory controller know it's offsets 522 */ 523 static void vcn_v3_0_mc_resume(struct amdgpu_vcn_inst *vinst) 524 { 525 struct amdgpu_device *adev = vinst->adev; 526 int inst = vinst->inst; 527 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst].fw->size + 4); 528 uint32_t offset; 529 530 /* cache window 0: fw */ 531 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 532 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 533 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 534 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 535 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 536 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 537 offset = 0; 538 } else { 539 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 540 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 541 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 542 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 543 offset = size; 544 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 545 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 546 } 547 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 548 549 /* cache window 1: stack */ 550 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 551 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 552 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 553 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 554 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 555 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 556 557 /* cache window 2: context */ 558 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 559 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 560 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 561 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 562 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 563 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 564 565 /* non-cache window */ 566 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 567 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 568 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 569 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); 570 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 571 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, 572 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 573 } 574 575 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 576 bool indirect) 577 { 578 struct amdgpu_device *adev = vinst->adev; 579 int inst_idx = vinst->inst; 580 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); 581 uint32_t offset; 582 583 /* cache window 0: fw */ 584 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 585 if (!indirect) { 586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 587 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 588 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 590 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 591 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 594 } else { 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 597 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 598 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 599 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 600 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 601 } 602 offset = 0; 603 } else { 604 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 605 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 606 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 607 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 608 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 609 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 610 offset = size; 611 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 612 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 613 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 614 } 615 616 if (!indirect) 617 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 618 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 619 else 620 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 621 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 622 623 /* cache window 1: stack */ 624 if (!indirect) { 625 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 626 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 627 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 628 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 629 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 630 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 631 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 632 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 633 } else { 634 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 635 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 636 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 637 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 638 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 639 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 640 } 641 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 642 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 643 644 /* cache window 2: context */ 645 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 646 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 647 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 648 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 649 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 650 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 651 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 652 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 653 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 654 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 655 656 /* non-cache window */ 657 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 658 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 659 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 660 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 661 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 662 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 663 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 664 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 665 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 666 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 667 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 668 669 /* VCN global tiling registers */ 670 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 671 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 672 } 673 674 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 675 { 676 struct amdgpu_device *adev = vinst->adev; 677 int inst = vinst->inst; 678 uint32_t data = 0; 679 680 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 681 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 682 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 683 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 684 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 685 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 686 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 687 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 688 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 689 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 690 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 691 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 692 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 693 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 694 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 695 696 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 697 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 698 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 699 } else { 700 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 701 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 702 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 703 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 706 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 707 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 709 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 710 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 713 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 714 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 715 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 716 } 717 718 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 719 data &= ~0x103; 720 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 721 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 722 UVD_POWER_STATUS__UVD_PG_EN_MASK; 723 724 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 725 } 726 727 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 728 { 729 struct amdgpu_device *adev = vinst->adev; 730 int inst = vinst->inst; 731 uint32_t data; 732 733 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 734 /* Before power off, this indicator has to be turned on */ 735 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 736 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 737 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 738 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 739 740 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 741 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 742 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 743 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 744 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 745 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 746 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 747 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 748 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 749 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 752 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 753 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 754 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 755 756 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 757 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 758 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 759 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 760 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 761 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 762 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 763 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 766 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 767 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 768 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 769 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 770 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 771 } 772 } 773 774 /** 775 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 776 * 777 * @vinst: Pointer to the VCN instance structure 778 * 779 * Disable clock gating for VCN block 780 */ 781 static void vcn_v3_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 782 { 783 struct amdgpu_device *adev = vinst->adev; 784 int inst = vinst->inst; 785 uint32_t data; 786 787 /* VCN disable CGC */ 788 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 789 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 790 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 791 else 792 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 793 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 794 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 795 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 796 797 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 798 data &= ~(UVD_CGC_GATE__SYS_MASK 799 | UVD_CGC_GATE__UDEC_MASK 800 | UVD_CGC_GATE__MPEG2_MASK 801 | UVD_CGC_GATE__REGS_MASK 802 | UVD_CGC_GATE__RBC_MASK 803 | UVD_CGC_GATE__LMI_MC_MASK 804 | UVD_CGC_GATE__LMI_UMC_MASK 805 | UVD_CGC_GATE__IDCT_MASK 806 | UVD_CGC_GATE__MPRD_MASK 807 | UVD_CGC_GATE__MPC_MASK 808 | UVD_CGC_GATE__LBSI_MASK 809 | UVD_CGC_GATE__LRBBM_MASK 810 | UVD_CGC_GATE__UDEC_RE_MASK 811 | UVD_CGC_GATE__UDEC_CM_MASK 812 | UVD_CGC_GATE__UDEC_IT_MASK 813 | UVD_CGC_GATE__UDEC_DB_MASK 814 | UVD_CGC_GATE__UDEC_MP_MASK 815 | UVD_CGC_GATE__WCB_MASK 816 | UVD_CGC_GATE__VCPU_MASK 817 | UVD_CGC_GATE__MMSCH_MASK); 818 819 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 820 821 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 822 823 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 824 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 825 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 826 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 827 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 828 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 829 | UVD_CGC_CTRL__SYS_MODE_MASK 830 | UVD_CGC_CTRL__UDEC_MODE_MASK 831 | UVD_CGC_CTRL__MPEG2_MODE_MASK 832 | UVD_CGC_CTRL__REGS_MODE_MASK 833 | UVD_CGC_CTRL__RBC_MODE_MASK 834 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 835 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 836 | UVD_CGC_CTRL__IDCT_MODE_MASK 837 | UVD_CGC_CTRL__MPRD_MODE_MASK 838 | UVD_CGC_CTRL__MPC_MODE_MASK 839 | UVD_CGC_CTRL__LBSI_MODE_MASK 840 | UVD_CGC_CTRL__LRBBM_MODE_MASK 841 | UVD_CGC_CTRL__WCB_MODE_MASK 842 | UVD_CGC_CTRL__VCPU_MODE_MASK 843 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 844 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 845 846 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 847 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 848 | UVD_SUVD_CGC_GATE__SIT_MASK 849 | UVD_SUVD_CGC_GATE__SMP_MASK 850 | UVD_SUVD_CGC_GATE__SCM_MASK 851 | UVD_SUVD_CGC_GATE__SDB_MASK 852 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 853 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 854 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 855 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 856 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 857 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 858 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 859 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 860 | UVD_SUVD_CGC_GATE__SCLR_MASK 861 | UVD_SUVD_CGC_GATE__ENT_MASK 862 | UVD_SUVD_CGC_GATE__IME_MASK 863 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 864 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 865 | UVD_SUVD_CGC_GATE__SITE_MASK 866 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 867 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 868 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 869 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 870 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 871 | UVD_SUVD_CGC_GATE__EFC_MASK 872 | UVD_SUVD_CGC_GATE__SAOE_MASK 873 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 874 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 875 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 876 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 877 | UVD_SUVD_CGC_GATE__SMPA_MASK); 878 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 879 880 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 881 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 882 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 883 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 884 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 885 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 886 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 887 888 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 889 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 892 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 893 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 894 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 895 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 896 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 897 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 898 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 899 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 900 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 901 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 902 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 903 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 904 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 905 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 906 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 907 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 908 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 909 } 910 911 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 912 uint8_t sram_sel, 913 uint8_t indirect) 914 { 915 struct amdgpu_device *adev = vinst->adev; 916 int inst_idx = vinst->inst; 917 uint32_t reg_data = 0; 918 919 /* enable sw clock gating control */ 920 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 921 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 922 else 923 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 924 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 925 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 926 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 927 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 928 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 929 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 930 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 931 UVD_CGC_CTRL__SYS_MODE_MASK | 932 UVD_CGC_CTRL__UDEC_MODE_MASK | 933 UVD_CGC_CTRL__MPEG2_MODE_MASK | 934 UVD_CGC_CTRL__REGS_MODE_MASK | 935 UVD_CGC_CTRL__RBC_MODE_MASK | 936 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 937 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 938 UVD_CGC_CTRL__IDCT_MODE_MASK | 939 UVD_CGC_CTRL__MPRD_MODE_MASK | 940 UVD_CGC_CTRL__MPC_MODE_MASK | 941 UVD_CGC_CTRL__LBSI_MODE_MASK | 942 UVD_CGC_CTRL__LRBBM_MODE_MASK | 943 UVD_CGC_CTRL__WCB_MODE_MASK | 944 UVD_CGC_CTRL__VCPU_MODE_MASK | 945 UVD_CGC_CTRL__MMSCH_MODE_MASK); 946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 947 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 948 949 /* turn off clock gating */ 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 952 953 /* turn on SUVD clock gating */ 954 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 955 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 956 957 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 958 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 959 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 960 } 961 962 /** 963 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 964 * 965 * @vinst: Pointer to the VCN instance structure 966 * 967 * Enable clock gating for VCN block 968 */ 969 static void vcn_v3_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 970 { 971 struct amdgpu_device *adev = vinst->adev; 972 int inst = vinst->inst; 973 uint32_t data; 974 975 /* enable VCN CGC */ 976 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 977 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 978 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 979 else 980 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 981 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 982 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 983 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 984 985 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 986 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 987 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 988 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 989 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 990 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 991 | UVD_CGC_CTRL__SYS_MODE_MASK 992 | UVD_CGC_CTRL__UDEC_MODE_MASK 993 | UVD_CGC_CTRL__MPEG2_MODE_MASK 994 | UVD_CGC_CTRL__REGS_MODE_MASK 995 | UVD_CGC_CTRL__RBC_MODE_MASK 996 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 997 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 998 | UVD_CGC_CTRL__IDCT_MODE_MASK 999 | UVD_CGC_CTRL__MPRD_MODE_MASK 1000 | UVD_CGC_CTRL__MPC_MODE_MASK 1001 | UVD_CGC_CTRL__LBSI_MODE_MASK 1002 | UVD_CGC_CTRL__LRBBM_MODE_MASK 1003 | UVD_CGC_CTRL__WCB_MODE_MASK 1004 | UVD_CGC_CTRL__VCPU_MODE_MASK 1005 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 1006 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 1007 1008 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 1009 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 1010 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 1011 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 1012 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 1013 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 1014 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 1015 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 1016 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 1017 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 1018 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 1019 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 1020 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 1021 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 1022 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 1023 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 1024 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 1025 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 1026 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 1027 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 1028 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 1029 } 1030 1031 static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 1032 { 1033 struct amdgpu_device *adev = vinst->adev; 1034 int inst_idx = vinst->inst; 1035 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1036 struct amdgpu_ring *ring; 1037 uint32_t rb_bufsz, tmp; 1038 int ret; 1039 1040 /* disable register anti-hang mechanism */ 1041 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 1042 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1043 /* enable dynamic power gating mode */ 1044 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 1045 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1046 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1047 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 1048 1049 if (indirect) 1050 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1051 1052 /* enable clock gating */ 1053 vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect); 1054 1055 /* enable VCPU clock */ 1056 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1057 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1058 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 1059 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1060 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1061 1062 /* disable master interupt */ 1063 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1064 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 1065 1066 /* setup mmUVD_LMI_CTRL */ 1067 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1068 UVD_LMI_CTRL__REQ_MODE_MASK | 1069 UVD_LMI_CTRL__CRC_RESET_MASK | 1070 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1071 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1072 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1073 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1074 0x00100000L); 1075 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1076 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 1077 1078 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1079 VCN, inst_idx, mmUVD_MPC_CNTL), 1080 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1081 1082 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1083 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 1084 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1085 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1086 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1087 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1088 1089 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1090 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 1091 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1092 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1093 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1094 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1095 1096 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1097 VCN, inst_idx, mmUVD_MPC_SET_MUX), 1098 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1099 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1100 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1101 1102 vcn_v3_0_mc_resume_dpg_mode(vinst, indirect); 1103 1104 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1105 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1106 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1107 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1108 1109 /* enable LMI MC and UMC channels */ 1110 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1111 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 1112 1113 /* unblock VCPU register access */ 1114 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1115 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1116 1117 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1118 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1119 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1120 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1121 1122 /* enable master interrupt */ 1123 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1124 VCN, inst_idx, mmUVD_MASTINT_EN), 1125 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1126 1127 /* add nop to workaround PSP size check */ 1128 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1129 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1130 1131 if (indirect) { 1132 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1133 if (ret) { 1134 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 1135 return ret; 1136 } 1137 } 1138 1139 ring = &adev->vcn.inst[inst_idx].ring_dec; 1140 /* force RBC into idle state */ 1141 rb_bufsz = order_base_2(ring->ring_size); 1142 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1143 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1144 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1145 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1146 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1147 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1148 1149 /* Stall DPG before WPTR/RPTR reset */ 1150 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1151 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1152 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1153 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1154 1155 /* set the write pointer delay */ 1156 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1157 1158 /* set the wb address */ 1159 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1160 (upper_32_bits(ring->gpu_addr) >> 2)); 1161 1162 /* programm the RB_BASE for ring buffer */ 1163 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1164 lower_32_bits(ring->gpu_addr)); 1165 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1166 upper_32_bits(ring->gpu_addr)); 1167 1168 /* Initialize the ring buffer's read and write pointers */ 1169 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1170 1171 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1172 1173 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1174 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1175 lower_32_bits(ring->wptr)); 1176 1177 /* Reset FW shared memory RBC WPTR/RPTR */ 1178 fw_shared->rb.rptr = 0; 1179 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1180 1181 /*resetting done, fw can check RB ring */ 1182 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1183 1184 /* Unstall DPG */ 1185 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1186 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1187 1188 /* Keeping one read-back to ensure all register writes are done, 1189 * otherwise it may introduce race conditions. 1190 */ 1191 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1192 1193 return 0; 1194 } 1195 1196 static int vcn_v3_0_start(struct amdgpu_vcn_inst *vinst) 1197 { 1198 struct amdgpu_device *adev = vinst->adev; 1199 int i = vinst->inst; 1200 volatile struct amdgpu_fw_shared *fw_shared; 1201 struct amdgpu_ring *ring; 1202 uint32_t rb_bufsz, tmp; 1203 int j, k, r; 1204 1205 if (adev->vcn.harvest_config & (1 << i)) 1206 return 0; 1207 1208 if (adev->pm.dpm_enabled) 1209 amdgpu_dpm_enable_vcn(adev, true, i); 1210 1211 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1212 return vcn_v3_0_start_dpg_mode(vinst, vinst->indirect_sram); 1213 1214 /* disable VCN power gating */ 1215 vcn_v3_0_disable_static_power_gating(vinst); 1216 1217 /* set VCN status busy */ 1218 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1219 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1220 1221 /* SW clock gating */ 1222 vcn_v3_0_disable_clock_gating(vinst); 1223 1224 /* enable VCPU clock */ 1225 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1226 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1227 1228 /* disable master interrupt */ 1229 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1230 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1231 1232 /* enable LMI MC and UMC channels */ 1233 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1234 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1235 1236 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1237 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1238 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1239 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1240 1241 /* setup mmUVD_LMI_CTRL */ 1242 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1243 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1244 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1245 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1246 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1247 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1248 1249 /* setup mmUVD_MPC_CNTL */ 1250 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1251 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1252 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1253 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1254 1255 /* setup UVD_MPC_SET_MUXA0 */ 1256 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1257 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1258 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1259 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1260 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1261 1262 /* setup UVD_MPC_SET_MUXB0 */ 1263 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1264 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1265 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1266 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1267 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1268 1269 /* setup mmUVD_MPC_SET_MUX */ 1270 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1271 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1272 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1273 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1274 1275 vcn_v3_0_mc_resume(vinst); 1276 1277 /* VCN global tiling registers */ 1278 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1279 adev->gfx.config.gb_addr_config); 1280 1281 /* unblock VCPU register access */ 1282 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1283 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1284 1285 /* release VCPU reset to boot */ 1286 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1287 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1288 1289 for (j = 0; j < 10; ++j) { 1290 uint32_t status; 1291 1292 for (k = 0; k < 100; ++k) { 1293 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1294 if (status & 2) 1295 break; 1296 mdelay(10); 1297 } 1298 r = 0; 1299 if (status & 2) 1300 break; 1301 1302 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1303 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1304 UVD_VCPU_CNTL__BLK_RST_MASK, 1305 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1306 mdelay(10); 1307 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1308 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1309 1310 mdelay(10); 1311 r = -1; 1312 } 1313 1314 if (r) { 1315 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1316 return r; 1317 } 1318 1319 /* enable master interrupt */ 1320 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1321 UVD_MASTINT_EN__VCPU_EN_MASK, 1322 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1323 1324 /* clear the busy bit of VCN_STATUS */ 1325 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1326 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1327 1328 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1329 1330 ring = &adev->vcn.inst[i].ring_dec; 1331 /* force RBC into idle state */ 1332 rb_bufsz = order_base_2(ring->ring_size); 1333 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1334 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1335 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1336 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1337 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1338 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1339 1340 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 1341 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1342 1343 /* programm the RB_BASE for ring buffer */ 1344 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1345 lower_32_bits(ring->gpu_addr)); 1346 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1347 upper_32_bits(ring->gpu_addr)); 1348 1349 /* Initialize the ring buffer's read and write pointers */ 1350 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1351 1352 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); 1353 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1354 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1355 lower_32_bits(ring->wptr)); 1356 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1357 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1358 1359 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1360 IP_VERSION(3, 0, 33)) { 1361 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1362 ring = &adev->vcn.inst[i].ring_enc[0]; 1363 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1364 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1365 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1366 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1367 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1368 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1369 1370 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1371 ring = &adev->vcn.inst[i].ring_enc[1]; 1372 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1373 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1374 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1375 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1376 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1377 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1378 } 1379 1380 /* Keeping one read-back to ensure all register writes are done, 1381 * otherwise it may introduce race conditions. 1382 */ 1383 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1384 1385 return 0; 1386 } 1387 1388 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1389 { 1390 int i, j; 1391 struct amdgpu_ring *ring; 1392 uint64_t cache_addr; 1393 uint64_t rb_addr; 1394 uint64_t ctx_addr; 1395 uint32_t param, resp, expected; 1396 uint32_t offset, cache_size; 1397 uint32_t tmp, timeout; 1398 1399 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1400 uint32_t *table_loc; 1401 uint32_t table_size; 1402 uint32_t size, size_dw; 1403 1404 struct mmsch_v3_0_cmd_direct_write 1405 direct_wt = { {0} }; 1406 struct mmsch_v3_0_cmd_direct_read_modify_write 1407 direct_rd_mod_wt = { {0} }; 1408 struct mmsch_v3_0_cmd_end end = { {0} }; 1409 struct mmsch_v3_0_init_header header; 1410 1411 direct_wt.cmd_header.command_type = 1412 MMSCH_COMMAND__DIRECT_REG_WRITE; 1413 direct_rd_mod_wt.cmd_header.command_type = 1414 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1415 end.cmd_header.command_type = 1416 MMSCH_COMMAND__END; 1417 1418 header.version = MMSCH_VERSION; 1419 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1420 for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) { 1421 header.inst[i].init_status = 0; 1422 header.inst[i].table_offset = 0; 1423 header.inst[i].table_size = 0; 1424 } 1425 1426 table_loc = (uint32_t *)table->cpu_addr; 1427 table_loc += header.total_size; 1428 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1429 if (adev->vcn.harvest_config & (1 << i)) 1430 continue; 1431 1432 table_size = 0; 1433 1434 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1435 mmUVD_STATUS), 1436 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1437 1438 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1439 1440 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1441 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1442 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1443 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1444 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1445 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1446 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1447 offset = 0; 1448 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1449 mmUVD_VCPU_CACHE_OFFSET0), 1450 0); 1451 } else { 1452 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1453 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1454 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1455 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1456 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1457 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1458 offset = cache_size; 1459 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1460 mmUVD_VCPU_CACHE_OFFSET0), 1461 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1462 } 1463 1464 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1465 mmUVD_VCPU_CACHE_SIZE0), 1466 cache_size); 1467 1468 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1469 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1470 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1471 lower_32_bits(cache_addr)); 1472 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1473 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1474 upper_32_bits(cache_addr)); 1475 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1476 mmUVD_VCPU_CACHE_OFFSET1), 1477 0); 1478 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1479 mmUVD_VCPU_CACHE_SIZE1), 1480 AMDGPU_VCN_STACK_SIZE); 1481 1482 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1483 AMDGPU_VCN_STACK_SIZE; 1484 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1485 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1486 lower_32_bits(cache_addr)); 1487 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1488 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1489 upper_32_bits(cache_addr)); 1490 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1491 mmUVD_VCPU_CACHE_OFFSET2), 1492 0); 1493 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1494 mmUVD_VCPU_CACHE_SIZE2), 1495 AMDGPU_VCN_CONTEXT_SIZE); 1496 1497 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 1498 ring = &adev->vcn.inst[i].ring_enc[j]; 1499 ring->wptr = 0; 1500 rb_addr = ring->gpu_addr; 1501 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1502 mmUVD_RB_BASE_LO), 1503 lower_32_bits(rb_addr)); 1504 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1505 mmUVD_RB_BASE_HI), 1506 upper_32_bits(rb_addr)); 1507 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1508 mmUVD_RB_SIZE), 1509 ring->ring_size / 4); 1510 } 1511 1512 ring = &adev->vcn.inst[i].ring_dec; 1513 ring->wptr = 0; 1514 rb_addr = ring->gpu_addr; 1515 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1516 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1517 lower_32_bits(rb_addr)); 1518 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1519 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1520 upper_32_bits(rb_addr)); 1521 /* force RBC into idle state */ 1522 tmp = order_base_2(ring->ring_size); 1523 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1524 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1525 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1526 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1527 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1528 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1529 mmUVD_RBC_RB_CNTL), 1530 tmp); 1531 1532 /* add end packet */ 1533 MMSCH_V3_0_INSERT_END(); 1534 1535 /* refine header */ 1536 header.inst[i].init_status = 0; 1537 header.inst[i].table_offset = header.total_size; 1538 header.inst[i].table_size = table_size; 1539 header.total_size += table_size; 1540 } 1541 1542 /* Update init table header in memory */ 1543 size = sizeof(struct mmsch_v3_0_init_header); 1544 table_loc = (uint32_t *)table->cpu_addr; 1545 memcpy((void *)table_loc, &header, size); 1546 1547 /* message MMSCH (in VCN[0]) to initialize this client 1548 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1549 * of memory descriptor location 1550 */ 1551 ctx_addr = table->gpu_addr; 1552 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1553 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1554 1555 /* 2, update vmid of descriptor */ 1556 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1557 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1558 /* use domain0 for MM scheduler */ 1559 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1560 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1561 1562 /* 3, notify mmsch about the size of this descriptor */ 1563 size = header.total_size; 1564 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1565 1566 /* 4, set resp to zero */ 1567 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1568 1569 /* 5, kick off the initialization and wait until 1570 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1571 */ 1572 param = 0x10000001; 1573 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1574 tmp = 0; 1575 timeout = 1000; 1576 resp = 0; 1577 expected = param + 1; 1578 while (resp != expected) { 1579 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1580 if (resp == expected) 1581 break; 1582 1583 udelay(10); 1584 tmp = tmp + 10; 1585 if (tmp >= timeout) { 1586 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1587 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1588 "(expected=0x%08x, readback=0x%08x)\n", 1589 tmp, expected, resp); 1590 return -EBUSY; 1591 } 1592 } 1593 1594 return 0; 1595 } 1596 1597 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1598 { 1599 struct amdgpu_device *adev = vinst->adev; 1600 int inst_idx = vinst->inst; 1601 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1602 uint32_t tmp; 1603 1604 vcn_v3_0_pause_dpg_mode(vinst, &state); 1605 1606 /* Wait for power status to be 1 */ 1607 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1608 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1609 1610 /* wait for read ptr to be equal to write ptr */ 1611 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1612 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1613 1614 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1615 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1616 1617 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1618 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1619 1620 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1621 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1622 1623 /* disable dynamic power gating mode */ 1624 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1625 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1626 1627 /* Keeping one read-back to ensure all register writes are done, 1628 * otherwise it may introduce race conditions. 1629 */ 1630 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1631 1632 return 0; 1633 } 1634 1635 static int vcn_v3_0_stop(struct amdgpu_vcn_inst *vinst) 1636 { 1637 struct amdgpu_device *adev = vinst->adev; 1638 int i = vinst->inst; 1639 uint32_t tmp; 1640 int r = 0; 1641 1642 if (adev->vcn.harvest_config & (1 << i)) 1643 return 0; 1644 1645 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1646 r = vcn_v3_0_stop_dpg_mode(vinst); 1647 goto done; 1648 } 1649 1650 /* wait for vcn idle */ 1651 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1652 if (r) 1653 goto done; 1654 1655 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1656 UVD_LMI_STATUS__READ_CLEAN_MASK | 1657 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1658 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1659 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1660 if (r) 1661 goto done; 1662 1663 /* disable LMI UMC channel */ 1664 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1665 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1666 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1667 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1668 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1669 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1670 if (r) 1671 goto done; 1672 1673 /* block VCPU register access */ 1674 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1675 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1676 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1677 1678 /* reset VCPU */ 1679 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1680 UVD_VCPU_CNTL__BLK_RST_MASK, 1681 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1682 1683 /* disable VCPU clock */ 1684 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1685 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1686 1687 /* apply soft reset */ 1688 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1689 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1690 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1691 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1692 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1693 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1694 1695 /* clear status */ 1696 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1697 1698 /* apply HW clock gating */ 1699 vcn_v3_0_enable_clock_gating(vinst); 1700 1701 /* enable VCN power gating */ 1702 vcn_v3_0_enable_static_power_gating(vinst); 1703 1704 /* Keeping one read-back to ensure all register writes are done, 1705 * otherwise it may introduce race conditions. 1706 */ 1707 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1708 1709 done: 1710 if (adev->pm.dpm_enabled) 1711 amdgpu_dpm_enable_vcn(adev, false, i); 1712 1713 return r; 1714 } 1715 1716 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1717 struct dpg_pause_state *new_state) 1718 { 1719 struct amdgpu_device *adev = vinst->adev; 1720 int inst_idx = vinst->inst; 1721 volatile struct amdgpu_fw_shared *fw_shared; 1722 struct amdgpu_ring *ring; 1723 uint32_t reg_data = 0; 1724 int ret_code; 1725 1726 /* pause/unpause if state is changed */ 1727 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1728 DRM_DEBUG("dpg pause state changed %d -> %d", 1729 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1730 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1731 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1732 1733 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1734 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1735 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1736 1737 if (!ret_code) { 1738 /* pause DPG */ 1739 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1740 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1741 1742 /* wait for ACK */ 1743 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1744 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1745 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1746 1747 /* Stall DPG before WPTR/RPTR reset */ 1748 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1749 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1750 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1751 1752 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != 1753 IP_VERSION(3, 0, 33)) { 1754 /* Restore */ 1755 fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1756 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1757 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1758 ring->wptr = 0; 1759 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1760 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1761 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1762 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1763 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1764 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1765 1766 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET); 1767 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1768 ring->wptr = 0; 1769 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1770 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1771 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1772 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1773 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1774 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET); 1775 1776 /* restore wptr/rptr with pointers saved in FW shared memory*/ 1777 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr); 1778 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr); 1779 } 1780 1781 /* Unstall DPG */ 1782 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1783 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1784 1785 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1786 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1787 } 1788 } else { 1789 /* unpause dpg, no need to wait */ 1790 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1791 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1792 } 1793 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1794 } 1795 1796 return 0; 1797 } 1798 1799 /** 1800 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1801 * 1802 * @ring: amdgpu_ring pointer 1803 * 1804 * Returns the current hardware read pointer 1805 */ 1806 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1807 { 1808 struct amdgpu_device *adev = ring->adev; 1809 1810 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1811 } 1812 1813 /** 1814 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1815 * 1816 * @ring: amdgpu_ring pointer 1817 * 1818 * Returns the current hardware write pointer 1819 */ 1820 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1821 { 1822 struct amdgpu_device *adev = ring->adev; 1823 1824 if (ring->use_doorbell) 1825 return *ring->wptr_cpu_addr; 1826 else 1827 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1828 } 1829 1830 /** 1831 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1832 * 1833 * @ring: amdgpu_ring pointer 1834 * 1835 * Commits the write pointer to the hardware 1836 */ 1837 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1838 { 1839 struct amdgpu_device *adev = ring->adev; 1840 volatile struct amdgpu_fw_shared *fw_shared; 1841 1842 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1843 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */ 1844 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr; 1845 fw_shared->rb.wptr = lower_32_bits(ring->wptr); 1846 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, 1847 lower_32_bits(ring->wptr)); 1848 } 1849 1850 if (ring->use_doorbell) { 1851 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1852 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1853 } else { 1854 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1855 } 1856 } 1857 1858 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { 1859 .type = AMDGPU_RING_TYPE_VCN_DEC, 1860 .align_mask = 0x3f, 1861 .nop = VCN_DEC_SW_CMD_NO_OP, 1862 .secure_submission_supported = true, 1863 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1864 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1865 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1866 .emit_frame_size = 1867 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1868 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1869 VCN_SW_RING_EMIT_FRAME_SIZE, 1870 .emit_ib_size = 5, /* vcn_dec_sw_ring_emit_ib */ 1871 .emit_ib = vcn_dec_sw_ring_emit_ib, 1872 .emit_fence = vcn_dec_sw_ring_emit_fence, 1873 .emit_vm_flush = vcn_dec_sw_ring_emit_vm_flush, 1874 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring, 1875 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib, 1876 .insert_nop = amdgpu_ring_insert_nop, 1877 .insert_end = vcn_dec_sw_ring_insert_end, 1878 .pad_ib = amdgpu_ring_generic_pad_ib, 1879 .begin_use = amdgpu_vcn_ring_begin_use, 1880 .end_use = amdgpu_vcn_ring_end_use, 1881 .emit_wreg = vcn_dec_sw_ring_emit_wreg, 1882 .emit_reg_wait = vcn_dec_sw_ring_emit_reg_wait, 1883 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1884 }; 1885 1886 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p, 1887 struct amdgpu_job *job) 1888 { 1889 struct drm_gpu_scheduler **scheds; 1890 1891 /* The create msg must be in the first IB submitted */ 1892 if (atomic_read(&job->base.entity->fence_seq)) 1893 return -EINVAL; 1894 1895 /* if VCN0 is harvested, we can't support AV1 */ 1896 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) 1897 return -EINVAL; 1898 1899 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC] 1900 [AMDGPU_RING_PRIO_DEFAULT].sched; 1901 drm_sched_entity_modify_sched(job->base.entity, scheds, 1); 1902 return 0; 1903 } 1904 1905 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, 1906 uint64_t addr) 1907 { 1908 struct ttm_operation_ctx ctx = { false, false }; 1909 struct amdgpu_bo_va_mapping *map; 1910 uint32_t *msg, num_buffers; 1911 struct amdgpu_bo *bo; 1912 uint64_t start, end; 1913 unsigned int i; 1914 void *ptr; 1915 int r; 1916 1917 addr &= AMDGPU_GMC_HOLE_MASK; 1918 r = amdgpu_cs_find_mapping(p, addr, &bo, &map); 1919 if (r) { 1920 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 1921 return r; 1922 } 1923 1924 start = map->start * AMDGPU_GPU_PAGE_SIZE; 1925 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; 1926 if (addr & 0x7) { 1927 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1928 return -EINVAL; 1929 } 1930 1931 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1932 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); 1933 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1934 if (r) { 1935 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); 1936 return r; 1937 } 1938 1939 r = amdgpu_bo_kmap(bo, &ptr); 1940 if (r) { 1941 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); 1942 return r; 1943 } 1944 1945 msg = ptr + addr - start; 1946 1947 /* Check length */ 1948 if (msg[1] > end - addr) { 1949 r = -EINVAL; 1950 goto out; 1951 } 1952 1953 if (msg[3] != RDECODE_MSG_CREATE) 1954 goto out; 1955 1956 num_buffers = msg[2]; 1957 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { 1958 uint32_t offset, size, *create; 1959 1960 if (msg[0] != RDECODE_MESSAGE_CREATE) 1961 continue; 1962 1963 offset = msg[1]; 1964 size = msg[2]; 1965 1966 if (offset + size > end) { 1967 r = -EINVAL; 1968 goto out; 1969 } 1970 1971 create = ptr + addr + offset - start; 1972 1973 /* H246, HEVC and VP9 can run on any instance */ 1974 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) 1975 continue; 1976 1977 r = vcn_v3_0_limit_sched(p, job); 1978 if (r) 1979 goto out; 1980 } 1981 1982 out: 1983 amdgpu_bo_kunmap(bo); 1984 return r; 1985 } 1986 1987 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1988 struct amdgpu_job *job, 1989 struct amdgpu_ib *ib) 1990 { 1991 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1992 uint32_t msg_lo = 0, msg_hi = 0; 1993 unsigned i; 1994 int r; 1995 1996 /* The first instance can decode anything */ 1997 if (!ring->me) 1998 return 0; 1999 2000 for (i = 0; i < ib->length_dw; i += 2) { 2001 uint32_t reg = amdgpu_ib_get_value(ib, i); 2002 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 2003 2004 if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data0, 0)) { 2005 msg_lo = val; 2006 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.data1, 0)) { 2007 msg_hi = val; 2008 } else if (reg == PACKET0(p->adev->vcn.inst[ring->me].internal.cmd, 0) && 2009 val == 0) { 2010 r = vcn_v3_0_dec_msg(p, job, 2011 ((u64)msg_hi) << 32 | msg_lo); 2012 if (r) 2013 return r; 2014 } 2015 } 2016 return 0; 2017 } 2018 2019 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 2020 .type = AMDGPU_RING_TYPE_VCN_DEC, 2021 .align_mask = 0xf, 2022 .secure_submission_supported = true, 2023 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 2024 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 2025 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 2026 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place, 2027 .emit_frame_size = 2028 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2029 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2030 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2031 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2032 6, 2033 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2034 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2035 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2036 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2037 .test_ring = vcn_v2_0_dec_ring_test_ring, 2038 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2039 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2040 .insert_start = vcn_v2_0_dec_ring_insert_start, 2041 .insert_end = vcn_v2_0_dec_ring_insert_end, 2042 .pad_ib = amdgpu_ring_generic_pad_ib, 2043 .begin_use = amdgpu_vcn_ring_begin_use, 2044 .end_use = amdgpu_vcn_ring_end_use, 2045 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2046 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2047 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2048 .reset = amdgpu_vcn_ring_reset, 2049 }; 2050 2051 /** 2052 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 2053 * 2054 * @ring: amdgpu_ring pointer 2055 * 2056 * Returns the current hardware enc read pointer 2057 */ 2058 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 2059 { 2060 struct amdgpu_device *adev = ring->adev; 2061 2062 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 2063 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 2064 else 2065 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 2066 } 2067 2068 /** 2069 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 2070 * 2071 * @ring: amdgpu_ring pointer 2072 * 2073 * Returns the current hardware enc write pointer 2074 */ 2075 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 2076 { 2077 struct amdgpu_device *adev = ring->adev; 2078 2079 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2080 if (ring->use_doorbell) 2081 return *ring->wptr_cpu_addr; 2082 else 2083 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 2084 } else { 2085 if (ring->use_doorbell) 2086 return *ring->wptr_cpu_addr; 2087 else 2088 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 2089 } 2090 } 2091 2092 /** 2093 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 2094 * 2095 * @ring: amdgpu_ring pointer 2096 * 2097 * Commits the enc write pointer to the hardware 2098 */ 2099 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 2100 { 2101 struct amdgpu_device *adev = ring->adev; 2102 2103 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 2104 if (ring->use_doorbell) { 2105 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2106 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2107 } else { 2108 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 2109 } 2110 } else { 2111 if (ring->use_doorbell) { 2112 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 2113 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 2114 } else { 2115 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 2116 } 2117 } 2118 } 2119 2120 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 2121 .type = AMDGPU_RING_TYPE_VCN_ENC, 2122 .align_mask = 0x3f, 2123 .nop = VCN_ENC_CMD_NO_OP, 2124 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 2125 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 2126 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 2127 .emit_frame_size = 2128 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2129 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2130 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2131 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2132 1, /* vcn_v2_0_enc_ring_insert_end */ 2133 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2134 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2135 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2136 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2137 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2138 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2139 .insert_nop = amdgpu_ring_insert_nop, 2140 .insert_end = vcn_v2_0_enc_ring_insert_end, 2141 .pad_ib = amdgpu_ring_generic_pad_ib, 2142 .begin_use = amdgpu_vcn_ring_begin_use, 2143 .end_use = amdgpu_vcn_ring_end_use, 2144 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2145 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2146 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2147 .reset = amdgpu_vcn_ring_reset, 2148 }; 2149 2150 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2151 { 2152 int i; 2153 2154 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2155 if (adev->vcn.harvest_config & (1 << i)) 2156 continue; 2157 2158 if (!DEC_SW_RING_ENABLED) 2159 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 2160 else 2161 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs; 2162 adev->vcn.inst[i].ring_dec.me = i; 2163 } 2164 } 2165 2166 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2167 { 2168 int i, j; 2169 2170 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2171 if (adev->vcn.harvest_config & (1 << i)) 2172 continue; 2173 2174 for (j = 0; j < adev->vcn.inst[i].num_enc_rings; ++j) { 2175 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 2176 adev->vcn.inst[i].ring_enc[j].me = i; 2177 } 2178 } 2179 } 2180 2181 static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst) 2182 { 2183 int r; 2184 2185 r = vcn_v3_0_stop(vinst); 2186 if (r) 2187 return r; 2188 vcn_v3_0_enable_clock_gating(vinst); 2189 vcn_v3_0_enable_static_power_gating(vinst); 2190 return vcn_v3_0_start(vinst); 2191 } 2192 2193 static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block) 2194 { 2195 struct amdgpu_device *adev = ip_block->adev; 2196 int i, ret = 1; 2197 2198 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2199 if (adev->vcn.harvest_config & (1 << i)) 2200 continue; 2201 2202 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 2203 } 2204 2205 return ret; 2206 } 2207 2208 static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 2209 { 2210 struct amdgpu_device *adev = ip_block->adev; 2211 int i, ret = 0; 2212 2213 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2214 if (adev->vcn.harvest_config & (1 << i)) 2215 continue; 2216 2217 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2218 UVD_STATUS__IDLE); 2219 if (ret) 2220 return ret; 2221 } 2222 2223 return ret; 2224 } 2225 2226 static int vcn_v3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2227 enum amd_clockgating_state state) 2228 { 2229 struct amdgpu_device *adev = ip_block->adev; 2230 bool enable = state == AMD_CG_STATE_GATE; 2231 int i; 2232 2233 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2234 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 2235 if (adev->vcn.harvest_config & (1 << i)) 2236 continue; 2237 2238 if (enable) { 2239 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 2240 return -EBUSY; 2241 vcn_v3_0_enable_clock_gating(vinst); 2242 } else { 2243 vcn_v3_0_disable_clock_gating(vinst); 2244 } 2245 } 2246 2247 return 0; 2248 } 2249 2250 static int vcn_v3_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 2251 enum amd_powergating_state state) 2252 { 2253 struct amdgpu_device *adev = vinst->adev; 2254 int ret = 0; 2255 2256 /* for SRIOV, guest should not control VCN Power-gating 2257 * MMSCH FW should control Power-gating and clock-gating 2258 * guest should avoid touching CGC and PG 2259 */ 2260 if (amdgpu_sriov_vf(adev)) { 2261 vinst->cur_state = AMD_PG_STATE_UNGATE; 2262 return 0; 2263 } 2264 2265 if (state == vinst->cur_state) 2266 return 0; 2267 2268 if (state == AMD_PG_STATE_GATE) 2269 ret = vcn_v3_0_stop(vinst); 2270 else 2271 ret = vcn_v3_0_start(vinst); 2272 2273 if (!ret) 2274 vinst->cur_state = state; 2275 2276 return ret; 2277 } 2278 2279 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 2280 struct amdgpu_irq_src *source, 2281 unsigned type, 2282 enum amdgpu_interrupt_state state) 2283 { 2284 return 0; 2285 } 2286 2287 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 2288 struct amdgpu_irq_src *source, 2289 struct amdgpu_iv_entry *entry) 2290 { 2291 uint32_t ip_instance; 2292 2293 switch (entry->client_id) { 2294 case SOC15_IH_CLIENTID_VCN: 2295 ip_instance = 0; 2296 break; 2297 case SOC15_IH_CLIENTID_VCN1: 2298 ip_instance = 1; 2299 break; 2300 default: 2301 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2302 return 0; 2303 } 2304 2305 DRM_DEBUG("IH: VCN TRAP\n"); 2306 2307 switch (entry->src_id) { 2308 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2309 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2310 break; 2311 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2312 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2313 break; 2314 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2315 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2316 break; 2317 default: 2318 DRM_ERROR("Unhandled interrupt: %d %d\n", 2319 entry->src_id, entry->src_data[0]); 2320 break; 2321 } 2322 2323 return 0; 2324 } 2325 2326 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 2327 .set = vcn_v3_0_set_interrupt_state, 2328 .process = vcn_v3_0_process_interrupt, 2329 }; 2330 2331 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 2332 { 2333 int i; 2334 2335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2336 if (adev->vcn.harvest_config & (1 << i)) 2337 continue; 2338 2339 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2340 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 2341 } 2342 } 2343 2344 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 2345 .name = "vcn_v3_0", 2346 .early_init = vcn_v3_0_early_init, 2347 .sw_init = vcn_v3_0_sw_init, 2348 .sw_fini = vcn_v3_0_sw_fini, 2349 .hw_init = vcn_v3_0_hw_init, 2350 .hw_fini = vcn_v3_0_hw_fini, 2351 .suspend = vcn_v3_0_suspend, 2352 .resume = vcn_v3_0_resume, 2353 .is_idle = vcn_v3_0_is_idle, 2354 .wait_for_idle = vcn_v3_0_wait_for_idle, 2355 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 2356 .set_powergating_state = vcn_set_powergating_state, 2357 .dump_ip_state = amdgpu_vcn_dump_ip_state, 2358 .print_ip_state = amdgpu_vcn_print_ip_state, 2359 }; 2360 2361 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { 2362 .type = AMD_IP_BLOCK_TYPE_VCN, 2363 .major = 3, 2364 .minor = 0, 2365 .rev = 0, 2366 .funcs = &vcn_v3_0_ip_funcs, 2367 }; 2368