1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v1_0.h" 34 #include "vcn_v2_5.h" 35 36 #include "vcn/vcn_2_5_offset.h" 37 #include "vcn/vcn_2_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 55 56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 57 58 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = { 59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 93 }; 94 95 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 96 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 97 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 98 static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block, 99 enum amd_powergating_state state); 100 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 101 int inst_idx, struct dpg_pause_state *new_state); 102 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 103 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); 104 105 static int amdgpu_ih_clientid_vcns[] = { 106 SOC15_IH_CLIENTID_VCN, 107 SOC15_IH_CLIENTID_VCN1 108 }; 109 110 /** 111 * vcn_v2_5_early_init - set function pointers and load microcode 112 * 113 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 114 * 115 * Set ring and irq function pointers 116 * Load microcode from filesystem 117 */ 118 static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block) 119 { 120 struct amdgpu_device *adev = ip_block->adev; 121 122 if (amdgpu_sriov_vf(adev)) { 123 adev->vcn.num_vcn_inst = 2; 124 adev->vcn.harvest_config = 0; 125 adev->vcn.num_enc_rings = 1; 126 } else { 127 u32 harvest; 128 int i; 129 130 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 131 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 132 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 133 adev->vcn.harvest_config |= 1 << i; 134 } 135 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 136 AMDGPU_VCN_HARVEST_VCN1)) 137 /* both instances are harvested, disable the block */ 138 return -ENOENT; 139 140 adev->vcn.num_enc_rings = 2; 141 } 142 143 vcn_v2_5_set_dec_ring_funcs(adev); 144 vcn_v2_5_set_enc_ring_funcs(adev); 145 vcn_v2_5_set_irq_funcs(adev); 146 vcn_v2_5_set_ras_funcs(adev); 147 148 return amdgpu_vcn_early_init(adev); 149 } 150 151 /** 152 * vcn_v2_5_sw_init - sw init for VCN block 153 * 154 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 155 * 156 * Load firmware and sw initialization 157 */ 158 static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 159 { 160 struct amdgpu_ring *ring; 161 int i, j, r; 162 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 163 uint32_t *ptr; 164 struct amdgpu_device *adev = ip_block->adev; 165 166 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 167 if (adev->vcn.harvest_config & (1 << j)) 168 continue; 169 /* VCN DEC TRAP */ 170 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 171 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 172 if (r) 173 return r; 174 175 /* VCN ENC TRAP */ 176 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 177 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 178 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 179 if (r) 180 return r; 181 } 182 183 /* VCN POISON TRAP */ 184 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 185 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq); 186 if (r) 187 return r; 188 } 189 190 r = amdgpu_vcn_sw_init(adev); 191 if (r) 192 return r; 193 194 amdgpu_vcn_setup_ucode(adev); 195 196 r = amdgpu_vcn_resume(adev); 197 if (r) 198 return r; 199 200 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 201 volatile struct amdgpu_fw_shared *fw_shared; 202 203 if (adev->vcn.harvest_config & (1 << j)) 204 continue; 205 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 206 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 207 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 208 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 209 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 210 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 211 212 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 213 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 214 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 215 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 216 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 217 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 218 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 219 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 220 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 221 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 222 223 ring = &adev->vcn.inst[j].ring_dec; 224 ring->use_doorbell = true; 225 226 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 227 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 228 229 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) 230 ring->vm_hub = AMDGPU_MMHUB1(0); 231 else 232 ring->vm_hub = AMDGPU_MMHUB0(0); 233 234 sprintf(ring->name, "vcn_dec_%d", j); 235 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 236 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 237 if (r) 238 return r; 239 240 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 241 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 242 243 ring = &adev->vcn.inst[j].ring_enc[i]; 244 ring->use_doorbell = true; 245 246 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 247 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 248 249 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 250 IP_VERSION(2, 5, 0)) 251 ring->vm_hub = AMDGPU_MMHUB1(0); 252 else 253 ring->vm_hub = AMDGPU_MMHUB0(0); 254 255 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 256 r = amdgpu_ring_init(adev, ring, 512, 257 &adev->vcn.inst[j].irq, 0, 258 hw_prio, NULL); 259 if (r) 260 return r; 261 } 262 263 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; 264 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 265 266 if (amdgpu_vcnfw_log) 267 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 268 } 269 270 if (amdgpu_sriov_vf(adev)) { 271 r = amdgpu_virt_alloc_mm_table(adev); 272 if (r) 273 return r; 274 } 275 276 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 277 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 278 279 r = amdgpu_vcn_ras_sw_init(adev); 280 if (r) 281 return r; 282 283 /* Allocate memory for VCN IP Dump buffer */ 284 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 285 if (!ptr) { 286 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 287 adev->vcn.ip_dump = NULL; 288 } else { 289 adev->vcn.ip_dump = ptr; 290 } 291 292 return 0; 293 } 294 295 /** 296 * vcn_v2_5_sw_fini - sw fini for VCN block 297 * 298 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 299 * 300 * VCN suspend and free up sw allocation 301 */ 302 static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) 303 { 304 int i, r, idx; 305 struct amdgpu_device *adev = ip_block->adev; 306 volatile struct amdgpu_fw_shared *fw_shared; 307 308 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 309 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 310 if (adev->vcn.harvest_config & (1 << i)) 311 continue; 312 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 313 fw_shared->present_flag_0 = 0; 314 } 315 drm_dev_exit(idx); 316 } 317 318 319 if (amdgpu_sriov_vf(adev)) 320 amdgpu_virt_free_mm_table(adev); 321 322 r = amdgpu_vcn_suspend(adev); 323 if (r) 324 return r; 325 326 r = amdgpu_vcn_sw_fini(adev); 327 328 kfree(adev->vcn.ip_dump); 329 330 return r; 331 } 332 333 /** 334 * vcn_v2_5_hw_init - start and test VCN block 335 * 336 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 337 * 338 * Initialize the hardware, boot up the VCPU and do some testing 339 */ 340 static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block) 341 { 342 struct amdgpu_device *adev = ip_block->adev; 343 struct amdgpu_ring *ring; 344 int i, j, r = 0; 345 346 if (amdgpu_sriov_vf(adev)) 347 r = vcn_v2_5_sriov_start(adev); 348 349 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 350 if (adev->vcn.harvest_config & (1 << j)) 351 continue; 352 353 if (amdgpu_sriov_vf(adev)) { 354 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 355 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 356 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 357 adev->vcn.inst[j].ring_dec.sched.ready = true; 358 } else { 359 360 ring = &adev->vcn.inst[j].ring_dec; 361 362 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 363 ring->doorbell_index, j); 364 365 r = amdgpu_ring_test_helper(ring); 366 if (r) 367 return r; 368 369 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 370 ring = &adev->vcn.inst[j].ring_enc[i]; 371 r = amdgpu_ring_test_helper(ring); 372 if (r) 373 return r; 374 } 375 } 376 } 377 378 return r; 379 } 380 381 /** 382 * vcn_v2_5_hw_fini - stop the hardware block 383 * 384 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 385 * 386 * Stop the VCN block, mark ring as not ready any more 387 */ 388 static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) 389 { 390 struct amdgpu_device *adev = ip_block->adev; 391 int i; 392 393 cancel_delayed_work_sync(&adev->vcn.idle_work); 394 395 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 396 if (adev->vcn.harvest_config & (1 << i)) 397 continue; 398 399 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 400 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 401 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 402 vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE); 403 404 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 405 amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0); 406 } 407 408 return 0; 409 } 410 411 /** 412 * vcn_v2_5_suspend - suspend VCN block 413 * 414 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 415 * 416 * HW fini and suspend VCN block 417 */ 418 static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) 419 { 420 int r; 421 422 r = vcn_v2_5_hw_fini(ip_block); 423 if (r) 424 return r; 425 426 r = amdgpu_vcn_suspend(ip_block->adev); 427 428 return r; 429 } 430 431 /** 432 * vcn_v2_5_resume - resume VCN block 433 * 434 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 435 * 436 * Resume firmware and hw init VCN block 437 */ 438 static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block) 439 { 440 int r; 441 442 r = amdgpu_vcn_resume(ip_block->adev); 443 if (r) 444 return r; 445 446 r = vcn_v2_5_hw_init(ip_block); 447 448 return r; 449 } 450 451 /** 452 * vcn_v2_5_mc_resume - memory controller programming 453 * 454 * @adev: amdgpu_device pointer 455 * @i: instance to resume 456 * 457 * Let the VCN memory controller know it's offsets 458 */ 459 static void vcn_v2_5_mc_resume(struct amdgpu_device *adev, int i) 460 { 461 uint32_t size; 462 uint32_t offset; 463 464 if (adev->vcn.harvest_config & (1 << i)) 465 return; 466 467 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 468 /* cache window 0: fw */ 469 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 470 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 471 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 472 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 473 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 474 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 475 offset = 0; 476 } else { 477 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 478 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 479 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 480 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 481 offset = size; 482 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 483 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 484 } 485 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 486 487 /* cache window 1: stack */ 488 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 489 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 490 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 491 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 492 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 493 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 494 495 /* cache window 2: context */ 496 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 497 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 498 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 499 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 500 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 501 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 502 503 /* non-cache window */ 504 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 505 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 506 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 507 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 508 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 509 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 510 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 511 } 512 513 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 514 { 515 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); 516 uint32_t offset; 517 518 /* cache window 0: fw */ 519 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 520 if (!indirect) { 521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 522 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 523 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 524 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 525 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 526 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 527 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 528 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 529 } else { 530 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 531 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 536 } 537 offset = 0; 538 } else { 539 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 540 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 541 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 544 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 545 offset = size; 546 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 547 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 548 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 549 } 550 551 if (!indirect) 552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 553 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 554 else 555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 556 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 557 558 /* cache window 1: stack */ 559 if (!indirect) { 560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 561 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 562 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 563 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 564 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 565 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 566 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 567 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 568 } else { 569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 570 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 571 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 572 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 573 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 574 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 575 } 576 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 577 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 578 579 /* cache window 2: context */ 580 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 581 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 582 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 583 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 584 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 585 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 586 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 587 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 588 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 589 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 590 591 /* non-cache window */ 592 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 593 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 594 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 595 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 596 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 597 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 598 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 599 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 600 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 601 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 602 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 603 604 /* VCN global tiling registers */ 605 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 606 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 607 } 608 609 /** 610 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 611 * 612 * @adev: amdgpu_device pointer 613 * @i: instance to disable clockgating on 614 * 615 * Disable clock gating for VCN block 616 */ 617 static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev, int i) 618 { 619 uint32_t data; 620 621 if (adev->vcn.harvest_config & (1 << i)) 622 return; 623 /* UVD disable CGC */ 624 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 625 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 626 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 627 else 628 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 629 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 630 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 631 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 632 633 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 634 data &= ~(UVD_CGC_GATE__SYS_MASK 635 | UVD_CGC_GATE__UDEC_MASK 636 | UVD_CGC_GATE__MPEG2_MASK 637 | UVD_CGC_GATE__REGS_MASK 638 | UVD_CGC_GATE__RBC_MASK 639 | UVD_CGC_GATE__LMI_MC_MASK 640 | UVD_CGC_GATE__LMI_UMC_MASK 641 | UVD_CGC_GATE__IDCT_MASK 642 | UVD_CGC_GATE__MPRD_MASK 643 | UVD_CGC_GATE__MPC_MASK 644 | UVD_CGC_GATE__LBSI_MASK 645 | UVD_CGC_GATE__LRBBM_MASK 646 | UVD_CGC_GATE__UDEC_RE_MASK 647 | UVD_CGC_GATE__UDEC_CM_MASK 648 | UVD_CGC_GATE__UDEC_IT_MASK 649 | UVD_CGC_GATE__UDEC_DB_MASK 650 | UVD_CGC_GATE__UDEC_MP_MASK 651 | UVD_CGC_GATE__WCB_MASK 652 | UVD_CGC_GATE__VCPU_MASK 653 | UVD_CGC_GATE__MMSCH_MASK); 654 655 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 656 657 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 658 659 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 660 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 661 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 662 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 663 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 664 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 665 | UVD_CGC_CTRL__SYS_MODE_MASK 666 | UVD_CGC_CTRL__UDEC_MODE_MASK 667 | UVD_CGC_CTRL__MPEG2_MODE_MASK 668 | UVD_CGC_CTRL__REGS_MODE_MASK 669 | UVD_CGC_CTRL__RBC_MODE_MASK 670 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 671 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 672 | UVD_CGC_CTRL__IDCT_MODE_MASK 673 | UVD_CGC_CTRL__MPRD_MODE_MASK 674 | UVD_CGC_CTRL__MPC_MODE_MASK 675 | UVD_CGC_CTRL__LBSI_MODE_MASK 676 | UVD_CGC_CTRL__LRBBM_MODE_MASK 677 | UVD_CGC_CTRL__WCB_MODE_MASK 678 | UVD_CGC_CTRL__VCPU_MODE_MASK 679 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 680 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 681 682 /* turn on */ 683 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 684 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 685 | UVD_SUVD_CGC_GATE__SIT_MASK 686 | UVD_SUVD_CGC_GATE__SMP_MASK 687 | UVD_SUVD_CGC_GATE__SCM_MASK 688 | UVD_SUVD_CGC_GATE__SDB_MASK 689 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 690 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 691 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 692 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 693 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 694 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 695 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 696 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 697 | UVD_SUVD_CGC_GATE__SCLR_MASK 698 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 699 | UVD_SUVD_CGC_GATE__ENT_MASK 700 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 701 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 702 | UVD_SUVD_CGC_GATE__SITE_MASK 703 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 704 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 705 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 706 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 707 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 708 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 709 710 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 711 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 712 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 713 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 714 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 715 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 716 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 717 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 718 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 719 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 720 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 721 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 722 } 723 724 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev, 725 uint8_t sram_sel, int inst_idx, uint8_t indirect) 726 { 727 uint32_t reg_data = 0; 728 729 /* enable sw clock gating control */ 730 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 731 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 732 else 733 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 734 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 735 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 736 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 737 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 738 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 739 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 740 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 741 UVD_CGC_CTRL__SYS_MODE_MASK | 742 UVD_CGC_CTRL__UDEC_MODE_MASK | 743 UVD_CGC_CTRL__MPEG2_MODE_MASK | 744 UVD_CGC_CTRL__REGS_MODE_MASK | 745 UVD_CGC_CTRL__RBC_MODE_MASK | 746 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 747 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 748 UVD_CGC_CTRL__IDCT_MODE_MASK | 749 UVD_CGC_CTRL__MPRD_MODE_MASK | 750 UVD_CGC_CTRL__MPC_MODE_MASK | 751 UVD_CGC_CTRL__LBSI_MODE_MASK | 752 UVD_CGC_CTRL__LRBBM_MODE_MASK | 753 UVD_CGC_CTRL__WCB_MODE_MASK | 754 UVD_CGC_CTRL__VCPU_MODE_MASK | 755 UVD_CGC_CTRL__MMSCH_MODE_MASK); 756 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 757 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 758 759 /* turn off clock gating */ 760 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 761 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 762 763 /* turn on SUVD clock gating */ 764 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 765 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 766 767 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 768 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 769 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 770 } 771 772 /** 773 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 774 * 775 * @adev: amdgpu_device pointer 776 * @i: instance to enable clockgating on 777 * 778 * Enable clock gating for VCN block 779 */ 780 static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev, int i) 781 { 782 uint32_t data = 0; 783 784 if (adev->vcn.harvest_config & (1 << i)) 785 return; 786 /* enable UVD CGC */ 787 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 788 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 789 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 790 else 791 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 792 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 793 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 794 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 795 796 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 797 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 798 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 799 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 800 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 801 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 802 | UVD_CGC_CTRL__SYS_MODE_MASK 803 | UVD_CGC_CTRL__UDEC_MODE_MASK 804 | UVD_CGC_CTRL__MPEG2_MODE_MASK 805 | UVD_CGC_CTRL__REGS_MODE_MASK 806 | UVD_CGC_CTRL__RBC_MODE_MASK 807 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 808 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 809 | UVD_CGC_CTRL__IDCT_MODE_MASK 810 | UVD_CGC_CTRL__MPRD_MODE_MASK 811 | UVD_CGC_CTRL__MPC_MODE_MASK 812 | UVD_CGC_CTRL__LBSI_MODE_MASK 813 | UVD_CGC_CTRL__LRBBM_MODE_MASK 814 | UVD_CGC_CTRL__WCB_MODE_MASK 815 | UVD_CGC_CTRL__VCPU_MODE_MASK); 816 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 817 818 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 819 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 820 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 821 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 822 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 823 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 824 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 825 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 826 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 827 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 828 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 829 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 830 } 831 832 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, 833 bool indirect) 834 { 835 uint32_t tmp; 836 837 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0)) 838 return; 839 840 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 841 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 842 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 843 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 844 WREG32_SOC15_DPG_MODE(inst_idx, 845 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), 846 tmp, 0, indirect); 847 848 tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 849 WREG32_SOC15_DPG_MODE(inst_idx, 850 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), 851 tmp, 0, indirect); 852 853 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 854 WREG32_SOC15_DPG_MODE(inst_idx, 855 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), 856 tmp, 0, indirect); 857 } 858 859 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 860 { 861 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 862 struct amdgpu_ring *ring; 863 uint32_t rb_bufsz, tmp; 864 865 /* disable register anti-hang mechanism */ 866 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 867 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 868 /* enable dynamic power gating mode */ 869 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 870 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 871 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 872 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 873 874 if (indirect) 875 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 876 877 /* enable clock gating */ 878 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 879 880 /* enable VCPU clock */ 881 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 882 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 883 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 884 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 885 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 886 887 /* disable master interupt */ 888 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 889 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 890 891 /* setup mmUVD_LMI_CTRL */ 892 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 893 UVD_LMI_CTRL__REQ_MODE_MASK | 894 UVD_LMI_CTRL__CRC_RESET_MASK | 895 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 896 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 897 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 898 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 899 0x00100000L); 900 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 901 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 902 903 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 904 VCN, 0, mmUVD_MPC_CNTL), 905 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 906 907 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 908 VCN, 0, mmUVD_MPC_SET_MUXA0), 909 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 910 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 911 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 912 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 913 914 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 915 VCN, 0, mmUVD_MPC_SET_MUXB0), 916 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 917 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 918 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 919 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 920 921 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 922 VCN, 0, mmUVD_MPC_SET_MUX), 923 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 924 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 925 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 926 927 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); 928 929 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 930 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 931 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 932 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 933 934 /* enable LMI MC and UMC channels */ 935 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 936 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 937 938 vcn_v2_6_enable_ras(adev, inst_idx, indirect); 939 940 /* unblock VCPU register access */ 941 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 942 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 943 944 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 945 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 946 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 947 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 948 949 /* enable master interrupt */ 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, 0, mmUVD_MASTINT_EN), 952 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 953 954 if (indirect) 955 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 956 957 ring = &adev->vcn.inst[inst_idx].ring_dec; 958 /* force RBC into idle state */ 959 rb_bufsz = order_base_2(ring->ring_size); 960 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 961 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 962 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 963 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 964 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 965 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 966 967 /* Stall DPG before WPTR/RPTR reset */ 968 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 969 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 970 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 971 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 972 973 /* set the write pointer delay */ 974 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 975 976 /* set the wb address */ 977 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 978 (upper_32_bits(ring->gpu_addr) >> 2)); 979 980 /* program the RB_BASE for ring buffer */ 981 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 982 lower_32_bits(ring->gpu_addr)); 983 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 984 upper_32_bits(ring->gpu_addr)); 985 986 /* Initialize the ring buffer's read and write pointers */ 987 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 988 989 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 990 991 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 992 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 993 lower_32_bits(ring->wptr)); 994 995 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 996 /* Unstall DPG */ 997 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 998 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 999 1000 return 0; 1001 } 1002 1003 static int vcn_v2_5_start(struct amdgpu_device *adev, int i) 1004 { 1005 volatile struct amdgpu_fw_shared *fw_shared = 1006 adev->vcn.inst[i].fw_shared.cpu_addr; 1007 struct amdgpu_ring *ring; 1008 uint32_t rb_bufsz, tmp; 1009 int j, k, r; 1010 1011 if (adev->vcn.harvest_config & (1 << i)) 1012 return 0; 1013 1014 if (adev->pm.dpm_enabled) 1015 amdgpu_dpm_enable_vcn(adev, true, i); 1016 1017 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1018 return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1019 1020 /* disable register anti-hang mechanism */ 1021 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 1022 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1023 1024 /* set uvd status busy */ 1025 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1026 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1027 1028 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1029 return 0; 1030 1031 /* SW clock gating */ 1032 vcn_v2_5_disable_clock_gating(adev, i); 1033 1034 /* enable VCPU clock */ 1035 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1036 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1037 1038 /* disable master interrupt */ 1039 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1040 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1041 1042 /* setup mmUVD_LMI_CTRL */ 1043 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1044 tmp &= ~0xff; 1045 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 1046 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1047 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1048 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1049 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1050 1051 /* setup mmUVD_MPC_CNTL */ 1052 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1053 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1054 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1055 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1056 1057 /* setup UVD_MPC_SET_MUXA0 */ 1058 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1059 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1060 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1061 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1062 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1063 1064 /* setup UVD_MPC_SET_MUXB0 */ 1065 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1066 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1067 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1068 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1069 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1070 1071 /* setup mmUVD_MPC_SET_MUX */ 1072 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1073 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1074 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1075 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1076 1077 vcn_v2_5_mc_resume(adev, i); 1078 1079 /* VCN global tiling registers */ 1080 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1081 adev->gfx.config.gb_addr_config); 1082 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1083 adev->gfx.config.gb_addr_config); 1084 1085 /* enable LMI MC and UMC channels */ 1086 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1087 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1088 1089 /* unblock VCPU register access */ 1090 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1091 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1092 1093 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1094 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1095 1096 for (k = 0; k < 10; ++k) { 1097 uint32_t status; 1098 1099 for (j = 0; j < 100; ++j) { 1100 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1101 if (status & 2) 1102 break; 1103 if (amdgpu_emu_mode == 1) 1104 msleep(500); 1105 else 1106 mdelay(10); 1107 } 1108 r = 0; 1109 if (status & 2) 1110 break; 1111 1112 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1113 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1114 UVD_VCPU_CNTL__BLK_RST_MASK, 1115 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1116 mdelay(10); 1117 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1118 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1119 1120 mdelay(10); 1121 r = -1; 1122 } 1123 1124 if (r) { 1125 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1126 return r; 1127 } 1128 1129 /* enable master interrupt */ 1130 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1131 UVD_MASTINT_EN__VCPU_EN_MASK, 1132 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1133 1134 /* clear the busy bit of VCN_STATUS */ 1135 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1136 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1137 1138 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1139 1140 ring = &adev->vcn.inst[i].ring_dec; 1141 /* force RBC into idle state */ 1142 rb_bufsz = order_base_2(ring->ring_size); 1143 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1144 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1145 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1146 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1147 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1148 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1149 1150 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1151 /* program the RB_BASE for ring buffer */ 1152 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1153 lower_32_bits(ring->gpu_addr)); 1154 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1155 upper_32_bits(ring->gpu_addr)); 1156 1157 /* Initialize the ring buffer's read and write pointers */ 1158 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1159 1160 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1161 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1162 lower_32_bits(ring->wptr)); 1163 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1164 1165 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1166 ring = &adev->vcn.inst[i].ring_enc[0]; 1167 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1168 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1169 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1170 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1171 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1172 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1173 1174 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1175 ring = &adev->vcn.inst[i].ring_enc[1]; 1176 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1177 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1178 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1179 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1180 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1181 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1182 1183 return 0; 1184 } 1185 1186 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1187 struct amdgpu_mm_table *table) 1188 { 1189 uint32_t data = 0, loop = 0, size = 0; 1190 uint64_t addr = table->gpu_addr; 1191 struct mmsch_v1_1_init_header *header = NULL; 1192 1193 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1194 size = header->total_size; 1195 1196 /* 1197 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1198 * memory descriptor location 1199 */ 1200 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1201 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1202 1203 /* 2, update vmid of descriptor */ 1204 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1205 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1206 /* use domain0 for MM scheduler */ 1207 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1208 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1209 1210 /* 3, notify mmsch about the size of this descriptor */ 1211 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1212 1213 /* 4, set resp to zero */ 1214 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1215 1216 /* 1217 * 5, kick off the initialization and wait until 1218 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1219 */ 1220 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1221 1222 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1223 loop = 10; 1224 while ((data & 0x10000002) != 0x10000002) { 1225 udelay(100); 1226 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1227 loop--; 1228 if (!loop) 1229 break; 1230 } 1231 1232 if (!loop) { 1233 dev_err(adev->dev, 1234 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1235 data); 1236 return -EBUSY; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1243 { 1244 struct amdgpu_ring *ring; 1245 uint32_t offset, size, tmp, i, rb_bufsz; 1246 uint32_t table_size = 0; 1247 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1248 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1249 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1250 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1251 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1252 1253 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1254 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1255 end.cmd_header.command_type = MMSCH_COMMAND__END; 1256 1257 header->version = MMSCH_VERSION; 1258 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1259 init_table += header->total_size; 1260 1261 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1262 header->eng[i].table_offset = header->total_size; 1263 header->eng[i].init_status = 0; 1264 header->eng[i].table_size = 0; 1265 1266 table_size = 0; 1267 1268 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1269 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1270 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1271 1272 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1273 /* mc resume*/ 1274 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1275 MMSCH_V1_0_INSERT_DIRECT_WT( 1276 SOC15_REG_OFFSET(VCN, i, 1277 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1278 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1279 MMSCH_V1_0_INSERT_DIRECT_WT( 1280 SOC15_REG_OFFSET(VCN, i, 1281 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1282 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1283 offset = 0; 1284 MMSCH_V1_0_INSERT_DIRECT_WT( 1285 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1286 } else { 1287 MMSCH_V1_0_INSERT_DIRECT_WT( 1288 SOC15_REG_OFFSET(VCN, i, 1289 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1290 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1291 MMSCH_V1_0_INSERT_DIRECT_WT( 1292 SOC15_REG_OFFSET(VCN, i, 1293 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1294 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1295 offset = size; 1296 MMSCH_V1_0_INSERT_DIRECT_WT( 1297 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1298 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1299 } 1300 1301 MMSCH_V1_0_INSERT_DIRECT_WT( 1302 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1303 size); 1304 MMSCH_V1_0_INSERT_DIRECT_WT( 1305 SOC15_REG_OFFSET(VCN, i, 1306 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1307 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1308 MMSCH_V1_0_INSERT_DIRECT_WT( 1309 SOC15_REG_OFFSET(VCN, i, 1310 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1311 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1312 MMSCH_V1_0_INSERT_DIRECT_WT( 1313 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1314 0); 1315 MMSCH_V1_0_INSERT_DIRECT_WT( 1316 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1317 AMDGPU_VCN_STACK_SIZE); 1318 MMSCH_V1_0_INSERT_DIRECT_WT( 1319 SOC15_REG_OFFSET(VCN, i, 1320 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1321 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1322 AMDGPU_VCN_STACK_SIZE)); 1323 MMSCH_V1_0_INSERT_DIRECT_WT( 1324 SOC15_REG_OFFSET(VCN, i, 1325 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1326 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1327 AMDGPU_VCN_STACK_SIZE)); 1328 MMSCH_V1_0_INSERT_DIRECT_WT( 1329 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1330 0); 1331 MMSCH_V1_0_INSERT_DIRECT_WT( 1332 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1333 AMDGPU_VCN_CONTEXT_SIZE); 1334 1335 ring = &adev->vcn.inst[i].ring_enc[0]; 1336 ring->wptr = 0; 1337 1338 MMSCH_V1_0_INSERT_DIRECT_WT( 1339 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1340 lower_32_bits(ring->gpu_addr)); 1341 MMSCH_V1_0_INSERT_DIRECT_WT( 1342 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1343 upper_32_bits(ring->gpu_addr)); 1344 MMSCH_V1_0_INSERT_DIRECT_WT( 1345 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1346 ring->ring_size / 4); 1347 1348 ring = &adev->vcn.inst[i].ring_dec; 1349 ring->wptr = 0; 1350 MMSCH_V1_0_INSERT_DIRECT_WT( 1351 SOC15_REG_OFFSET(VCN, i, 1352 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1353 lower_32_bits(ring->gpu_addr)); 1354 MMSCH_V1_0_INSERT_DIRECT_WT( 1355 SOC15_REG_OFFSET(VCN, i, 1356 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1357 upper_32_bits(ring->gpu_addr)); 1358 1359 /* force RBC into idle state */ 1360 rb_bufsz = order_base_2(ring->ring_size); 1361 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1362 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1363 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1364 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1365 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1366 MMSCH_V1_0_INSERT_DIRECT_WT( 1367 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1368 1369 /* add end packet */ 1370 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1371 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1372 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1373 1374 /* refine header */ 1375 header->eng[i].table_size = table_size; 1376 header->total_size += table_size; 1377 } 1378 1379 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1380 } 1381 1382 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1383 { 1384 uint32_t tmp; 1385 1386 /* Wait for power status to be 1 */ 1387 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1388 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1389 1390 /* wait for read ptr to be equal to write ptr */ 1391 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1392 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1393 1394 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1395 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1396 1397 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1398 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1399 1400 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1401 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1402 1403 /* disable dynamic power gating mode */ 1404 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1405 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1406 1407 return 0; 1408 } 1409 1410 static int vcn_v2_5_stop(struct amdgpu_device *adev, int i) 1411 { 1412 uint32_t tmp; 1413 int r; 1414 1415 if (adev->vcn.harvest_config & (1 << i)) 1416 return 0; 1417 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1418 return vcn_v2_5_stop_dpg_mode(adev, i); 1419 1420 /* wait for vcn idle */ 1421 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1422 if (r) 1423 return r; 1424 1425 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1426 UVD_LMI_STATUS__READ_CLEAN_MASK | 1427 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1428 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1429 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1430 if (r) 1431 return r; 1432 1433 /* block LMI UMC channel */ 1434 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1435 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1436 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1437 1438 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1439 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1440 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1441 if (r) 1442 return r; 1443 1444 /* block VCPU register access */ 1445 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1446 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1447 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1448 1449 /* reset VCPU */ 1450 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1451 UVD_VCPU_CNTL__BLK_RST_MASK, 1452 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1453 1454 /* disable VCPU clock */ 1455 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1456 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1457 1458 /* clear status */ 1459 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1460 1461 vcn_v2_5_enable_clock_gating(adev, i); 1462 1463 /* enable register anti-hang mechanism */ 1464 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1465 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1466 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1467 1468 if (adev->pm.dpm_enabled) 1469 amdgpu_dpm_enable_vcn(adev, false, i); 1470 1471 return 0; 1472 } 1473 1474 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev, 1475 int inst_idx, struct dpg_pause_state *new_state) 1476 { 1477 struct amdgpu_ring *ring; 1478 uint32_t reg_data = 0; 1479 int ret_code = 0; 1480 1481 /* pause/unpause if state is changed */ 1482 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1483 DRM_DEBUG("dpg pause state changed %d -> %d", 1484 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1485 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1486 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1487 1488 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1489 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1490 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1491 1492 if (!ret_code) { 1493 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1494 1495 /* pause DPG */ 1496 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1497 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1498 1499 /* wait for ACK */ 1500 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1501 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1502 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1503 1504 /* Stall DPG before WPTR/RPTR reset */ 1505 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1506 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1507 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1508 1509 /* Restore */ 1510 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1511 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1512 ring->wptr = 0; 1513 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1514 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1515 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1516 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1517 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1518 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1519 1520 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1521 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1522 ring->wptr = 0; 1523 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1524 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1525 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1526 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1527 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1528 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1529 1530 /* Unstall DPG */ 1531 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1532 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1533 1534 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1535 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1536 } 1537 } else { 1538 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1539 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1540 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1541 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1542 } 1543 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1544 } 1545 1546 return 0; 1547 } 1548 1549 /** 1550 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1551 * 1552 * @ring: amdgpu_ring pointer 1553 * 1554 * Returns the current hardware read pointer 1555 */ 1556 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1557 { 1558 struct amdgpu_device *adev = ring->adev; 1559 1560 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1561 } 1562 1563 /** 1564 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1565 * 1566 * @ring: amdgpu_ring pointer 1567 * 1568 * Returns the current hardware write pointer 1569 */ 1570 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1571 { 1572 struct amdgpu_device *adev = ring->adev; 1573 1574 if (ring->use_doorbell) 1575 return *ring->wptr_cpu_addr; 1576 else 1577 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1578 } 1579 1580 /** 1581 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1582 * 1583 * @ring: amdgpu_ring pointer 1584 * 1585 * Commits the write pointer to the hardware 1586 */ 1587 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1588 { 1589 struct amdgpu_device *adev = ring->adev; 1590 1591 if (ring->use_doorbell) { 1592 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1593 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1594 } else { 1595 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1596 } 1597 } 1598 1599 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1600 .type = AMDGPU_RING_TYPE_VCN_DEC, 1601 .align_mask = 0xf, 1602 .secure_submission_supported = true, 1603 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1604 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1605 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1606 .emit_frame_size = 1607 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1608 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1609 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1610 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1611 6, 1612 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1613 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1614 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1615 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1616 .test_ring = vcn_v2_0_dec_ring_test_ring, 1617 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1618 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1619 .insert_start = vcn_v2_0_dec_ring_insert_start, 1620 .insert_end = vcn_v2_0_dec_ring_insert_end, 1621 .pad_ib = amdgpu_ring_generic_pad_ib, 1622 .begin_use = amdgpu_vcn_ring_begin_use, 1623 .end_use = amdgpu_vcn_ring_end_use, 1624 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1625 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1626 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1627 }; 1628 1629 /** 1630 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1631 * 1632 * @ring: amdgpu_ring pointer 1633 * 1634 * Returns the current hardware enc read pointer 1635 */ 1636 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1637 { 1638 struct amdgpu_device *adev = ring->adev; 1639 1640 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1641 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1642 else 1643 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1644 } 1645 1646 /** 1647 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1648 * 1649 * @ring: amdgpu_ring pointer 1650 * 1651 * Returns the current hardware enc write pointer 1652 */ 1653 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1654 { 1655 struct amdgpu_device *adev = ring->adev; 1656 1657 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1658 if (ring->use_doorbell) 1659 return *ring->wptr_cpu_addr; 1660 else 1661 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1662 } else { 1663 if (ring->use_doorbell) 1664 return *ring->wptr_cpu_addr; 1665 else 1666 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1667 } 1668 } 1669 1670 /** 1671 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1672 * 1673 * @ring: amdgpu_ring pointer 1674 * 1675 * Commits the enc write pointer to the hardware 1676 */ 1677 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1678 { 1679 struct amdgpu_device *adev = ring->adev; 1680 1681 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1682 if (ring->use_doorbell) { 1683 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1684 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1685 } else { 1686 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1687 } 1688 } else { 1689 if (ring->use_doorbell) { 1690 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1691 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1692 } else { 1693 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1694 } 1695 } 1696 } 1697 1698 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1699 .type = AMDGPU_RING_TYPE_VCN_ENC, 1700 .align_mask = 0x3f, 1701 .nop = VCN_ENC_CMD_NO_OP, 1702 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1703 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1704 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1705 .emit_frame_size = 1706 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1707 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1708 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1709 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1710 1, /* vcn_v2_0_enc_ring_insert_end */ 1711 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1712 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1713 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1714 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1715 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1716 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1717 .insert_nop = amdgpu_ring_insert_nop, 1718 .insert_end = vcn_v2_0_enc_ring_insert_end, 1719 .pad_ib = amdgpu_ring_generic_pad_ib, 1720 .begin_use = amdgpu_vcn_ring_begin_use, 1721 .end_use = amdgpu_vcn_ring_end_use, 1722 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1723 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1724 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1725 }; 1726 1727 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1728 { 1729 int i; 1730 1731 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1732 if (adev->vcn.harvest_config & (1 << i)) 1733 continue; 1734 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1735 adev->vcn.inst[i].ring_dec.me = i; 1736 } 1737 } 1738 1739 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1740 { 1741 int i, j; 1742 1743 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1744 if (adev->vcn.harvest_config & (1 << j)) 1745 continue; 1746 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1747 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1748 adev->vcn.inst[j].ring_enc[i].me = j; 1749 } 1750 } 1751 } 1752 1753 static bool vcn_v2_5_is_idle(void *handle) 1754 { 1755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1756 int i, ret = 1; 1757 1758 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1759 if (adev->vcn.harvest_config & (1 << i)) 1760 continue; 1761 1762 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1763 } 1764 1765 return ret; 1766 } 1767 1768 static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1769 { 1770 struct amdgpu_device *adev = ip_block->adev; 1771 int i, ret = 0; 1772 1773 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1774 if (adev->vcn.harvest_config & (1 << i)) 1775 continue; 1776 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1777 UVD_STATUS__IDLE); 1778 if (ret) 1779 return ret; 1780 } 1781 1782 return ret; 1783 } 1784 1785 static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1786 enum amd_clockgating_state state) 1787 { 1788 struct amdgpu_device *adev = ip_block->adev; 1789 bool enable = (state == AMD_CG_STATE_GATE); 1790 int i; 1791 1792 if (amdgpu_sriov_vf(adev)) 1793 return 0; 1794 1795 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1796 if (enable) { 1797 if (!vcn_v2_5_is_idle(adev)) 1798 return -EBUSY; 1799 vcn_v2_5_enable_clock_gating(adev, i); 1800 } else { 1801 vcn_v2_5_disable_clock_gating(adev, i); 1802 } 1803 } 1804 1805 return 0; 1806 } 1807 1808 static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block, 1809 enum amd_powergating_state state) 1810 { 1811 struct amdgpu_device *adev = ip_block->adev; 1812 int ret = 0, i; 1813 1814 if (amdgpu_sriov_vf(adev)) 1815 return 0; 1816 1817 if (state == adev->vcn.cur_state) 1818 return 0; 1819 1820 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1821 if (state == AMD_PG_STATE_GATE) 1822 ret |= vcn_v2_5_stop(adev, i); 1823 else 1824 ret |= vcn_v2_5_start(adev, i); 1825 } 1826 1827 if (!ret) 1828 adev->vcn.cur_state = state; 1829 1830 return ret; 1831 } 1832 1833 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 1834 struct amdgpu_irq_src *source, 1835 unsigned type, 1836 enum amdgpu_interrupt_state state) 1837 { 1838 return 0; 1839 } 1840 1841 static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev, 1842 struct amdgpu_irq_src *source, 1843 unsigned int type, 1844 enum amdgpu_interrupt_state state) 1845 { 1846 return 0; 1847 } 1848 1849 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 1850 struct amdgpu_irq_src *source, 1851 struct amdgpu_iv_entry *entry) 1852 { 1853 uint32_t ip_instance; 1854 1855 switch (entry->client_id) { 1856 case SOC15_IH_CLIENTID_VCN: 1857 ip_instance = 0; 1858 break; 1859 case SOC15_IH_CLIENTID_VCN1: 1860 ip_instance = 1; 1861 break; 1862 default: 1863 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1864 return 0; 1865 } 1866 1867 DRM_DEBUG("IH: VCN TRAP\n"); 1868 1869 switch (entry->src_id) { 1870 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1871 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1872 break; 1873 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1874 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1875 break; 1876 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1877 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1878 break; 1879 default: 1880 DRM_ERROR("Unhandled interrupt: %d %d\n", 1881 entry->src_id, entry->src_data[0]); 1882 break; 1883 } 1884 1885 return 0; 1886 } 1887 1888 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 1889 .set = vcn_v2_5_set_interrupt_state, 1890 .process = vcn_v2_5_process_interrupt, 1891 }; 1892 1893 static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = { 1894 .set = vcn_v2_6_set_ras_interrupt_state, 1895 .process = amdgpu_vcn_process_poison_irq, 1896 }; 1897 1898 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 1899 { 1900 int i; 1901 1902 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1903 if (adev->vcn.harvest_config & (1 << i)) 1904 continue; 1905 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1906 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 1907 1908 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.num_enc_rings + 1; 1909 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs; 1910 } 1911 } 1912 1913 static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 1914 { 1915 struct amdgpu_device *adev = ip_block->adev; 1916 int i, j; 1917 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 1918 uint32_t inst_off, is_powered; 1919 1920 if (!adev->vcn.ip_dump) 1921 return; 1922 1923 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 1924 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1925 if (adev->vcn.harvest_config & (1 << i)) { 1926 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 1927 continue; 1928 } 1929 1930 inst_off = i * reg_count; 1931 is_powered = (adev->vcn.ip_dump[inst_off] & 1932 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1933 1934 if (is_powered) { 1935 drm_printf(p, "\nActive Instance:VCN%d\n", i); 1936 for (j = 0; j < reg_count; j++) 1937 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name, 1938 adev->vcn.ip_dump[inst_off + j]); 1939 } else { 1940 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 1941 } 1942 } 1943 } 1944 1945 static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 1946 { 1947 struct amdgpu_device *adev = ip_block->adev; 1948 int i, j; 1949 bool is_powered; 1950 uint32_t inst_off; 1951 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 1952 1953 if (!adev->vcn.ip_dump) 1954 return; 1955 1956 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1957 if (adev->vcn.harvest_config & (1 << i)) 1958 continue; 1959 1960 inst_off = i * reg_count; 1961 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1962 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 1963 is_powered = (adev->vcn.ip_dump[inst_off] & 1964 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1965 1966 if (is_powered) 1967 for (j = 1; j < reg_count; j++) 1968 adev->vcn.ip_dump[inst_off + j] = 1969 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i)); 1970 } 1971 } 1972 1973 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1974 .name = "vcn_v2_5", 1975 .early_init = vcn_v2_5_early_init, 1976 .sw_init = vcn_v2_5_sw_init, 1977 .sw_fini = vcn_v2_5_sw_fini, 1978 .hw_init = vcn_v2_5_hw_init, 1979 .hw_fini = vcn_v2_5_hw_fini, 1980 .suspend = vcn_v2_5_suspend, 1981 .resume = vcn_v2_5_resume, 1982 .is_idle = vcn_v2_5_is_idle, 1983 .wait_for_idle = vcn_v2_5_wait_for_idle, 1984 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1985 .set_powergating_state = vcn_v2_5_set_powergating_state, 1986 .dump_ip_state = vcn_v2_5_dump_ip_state, 1987 .print_ip_state = vcn_v2_5_print_ip_state, 1988 }; 1989 1990 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 1991 .name = "vcn_v2_6", 1992 .early_init = vcn_v2_5_early_init, 1993 .sw_init = vcn_v2_5_sw_init, 1994 .sw_fini = vcn_v2_5_sw_fini, 1995 .hw_init = vcn_v2_5_hw_init, 1996 .hw_fini = vcn_v2_5_hw_fini, 1997 .suspend = vcn_v2_5_suspend, 1998 .resume = vcn_v2_5_resume, 1999 .is_idle = vcn_v2_5_is_idle, 2000 .wait_for_idle = vcn_v2_5_wait_for_idle, 2001 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 2002 .set_powergating_state = vcn_v2_5_set_powergating_state, 2003 .dump_ip_state = vcn_v2_5_dump_ip_state, 2004 .print_ip_state = vcn_v2_5_print_ip_state, 2005 }; 2006 2007 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 2008 { 2009 .type = AMD_IP_BLOCK_TYPE_VCN, 2010 .major = 2, 2011 .minor = 5, 2012 .rev = 0, 2013 .funcs = &vcn_v2_5_ip_funcs, 2014 }; 2015 2016 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 2017 { 2018 .type = AMD_IP_BLOCK_TYPE_VCN, 2019 .major = 2, 2020 .minor = 6, 2021 .rev = 0, 2022 .funcs = &vcn_v2_6_ip_funcs, 2023 }; 2024 2025 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 2026 uint32_t instance, uint32_t sub_block) 2027 { 2028 uint32_t poison_stat = 0, reg_value = 0; 2029 2030 switch (sub_block) { 2031 case AMDGPU_VCN_V2_6_VCPU_VCODEC: 2032 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); 2033 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2034 break; 2035 default: 2036 break; 2037 } 2038 2039 if (poison_stat) 2040 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2041 instance, sub_block); 2042 2043 return poison_stat; 2044 } 2045 2046 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) 2047 { 2048 uint32_t inst, sub; 2049 uint32_t poison_stat = 0; 2050 2051 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2052 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) 2053 poison_stat += 2054 vcn_v2_6_query_poison_by_instance(adev, inst, sub); 2055 2056 return !!poison_stat; 2057 } 2058 2059 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = { 2060 .query_poison_status = vcn_v2_6_query_poison_status, 2061 }; 2062 2063 static struct amdgpu_vcn_ras vcn_v2_6_ras = { 2064 .ras_block = { 2065 .hw_ops = &vcn_v2_6_ras_hw_ops, 2066 .ras_late_init = amdgpu_vcn_ras_late_init, 2067 }, 2068 }; 2069 2070 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) 2071 { 2072 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2073 case IP_VERSION(2, 6, 0): 2074 adev->vcn.ras = &vcn_v2_6_ras; 2075 break; 2076 default: 2077 break; 2078 } 2079 } 2080