1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "vcn_v2_0.h" 33 #include "mmsch_v1_0.h" 34 #include "vcn_v2_5.h" 35 36 #include "vcn/vcn_2_5_offset.h" 37 #include "vcn/vcn_2_5_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 56 57 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 58 59 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = { 60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 92 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 93 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 94 }; 95 96 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 97 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 98 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); 99 static int vcn_v2_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 100 enum amd_powergating_state state); 101 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 102 struct dpg_pause_state *new_state); 103 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev); 104 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev); 105 static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst); 106 107 static int amdgpu_ih_clientid_vcns[] = { 108 SOC15_IH_CLIENTID_VCN, 109 SOC15_IH_CLIENTID_VCN1 110 }; 111 112 static void vcn_v2_5_idle_work_handler(struct work_struct *work) 113 { 114 struct amdgpu_vcn_inst *vcn_inst = 115 container_of(work, struct amdgpu_vcn_inst, idle_work.work); 116 struct amdgpu_device *adev = vcn_inst->adev; 117 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0}; 118 unsigned int i, j; 119 int r = 0; 120 121 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 122 struct amdgpu_vcn_inst *v = &adev->vcn.inst[i]; 123 124 if (adev->vcn.harvest_config & (1 << i)) 125 continue; 126 127 for (j = 0; j < v->num_enc_rings; ++j) 128 fence[i] += amdgpu_fence_count_emitted(&v->ring_enc[j]); 129 130 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 131 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 132 !v->using_unified_queue) { 133 struct dpg_pause_state new_state; 134 135 if (fence[i] || 136 unlikely(atomic_read(&v->dpg_enc_submission_cnt))) 137 new_state.fw_based = VCN_DPG_STATE__PAUSE; 138 else 139 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 140 141 v->pause_dpg_mode(v, &new_state); 142 } 143 144 fence[i] += amdgpu_fence_count_emitted(&v->ring_dec); 145 fences += fence[i]; 146 147 } 148 149 if (!fences && !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) { 150 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 151 AMD_PG_STATE_GATE); 152 mutex_lock(&adev->vcn.workload_profile_mutex); 153 if (adev->vcn.workload_profile_active) { 154 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 155 false); 156 if (r) 157 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r); 158 adev->vcn.workload_profile_active = false; 159 } 160 mutex_unlock(&adev->vcn.workload_profile_mutex); 161 } else { 162 schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT); 163 } 164 } 165 166 static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring) 167 { 168 struct amdgpu_device *adev = ring->adev; 169 struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me]; 170 int r = 0; 171 172 atomic_inc(&adev->vcn.inst[0].total_submission_cnt); 173 174 cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work); 175 176 /* We can safely return early here because we've cancelled the 177 * the delayed work so there is no one else to set it to false 178 * and we don't care if someone else sets it to true. 179 */ 180 if (adev->vcn.workload_profile_active) 181 goto pg_lock; 182 183 mutex_lock(&adev->vcn.workload_profile_mutex); 184 if (!adev->vcn.workload_profile_active) { 185 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO, 186 true); 187 if (r) 188 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r); 189 adev->vcn.workload_profile_active = true; 190 } 191 mutex_unlock(&adev->vcn.workload_profile_mutex); 192 193 pg_lock: 194 mutex_lock(&adev->vcn.inst[0].vcn_pg_lock); 195 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 196 AMD_PG_STATE_UNGATE); 197 198 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 199 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 200 !v->using_unified_queue) { 201 struct dpg_pause_state new_state; 202 203 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) { 204 atomic_inc(&v->dpg_enc_submission_cnt); 205 new_state.fw_based = VCN_DPG_STATE__PAUSE; 206 } else { 207 unsigned int fences = 0; 208 unsigned int i; 209 210 for (i = 0; i < v->num_enc_rings; ++i) 211 fences += amdgpu_fence_count_emitted(&v->ring_enc[i]); 212 213 if (fences || atomic_read(&v->dpg_enc_submission_cnt)) 214 new_state.fw_based = VCN_DPG_STATE__PAUSE; 215 else 216 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 217 } 218 v->pause_dpg_mode(v, &new_state); 219 } 220 mutex_unlock(&adev->vcn.inst[0].vcn_pg_lock); 221 } 222 223 static void vcn_v2_5_ring_end_use(struct amdgpu_ring *ring) 224 { 225 struct amdgpu_device *adev = ring->adev; 226 227 /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */ 228 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG && 229 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC && 230 !adev->vcn.inst[ring->me].using_unified_queue) 231 atomic_dec(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt); 232 233 atomic_dec(&adev->vcn.inst[0].total_submission_cnt); 234 235 schedule_delayed_work(&adev->vcn.inst[0].idle_work, 236 VCN_IDLE_TIMEOUT); 237 } 238 239 /** 240 * vcn_v2_5_early_init - set function pointers and load microcode 241 * 242 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 243 * 244 * Set ring and irq function pointers 245 * Load microcode from filesystem 246 */ 247 static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block) 248 { 249 struct amdgpu_device *adev = ip_block->adev; 250 int i, r; 251 252 if (amdgpu_sriov_vf(adev)) { 253 adev->vcn.num_vcn_inst = 2; 254 adev->vcn.harvest_config = 0; 255 for (i = 0; i < adev->vcn.num_vcn_inst; i++) 256 adev->vcn.inst[i].num_enc_rings = 1; 257 } else { 258 u32 harvest; 259 int i; 260 261 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 262 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 263 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 264 adev->vcn.harvest_config |= 1 << i; 265 adev->vcn.inst[i].num_enc_rings = 2; 266 } 267 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 268 AMDGPU_VCN_HARVEST_VCN1)) 269 /* both instances are harvested, disable the block */ 270 return -ENOENT; 271 } 272 273 vcn_v2_5_set_dec_ring_funcs(adev); 274 vcn_v2_5_set_enc_ring_funcs(adev); 275 vcn_v2_5_set_irq_funcs(adev); 276 vcn_v2_5_set_ras_funcs(adev); 277 278 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 279 adev->vcn.inst[i].set_pg_state = vcn_v2_5_set_pg_state; 280 281 r = amdgpu_vcn_early_init(adev, i); 282 if (r) 283 return r; 284 } 285 286 return 0; 287 } 288 289 /** 290 * vcn_v2_5_sw_init - sw init for VCN block 291 * 292 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 293 * 294 * Load firmware and sw initialization 295 */ 296 static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) 297 { 298 struct amdgpu_ring *ring; 299 int i, j, r; 300 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 301 uint32_t *ptr; 302 struct amdgpu_device *adev = ip_block->adev; 303 304 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { 305 volatile struct amdgpu_fw_shared *fw_shared; 306 307 if (adev->vcn.harvest_config & (1 << j)) 308 continue; 309 /* VCN DEC TRAP */ 310 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 311 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq); 312 if (r) 313 return r; 314 315 /* VCN ENC TRAP */ 316 for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) { 317 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 318 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq); 319 if (r) 320 return r; 321 } 322 323 /* VCN POISON TRAP */ 324 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j], 325 VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq); 326 if (r) 327 return r; 328 329 r = amdgpu_vcn_sw_init(adev, j); 330 if (r) 331 return r; 332 333 /* Override the work func */ 334 adev->vcn.inst[j].idle_work.work.func = vcn_v2_5_idle_work_handler; 335 336 amdgpu_vcn_setup_ucode(adev, j); 337 338 r = amdgpu_vcn_resume(adev, j); 339 if (r) 340 return r; 341 342 adev->vcn.inst[j].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 343 adev->vcn.inst[j].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 344 adev->vcn.inst[j].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 345 adev->vcn.inst[j].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 346 adev->vcn.inst[j].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 347 adev->vcn.inst[j].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 348 349 adev->vcn.inst[j].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 350 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); 351 adev->vcn.inst[j].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 352 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); 353 adev->vcn.inst[j].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 354 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); 355 adev->vcn.inst[j].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 356 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); 357 adev->vcn.inst[j].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 358 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); 359 360 ring = &adev->vcn.inst[j].ring_dec; 361 ring->use_doorbell = true; 362 363 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 364 (amdgpu_sriov_vf(adev) ? 2*j : 8*j); 365 366 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0)) 367 ring->vm_hub = AMDGPU_MMHUB1(0); 368 else 369 ring->vm_hub = AMDGPU_MMHUB0(0); 370 371 sprintf(ring->name, "vcn_dec_%d", j); 372 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq, 373 0, AMDGPU_RING_PRIO_DEFAULT, NULL); 374 if (r) 375 return r; 376 377 for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) { 378 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 379 380 ring = &adev->vcn.inst[j].ring_enc[i]; 381 ring->use_doorbell = true; 382 383 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 384 (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j)); 385 386 if (amdgpu_ip_version(adev, UVD_HWIP, 0) == 387 IP_VERSION(2, 5, 0)) 388 ring->vm_hub = AMDGPU_MMHUB1(0); 389 else 390 ring->vm_hub = AMDGPU_MMHUB0(0); 391 392 sprintf(ring->name, "vcn_enc_%d.%d", j, i); 393 r = amdgpu_ring_init(adev, ring, 512, 394 &adev->vcn.inst[j].irq, 0, 395 hw_prio, NULL); 396 if (r) 397 return r; 398 } 399 400 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr; 401 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 402 403 if (amdgpu_vcnfw_log) 404 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); 405 406 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 407 adev->vcn.inst[j].pause_dpg_mode = vcn_v2_5_pause_dpg_mode; 408 adev->vcn.inst[j].reset = vcn_v2_5_reset; 409 } 410 411 adev->vcn.supported_reset = 412 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 413 if (!amdgpu_sriov_vf(adev)) 414 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 415 416 if (amdgpu_sriov_vf(adev)) { 417 r = amdgpu_virt_alloc_mm_table(adev); 418 if (r) 419 return r; 420 } 421 422 r = amdgpu_vcn_ras_sw_init(adev); 423 if (r) 424 return r; 425 426 /* Allocate memory for VCN IP Dump buffer */ 427 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 428 if (!ptr) { 429 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 430 adev->vcn.ip_dump = NULL; 431 } else { 432 adev->vcn.ip_dump = ptr; 433 } 434 435 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 436 if (r) 437 return r; 438 439 return 0; 440 } 441 442 /** 443 * vcn_v2_5_sw_fini - sw fini for VCN block 444 * 445 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 446 * 447 * VCN suspend and free up sw allocation 448 */ 449 static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) 450 { 451 int i, r, idx; 452 struct amdgpu_device *adev = ip_block->adev; 453 volatile struct amdgpu_fw_shared *fw_shared; 454 455 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 456 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 457 if (adev->vcn.harvest_config & (1 << i)) 458 continue; 459 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; 460 fw_shared->present_flag_0 = 0; 461 } 462 drm_dev_exit(idx); 463 } 464 465 466 if (amdgpu_sriov_vf(adev)) 467 amdgpu_virt_free_mm_table(adev); 468 469 amdgpu_vcn_sysfs_reset_mask_fini(adev); 470 471 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 472 r = amdgpu_vcn_suspend(adev, i); 473 if (r) 474 return r; 475 r = amdgpu_vcn_sw_fini(adev, i); 476 if (r) 477 return r; 478 } 479 480 kfree(adev->vcn.ip_dump); 481 482 return 0; 483 } 484 485 /** 486 * vcn_v2_5_hw_init - start and test VCN block 487 * 488 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 489 * 490 * Initialize the hardware, boot up the VCPU and do some testing 491 */ 492 static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block) 493 { 494 struct amdgpu_device *adev = ip_block->adev; 495 struct amdgpu_ring *ring; 496 int i, j, r = 0; 497 498 if (amdgpu_sriov_vf(adev)) 499 r = vcn_v2_5_sriov_start(adev); 500 501 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 502 if (adev->vcn.harvest_config & (1 << j)) 503 continue; 504 505 if (amdgpu_sriov_vf(adev)) { 506 adev->vcn.inst[j].ring_enc[0].sched.ready = true; 507 adev->vcn.inst[j].ring_enc[1].sched.ready = false; 508 adev->vcn.inst[j].ring_enc[2].sched.ready = false; 509 adev->vcn.inst[j].ring_dec.sched.ready = true; 510 } else { 511 512 ring = &adev->vcn.inst[j].ring_dec; 513 514 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 515 ring->doorbell_index, j); 516 517 r = amdgpu_ring_test_helper(ring); 518 if (r) 519 return r; 520 521 for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) { 522 ring = &adev->vcn.inst[j].ring_enc[i]; 523 r = amdgpu_ring_test_helper(ring); 524 if (r) 525 return r; 526 } 527 } 528 } 529 530 return r; 531 } 532 533 /** 534 * vcn_v2_5_hw_fini - stop the hardware block 535 * 536 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 537 * 538 * Stop the VCN block, mark ring as not ready any more 539 */ 540 static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) 541 { 542 struct amdgpu_device *adev = ip_block->adev; 543 int i; 544 545 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 546 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 547 548 if (adev->vcn.harvest_config & (1 << i)) 549 continue; 550 551 cancel_delayed_work_sync(&vinst->idle_work); 552 553 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 554 (vinst->cur_state != AMD_PG_STATE_GATE && 555 RREG32_SOC15(VCN, i, mmUVD_STATUS))) 556 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 557 558 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) 559 amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0); 560 } 561 562 return 0; 563 } 564 565 /** 566 * vcn_v2_5_suspend - suspend VCN block 567 * 568 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 569 * 570 * HW fini and suspend VCN block 571 */ 572 static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) 573 { 574 struct amdgpu_device *adev = ip_block->adev; 575 int r, i; 576 577 r = vcn_v2_5_hw_fini(ip_block); 578 if (r) 579 return r; 580 581 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 582 r = amdgpu_vcn_suspend(ip_block->adev, i); 583 if (r) 584 return r; 585 } 586 587 return 0; 588 } 589 590 /** 591 * vcn_v2_5_resume - resume VCN block 592 * 593 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 594 * 595 * Resume firmware and hw init VCN block 596 */ 597 static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block) 598 { 599 struct amdgpu_device *adev = ip_block->adev; 600 int r, i; 601 602 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 603 r = amdgpu_vcn_resume(ip_block->adev, i); 604 if (r) 605 return r; 606 } 607 608 r = vcn_v2_5_hw_init(ip_block); 609 610 return r; 611 } 612 613 /** 614 * vcn_v2_5_mc_resume - memory controller programming 615 * 616 * @vinst: VCN instance 617 * 618 * Let the VCN memory controller know it's offsets 619 */ 620 static void vcn_v2_5_mc_resume(struct amdgpu_vcn_inst *vinst) 621 { 622 struct amdgpu_device *adev = vinst->adev; 623 int i = vinst->inst; 624 uint32_t size; 625 uint32_t offset; 626 627 if (adev->vcn.harvest_config & (1 << i)) 628 return; 629 630 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 631 /* cache window 0: fw */ 632 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 633 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 634 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); 635 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 636 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); 637 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 638 offset = 0; 639 } else { 640 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 641 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 642 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 643 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 644 offset = size; 645 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 646 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 647 } 648 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); 649 650 /* cache window 1: stack */ 651 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 652 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 653 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 654 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 655 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); 656 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 657 658 /* cache window 2: context */ 659 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 660 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 661 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 662 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 663 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); 664 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 665 666 /* non-cache window */ 667 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 668 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 669 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 670 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr)); 671 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 672 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, 673 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 674 } 675 676 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 677 bool indirect) 678 { 679 struct amdgpu_device *adev = vinst->adev; 680 int inst_idx = vinst->inst; 681 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[inst_idx].fw->size + 4); 682 uint32_t offset; 683 684 /* cache window 0: fw */ 685 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 686 if (!indirect) { 687 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 688 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 689 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 690 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 691 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 692 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 693 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 694 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 695 } else { 696 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 697 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 698 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 699 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 700 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 701 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 702 } 703 offset = 0; 704 } else { 705 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 706 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 707 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 708 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 709 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 710 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 711 offset = size; 712 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 713 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 714 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 715 } 716 717 if (!indirect) 718 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 719 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 720 else 721 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 722 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 723 724 /* cache window 1: stack */ 725 if (!indirect) { 726 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 727 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 728 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 729 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 730 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 731 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 732 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 733 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 734 } else { 735 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 736 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 737 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 738 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 739 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 740 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 741 } 742 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 743 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 744 745 /* cache window 2: context */ 746 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 747 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 748 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 749 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 750 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 751 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 752 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 753 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 754 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 755 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 756 757 /* non-cache window */ 758 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 759 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 760 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 761 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 762 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 763 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); 764 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 765 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 766 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 767 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), 768 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 769 770 /* VCN global tiling registers */ 771 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 772 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 773 } 774 775 /** 776 * vcn_v2_5_disable_clock_gating - disable VCN clock gating 777 * 778 * @vinst: VCN instance 779 * 780 * Disable clock gating for VCN block 781 */ 782 static void vcn_v2_5_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 783 { 784 struct amdgpu_device *adev = vinst->adev; 785 int i = vinst->inst; 786 uint32_t data; 787 788 if (adev->vcn.harvest_config & (1 << i)) 789 return; 790 /* UVD disable CGC */ 791 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 792 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 793 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 794 else 795 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 796 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 797 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 798 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 799 800 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); 801 data &= ~(UVD_CGC_GATE__SYS_MASK 802 | UVD_CGC_GATE__UDEC_MASK 803 | UVD_CGC_GATE__MPEG2_MASK 804 | UVD_CGC_GATE__REGS_MASK 805 | UVD_CGC_GATE__RBC_MASK 806 | UVD_CGC_GATE__LMI_MC_MASK 807 | UVD_CGC_GATE__LMI_UMC_MASK 808 | UVD_CGC_GATE__IDCT_MASK 809 | UVD_CGC_GATE__MPRD_MASK 810 | UVD_CGC_GATE__MPC_MASK 811 | UVD_CGC_GATE__LBSI_MASK 812 | UVD_CGC_GATE__LRBBM_MASK 813 | UVD_CGC_GATE__UDEC_RE_MASK 814 | UVD_CGC_GATE__UDEC_CM_MASK 815 | UVD_CGC_GATE__UDEC_IT_MASK 816 | UVD_CGC_GATE__UDEC_DB_MASK 817 | UVD_CGC_GATE__UDEC_MP_MASK 818 | UVD_CGC_GATE__WCB_MASK 819 | UVD_CGC_GATE__VCPU_MASK 820 | UVD_CGC_GATE__MMSCH_MASK); 821 822 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); 823 824 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 825 826 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 827 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 828 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 829 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 830 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 831 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 832 | UVD_CGC_CTRL__SYS_MODE_MASK 833 | UVD_CGC_CTRL__UDEC_MODE_MASK 834 | UVD_CGC_CTRL__MPEG2_MODE_MASK 835 | UVD_CGC_CTRL__REGS_MODE_MASK 836 | UVD_CGC_CTRL__RBC_MODE_MASK 837 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 838 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 839 | UVD_CGC_CTRL__IDCT_MODE_MASK 840 | UVD_CGC_CTRL__MPRD_MODE_MASK 841 | UVD_CGC_CTRL__MPC_MODE_MASK 842 | UVD_CGC_CTRL__LBSI_MODE_MASK 843 | UVD_CGC_CTRL__LRBBM_MODE_MASK 844 | UVD_CGC_CTRL__WCB_MODE_MASK 845 | UVD_CGC_CTRL__VCPU_MODE_MASK 846 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 847 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 848 849 /* turn on */ 850 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); 851 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 852 | UVD_SUVD_CGC_GATE__SIT_MASK 853 | UVD_SUVD_CGC_GATE__SMP_MASK 854 | UVD_SUVD_CGC_GATE__SCM_MASK 855 | UVD_SUVD_CGC_GATE__SDB_MASK 856 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 857 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 858 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 859 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 860 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 861 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 862 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 863 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 864 | UVD_SUVD_CGC_GATE__SCLR_MASK 865 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 866 | UVD_SUVD_CGC_GATE__ENT_MASK 867 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 868 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 869 | UVD_SUVD_CGC_GATE__SITE_MASK 870 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 871 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 872 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 873 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 874 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 875 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); 876 877 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 878 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 879 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 880 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 881 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 882 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 883 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 884 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 885 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 886 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 887 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 888 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 889 } 890 891 static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 892 uint8_t sram_sel, uint8_t indirect) 893 { 894 struct amdgpu_device *adev = vinst->adev; 895 int inst_idx = vinst->inst; 896 uint32_t reg_data = 0; 897 898 /* enable sw clock gating control */ 899 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 900 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 901 else 902 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 903 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 904 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 905 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 906 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 907 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 908 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 909 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 910 UVD_CGC_CTRL__SYS_MODE_MASK | 911 UVD_CGC_CTRL__UDEC_MODE_MASK | 912 UVD_CGC_CTRL__MPEG2_MODE_MASK | 913 UVD_CGC_CTRL__REGS_MODE_MASK | 914 UVD_CGC_CTRL__RBC_MODE_MASK | 915 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 916 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 917 UVD_CGC_CTRL__IDCT_MODE_MASK | 918 UVD_CGC_CTRL__MPRD_MODE_MASK | 919 UVD_CGC_CTRL__MPC_MODE_MASK | 920 UVD_CGC_CTRL__LBSI_MODE_MASK | 921 UVD_CGC_CTRL__LRBBM_MODE_MASK | 922 UVD_CGC_CTRL__WCB_MODE_MASK | 923 UVD_CGC_CTRL__VCPU_MODE_MASK | 924 UVD_CGC_CTRL__MMSCH_MODE_MASK); 925 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 926 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 927 928 /* turn off clock gating */ 929 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 930 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 931 932 /* turn on SUVD clock gating */ 933 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 934 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 935 936 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 937 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 938 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 939 } 940 941 /** 942 * vcn_v2_5_enable_clock_gating - enable VCN clock gating 943 * 944 * @vinst: VCN instance 945 * 946 * Enable clock gating for VCN block 947 */ 948 static void vcn_v2_5_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 949 { 950 struct amdgpu_device *adev = vinst->adev; 951 int i = vinst->inst; 952 uint32_t data = 0; 953 954 if (adev->vcn.harvest_config & (1 << i)) 955 return; 956 /* enable UVD CGC */ 957 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 958 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 959 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 960 else 961 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 962 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 963 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 964 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 965 966 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); 967 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 968 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 969 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 970 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 971 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 972 | UVD_CGC_CTRL__SYS_MODE_MASK 973 | UVD_CGC_CTRL__UDEC_MODE_MASK 974 | UVD_CGC_CTRL__MPEG2_MODE_MASK 975 | UVD_CGC_CTRL__REGS_MODE_MASK 976 | UVD_CGC_CTRL__RBC_MODE_MASK 977 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 978 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 979 | UVD_CGC_CTRL__IDCT_MODE_MASK 980 | UVD_CGC_CTRL__MPRD_MODE_MASK 981 | UVD_CGC_CTRL__MPC_MODE_MASK 982 | UVD_CGC_CTRL__LBSI_MODE_MASK 983 | UVD_CGC_CTRL__LRBBM_MODE_MASK 984 | UVD_CGC_CTRL__WCB_MODE_MASK 985 | UVD_CGC_CTRL__VCPU_MODE_MASK); 986 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); 987 988 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); 989 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 990 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 991 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 992 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 993 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 994 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 995 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 996 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 997 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 998 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 999 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); 1000 } 1001 1002 static void vcn_v2_6_enable_ras(struct amdgpu_vcn_inst *vinst, 1003 bool indirect) 1004 { 1005 struct amdgpu_device *adev = vinst->adev; 1006 int inst_idx = vinst->inst; 1007 uint32_t tmp; 1008 1009 if (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(2, 6, 0)) 1010 return; 1011 1012 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK | 1013 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK | 1014 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK | 1015 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK; 1016 WREG32_SOC15_DPG_MODE(inst_idx, 1017 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), 1018 tmp, 0, indirect); 1019 1020 tmp = UVD_VCPU_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 1021 WREG32_SOC15_DPG_MODE(inst_idx, 1022 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), 1023 tmp, 0, indirect); 1024 1025 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK; 1026 WREG32_SOC15_DPG_MODE(inst_idx, 1027 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), 1028 tmp, 0, indirect); 1029 } 1030 1031 static int vcn_v2_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 1032 { 1033 struct amdgpu_device *adev = vinst->adev; 1034 int inst_idx = vinst->inst; 1035 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1036 struct amdgpu_ring *ring; 1037 uint32_t rb_bufsz, tmp; 1038 int ret; 1039 1040 /* disable register anti-hang mechanism */ 1041 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 1042 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1043 /* enable dynamic power gating mode */ 1044 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 1045 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 1046 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 1047 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 1048 1049 if (indirect) 1050 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 1051 1052 /* enable clock gating */ 1053 vcn_v2_5_clock_gating_dpg_mode(vinst, 0, indirect); 1054 1055 /* enable VCPU clock */ 1056 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1057 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1058 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 1059 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1060 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1061 1062 /* disable master interupt */ 1063 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1064 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 1065 1066 /* setup mmUVD_LMI_CTRL */ 1067 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1068 UVD_LMI_CTRL__REQ_MODE_MASK | 1069 UVD_LMI_CTRL__CRC_RESET_MASK | 1070 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1071 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1072 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1073 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1074 0x00100000L); 1075 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1076 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 1077 1078 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1079 VCN, 0, mmUVD_MPC_CNTL), 1080 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 1081 1082 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1083 VCN, 0, mmUVD_MPC_SET_MUXA0), 1084 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1085 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1086 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1087 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 1088 1089 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1090 VCN, 0, mmUVD_MPC_SET_MUXB0), 1091 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1092 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1093 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1094 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 1095 1096 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1097 VCN, 0, mmUVD_MPC_SET_MUX), 1098 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1099 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1100 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 1101 1102 vcn_v2_5_mc_resume_dpg_mode(vinst, indirect); 1103 1104 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1105 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 1106 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1107 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 1108 1109 /* enable LMI MC and UMC channels */ 1110 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1111 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); 1112 1113 vcn_v2_6_enable_ras(vinst, indirect); 1114 1115 /* unblock VCPU register access */ 1116 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1117 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 1118 1119 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 1120 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 1121 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1122 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 1123 1124 /* enable master interrupt */ 1125 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 1126 VCN, 0, mmUVD_MASTINT_EN), 1127 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 1128 1129 if (indirect) { 1130 ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); 1131 if (ret) { 1132 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 1133 return ret; 1134 } 1135 } 1136 1137 ring = &adev->vcn.inst[inst_idx].ring_dec; 1138 /* force RBC into idle state */ 1139 rb_bufsz = order_base_2(ring->ring_size); 1140 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1141 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1142 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1143 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1144 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1145 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1146 1147 /* Stall DPG before WPTR/RPTR reset */ 1148 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1149 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1150 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1151 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1152 1153 /* set the write pointer delay */ 1154 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1155 1156 /* set the wb address */ 1157 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1158 (upper_32_bits(ring->gpu_addr) >> 2)); 1159 1160 /* program the RB_BASE for ring buffer */ 1161 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1162 lower_32_bits(ring->gpu_addr)); 1163 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1164 upper_32_bits(ring->gpu_addr)); 1165 1166 /* Initialize the ring buffer's read and write pointers */ 1167 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1168 1169 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1170 1171 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1172 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1173 lower_32_bits(ring->wptr)); 1174 1175 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1176 /* Unstall DPG */ 1177 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1178 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1179 1180 /* Keeping one read-back to ensure all register writes are done, 1181 * otherwise it may introduce race conditions. 1182 */ 1183 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1184 1185 return 0; 1186 } 1187 1188 static int vcn_v2_5_start(struct amdgpu_vcn_inst *vinst) 1189 { 1190 struct amdgpu_device *adev = vinst->adev; 1191 int i = vinst->inst; 1192 volatile struct amdgpu_fw_shared *fw_shared = 1193 adev->vcn.inst[i].fw_shared.cpu_addr; 1194 struct amdgpu_ring *ring; 1195 uint32_t rb_bufsz, tmp; 1196 int j, k, r; 1197 1198 if (adev->vcn.harvest_config & (1 << i)) 1199 return 0; 1200 1201 if (adev->pm.dpm_enabled) 1202 amdgpu_dpm_enable_vcn(adev, true, i); 1203 1204 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1205 return vcn_v2_5_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); 1206 1207 /* disable register anti-hang mechanism */ 1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, 1209 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1210 1211 /* set uvd status busy */ 1212 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1213 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1214 1215 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1216 return 0; 1217 1218 /* SW clock gating */ 1219 vcn_v2_5_disable_clock_gating(vinst); 1220 1221 /* enable VCPU clock */ 1222 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1223 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1224 1225 /* disable master interrupt */ 1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1227 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1228 1229 /* setup mmUVD_LMI_CTRL */ 1230 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1231 tmp &= ~0xff; 1232 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| 1233 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1234 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1235 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1236 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1237 1238 /* setup mmUVD_MPC_CNTL */ 1239 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1240 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1241 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1242 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1243 1244 /* setup UVD_MPC_SET_MUXA0 */ 1245 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1246 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1247 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1248 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1249 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1250 1251 /* setup UVD_MPC_SET_MUXB0 */ 1252 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1253 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1254 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1255 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1256 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1257 1258 /* setup mmUVD_MPC_SET_MUX */ 1259 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1260 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1261 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1262 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1263 1264 vcn_v2_5_mc_resume(vinst); 1265 1266 /* VCN global tiling registers */ 1267 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1268 adev->gfx.config.gb_addr_config); 1269 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, 1270 adev->gfx.config.gb_addr_config); 1271 1272 /* enable LMI MC and UMC channels */ 1273 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1274 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1275 1276 /* unblock VCPU register access */ 1277 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1278 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1279 1280 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1281 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1282 1283 for (k = 0; k < 10; ++k) { 1284 uint32_t status; 1285 1286 for (j = 0; j < 100; ++j) { 1287 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1288 if (status & 2) 1289 break; 1290 if (amdgpu_emu_mode == 1) 1291 msleep(500); 1292 else 1293 mdelay(10); 1294 } 1295 r = 0; 1296 if (status & 2) 1297 break; 1298 1299 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1300 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1301 UVD_VCPU_CNTL__BLK_RST_MASK, 1302 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1303 mdelay(10); 1304 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1305 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1306 1307 mdelay(10); 1308 r = -1; 1309 } 1310 1311 if (r) { 1312 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1313 return r; 1314 } 1315 1316 /* enable master interrupt */ 1317 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1318 UVD_MASTINT_EN__VCPU_EN_MASK, 1319 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1320 1321 /* clear the busy bit of VCN_STATUS */ 1322 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1323 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1324 1325 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1326 1327 ring = &adev->vcn.inst[i].ring_dec; 1328 /* force RBC into idle state */ 1329 rb_bufsz = order_base_2(ring->ring_size); 1330 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1331 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1332 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1333 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1334 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1335 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1336 1337 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1338 /* program the RB_BASE for ring buffer */ 1339 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1340 lower_32_bits(ring->gpu_addr)); 1341 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1342 upper_32_bits(ring->gpu_addr)); 1343 1344 /* Initialize the ring buffer's read and write pointers */ 1345 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1346 1347 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1348 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1349 lower_32_bits(ring->wptr)); 1350 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1351 1352 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1353 ring = &adev->vcn.inst[i].ring_enc[0]; 1354 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1355 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1356 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1357 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1358 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1359 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1360 1361 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1362 ring = &adev->vcn.inst[i].ring_enc[1]; 1363 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1364 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1365 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1366 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1367 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1368 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1369 1370 /* Keeping one read-back to ensure all register writes are done, 1371 * otherwise it may introduce race conditions. 1372 */ 1373 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1374 1375 return 0; 1376 } 1377 1378 static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev, 1379 struct amdgpu_mm_table *table) 1380 { 1381 uint32_t data = 0, loop = 0, size = 0; 1382 uint64_t addr = table->gpu_addr; 1383 struct mmsch_v1_1_init_header *header = NULL; 1384 1385 header = (struct mmsch_v1_1_init_header *)table->cpu_addr; 1386 size = header->total_size; 1387 1388 /* 1389 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of 1390 * memory descriptor location 1391 */ 1392 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1394 1395 /* 2, update vmid of descriptor */ 1396 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1397 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1398 /* use domain0 for MM scheduler */ 1399 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1400 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); 1401 1402 /* 3, notify mmsch about the size of this descriptor */ 1403 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1404 1405 /* 4, set resp to zero */ 1406 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1407 1408 /* 1409 * 5, kick off the initialization and wait until 1410 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1411 */ 1412 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1413 1414 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1415 loop = 10; 1416 while ((data & 0x10000002) != 0x10000002) { 1417 udelay(100); 1418 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1419 loop--; 1420 if (!loop) 1421 break; 1422 } 1423 1424 if (!loop) { 1425 dev_err(adev->dev, 1426 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n", 1427 data); 1428 return -EBUSY; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev) 1435 { 1436 struct amdgpu_ring *ring; 1437 uint32_t offset, size, tmp, i, rb_bufsz; 1438 uint32_t table_size = 0; 1439 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } }; 1440 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } }; 1441 struct mmsch_v1_0_cmd_end end = { { 0 } }; 1442 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1443 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table; 1444 1445 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1446 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1447 end.cmd_header.command_type = MMSCH_COMMAND__END; 1448 1449 header->version = MMSCH_VERSION; 1450 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2; 1451 init_table += header->total_size; 1452 1453 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1454 header->eng[i].table_offset = header->total_size; 1455 header->eng[i].init_status = 0; 1456 header->eng[i].table_size = 0; 1457 1458 table_size = 0; 1459 1460 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( 1461 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 1462 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1463 1464 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[i].fw->size + 4); 1465 /* mc resume*/ 1466 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1467 MMSCH_V1_0_INSERT_DIRECT_WT( 1468 SOC15_REG_OFFSET(VCN, i, 1469 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1470 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo); 1471 MMSCH_V1_0_INSERT_DIRECT_WT( 1472 SOC15_REG_OFFSET(VCN, i, 1473 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1474 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi); 1475 offset = 0; 1476 MMSCH_V1_0_INSERT_DIRECT_WT( 1477 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); 1478 } else { 1479 MMSCH_V1_0_INSERT_DIRECT_WT( 1480 SOC15_REG_OFFSET(VCN, i, 1481 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1482 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1483 MMSCH_V1_0_INSERT_DIRECT_WT( 1484 SOC15_REG_OFFSET(VCN, i, 1485 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1486 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1487 offset = size; 1488 MMSCH_V1_0_INSERT_DIRECT_WT( 1489 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 1490 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1491 } 1492 1493 MMSCH_V1_0_INSERT_DIRECT_WT( 1494 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), 1495 size); 1496 MMSCH_V1_0_INSERT_DIRECT_WT( 1497 SOC15_REG_OFFSET(VCN, i, 1498 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1499 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1500 MMSCH_V1_0_INSERT_DIRECT_WT( 1501 SOC15_REG_OFFSET(VCN, i, 1502 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1503 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 1504 MMSCH_V1_0_INSERT_DIRECT_WT( 1505 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), 1506 0); 1507 MMSCH_V1_0_INSERT_DIRECT_WT( 1508 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), 1509 AMDGPU_VCN_STACK_SIZE); 1510 MMSCH_V1_0_INSERT_DIRECT_WT( 1511 SOC15_REG_OFFSET(VCN, i, 1512 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1513 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1514 AMDGPU_VCN_STACK_SIZE)); 1515 MMSCH_V1_0_INSERT_DIRECT_WT( 1516 SOC15_REG_OFFSET(VCN, i, 1517 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1518 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + 1519 AMDGPU_VCN_STACK_SIZE)); 1520 MMSCH_V1_0_INSERT_DIRECT_WT( 1521 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), 1522 0); 1523 MMSCH_V1_0_INSERT_DIRECT_WT( 1524 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), 1525 AMDGPU_VCN_CONTEXT_SIZE); 1526 1527 ring = &adev->vcn.inst[i].ring_enc[0]; 1528 ring->wptr = 0; 1529 1530 MMSCH_V1_0_INSERT_DIRECT_WT( 1531 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), 1532 lower_32_bits(ring->gpu_addr)); 1533 MMSCH_V1_0_INSERT_DIRECT_WT( 1534 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), 1535 upper_32_bits(ring->gpu_addr)); 1536 MMSCH_V1_0_INSERT_DIRECT_WT( 1537 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), 1538 ring->ring_size / 4); 1539 1540 ring = &adev->vcn.inst[i].ring_dec; 1541 ring->wptr = 0; 1542 MMSCH_V1_0_INSERT_DIRECT_WT( 1543 SOC15_REG_OFFSET(VCN, i, 1544 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1545 lower_32_bits(ring->gpu_addr)); 1546 MMSCH_V1_0_INSERT_DIRECT_WT( 1547 SOC15_REG_OFFSET(VCN, i, 1548 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1549 upper_32_bits(ring->gpu_addr)); 1550 1551 /* force RBC into idle state */ 1552 rb_bufsz = order_base_2(ring->ring_size); 1553 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1554 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1555 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1556 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1557 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1558 MMSCH_V1_0_INSERT_DIRECT_WT( 1559 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); 1560 1561 /* add end packet */ 1562 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 1563 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1564 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4; 1565 1566 /* refine header */ 1567 header->eng[i].table_size = table_size; 1568 header->total_size += table_size; 1569 } 1570 1571 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table); 1572 } 1573 1574 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1575 { 1576 struct amdgpu_device *adev = vinst->adev; 1577 int inst_idx = vinst->inst; 1578 uint32_t tmp; 1579 1580 /* Wait for power status to be 1 */ 1581 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1582 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1583 1584 /* wait for read ptr to be equal to write ptr */ 1585 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1586 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1587 1588 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1589 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1590 1591 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1592 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1593 1594 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1595 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1596 1597 /* disable dynamic power gating mode */ 1598 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1599 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1600 1601 /* Keeping one read-back to ensure all register writes are done, 1602 * otherwise it may introduce race conditions. 1603 */ 1604 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); 1605 1606 return 0; 1607 } 1608 1609 static int vcn_v2_5_stop(struct amdgpu_vcn_inst *vinst) 1610 { 1611 struct amdgpu_device *adev = vinst->adev; 1612 int i = vinst->inst; 1613 uint32_t tmp; 1614 int r; 1615 1616 if (adev->vcn.harvest_config & (1 << i)) 1617 return 0; 1618 1619 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1620 r = vcn_v2_5_stop_dpg_mode(vinst); 1621 goto done; 1622 } 1623 1624 /* wait for vcn idle */ 1625 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1626 if (r) 1627 goto done; 1628 1629 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1630 UVD_LMI_STATUS__READ_CLEAN_MASK | 1631 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1632 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1633 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1634 if (r) 1635 goto done; 1636 1637 /* block LMI UMC channel */ 1638 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1639 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1640 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1641 1642 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1643 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1644 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1645 if (r) 1646 goto done; 1647 1648 /* block VCPU register access */ 1649 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1650 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1651 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1652 1653 /* reset VCPU */ 1654 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1655 UVD_VCPU_CNTL__BLK_RST_MASK, 1656 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1657 1658 /* disable VCPU clock */ 1659 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1660 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1661 1662 /* clear status */ 1663 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1664 1665 vcn_v2_5_enable_clock_gating(vinst); 1666 1667 /* enable register anti-hang mechanism */ 1668 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 1669 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, 1670 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1671 1672 /* Keeping one read-back to ensure all register writes are done, 1673 * otherwise it may introduce race conditions. 1674 */ 1675 RREG32_SOC15(VCN, i, mmUVD_STATUS); 1676 done: 1677 if (adev->pm.dpm_enabled) 1678 amdgpu_dpm_enable_vcn(adev, false, i); 1679 1680 return r; 1681 } 1682 1683 static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1684 struct dpg_pause_state *new_state) 1685 { 1686 struct amdgpu_device *adev = vinst->adev; 1687 int inst_idx = vinst->inst; 1688 struct amdgpu_ring *ring; 1689 uint32_t reg_data = 0; 1690 int ret_code = 0; 1691 1692 /* pause/unpause if state is changed */ 1693 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1694 DRM_DEBUG("dpg pause state changed %d -> %d", 1695 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1696 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1697 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1698 1699 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1700 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1701 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1702 1703 if (!ret_code) { 1704 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 1705 1706 /* pause DPG */ 1707 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1708 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1709 1710 /* wait for ACK */ 1711 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1712 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1713 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1714 1715 /* Stall DPG before WPTR/RPTR reset */ 1716 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1717 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1718 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1719 1720 /* Restore */ 1721 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1722 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1723 ring->wptr = 0; 1724 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1725 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1726 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1727 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1728 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1729 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1730 1731 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1732 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1733 ring->wptr = 0; 1734 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1735 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1736 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1737 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1738 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1739 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1740 1741 /* Unstall DPG */ 1742 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1743 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1744 1745 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1746 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1747 } 1748 } else { 1749 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1750 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1751 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1752 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1753 } 1754 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1755 } 1756 1757 return 0; 1758 } 1759 1760 /** 1761 * vcn_v2_5_dec_ring_get_rptr - get read pointer 1762 * 1763 * @ring: amdgpu_ring pointer 1764 * 1765 * Returns the current hardware read pointer 1766 */ 1767 static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring) 1768 { 1769 struct amdgpu_device *adev = ring->adev; 1770 1771 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1772 } 1773 1774 /** 1775 * vcn_v2_5_dec_ring_get_wptr - get write pointer 1776 * 1777 * @ring: amdgpu_ring pointer 1778 * 1779 * Returns the current hardware write pointer 1780 */ 1781 static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring) 1782 { 1783 struct amdgpu_device *adev = ring->adev; 1784 1785 if (ring->use_doorbell) 1786 return *ring->wptr_cpu_addr; 1787 else 1788 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1789 } 1790 1791 /** 1792 * vcn_v2_5_dec_ring_set_wptr - set write pointer 1793 * 1794 * @ring: amdgpu_ring pointer 1795 * 1796 * Commits the write pointer to the hardware 1797 */ 1798 static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring) 1799 { 1800 struct amdgpu_device *adev = ring->adev; 1801 1802 if (ring->use_doorbell) { 1803 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1804 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1805 } else { 1806 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1807 } 1808 } 1809 1810 static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { 1811 .type = AMDGPU_RING_TYPE_VCN_DEC, 1812 .align_mask = 0xf, 1813 .secure_submission_supported = true, 1814 .get_rptr = vcn_v2_5_dec_ring_get_rptr, 1815 .get_wptr = vcn_v2_5_dec_ring_get_wptr, 1816 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1817 .emit_frame_size = 1818 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1819 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1820 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1821 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1822 6, 1823 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1824 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1825 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1826 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1827 .test_ring = vcn_v2_0_dec_ring_test_ring, 1828 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1829 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1830 .insert_start = vcn_v2_0_dec_ring_insert_start, 1831 .insert_end = vcn_v2_0_dec_ring_insert_end, 1832 .pad_ib = amdgpu_ring_generic_pad_ib, 1833 .begin_use = vcn_v2_5_ring_begin_use, 1834 .end_use = vcn_v2_5_ring_end_use, 1835 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1836 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1837 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1838 .reset = amdgpu_vcn_ring_reset, 1839 }; 1840 1841 /** 1842 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer 1843 * 1844 * @ring: amdgpu_ring pointer 1845 * 1846 * Returns the current hardware enc read pointer 1847 */ 1848 static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring) 1849 { 1850 struct amdgpu_device *adev = ring->adev; 1851 1852 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1853 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1854 else 1855 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1856 } 1857 1858 /** 1859 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer 1860 * 1861 * @ring: amdgpu_ring pointer 1862 * 1863 * Returns the current hardware enc write pointer 1864 */ 1865 static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring) 1866 { 1867 struct amdgpu_device *adev = ring->adev; 1868 1869 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1870 if (ring->use_doorbell) 1871 return *ring->wptr_cpu_addr; 1872 else 1873 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1874 } else { 1875 if (ring->use_doorbell) 1876 return *ring->wptr_cpu_addr; 1877 else 1878 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1879 } 1880 } 1881 1882 /** 1883 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer 1884 * 1885 * @ring: amdgpu_ring pointer 1886 * 1887 * Commits the enc write pointer to the hardware 1888 */ 1889 static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring) 1890 { 1891 struct amdgpu_device *adev = ring->adev; 1892 1893 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1894 if (ring->use_doorbell) { 1895 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1896 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1897 } else { 1898 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1899 } 1900 } else { 1901 if (ring->use_doorbell) { 1902 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1903 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1904 } else { 1905 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1906 } 1907 } 1908 } 1909 1910 static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { 1911 .type = AMDGPU_RING_TYPE_VCN_ENC, 1912 .align_mask = 0x3f, 1913 .nop = VCN_ENC_CMD_NO_OP, 1914 .get_rptr = vcn_v2_5_enc_ring_get_rptr, 1915 .get_wptr = vcn_v2_5_enc_ring_get_wptr, 1916 .set_wptr = vcn_v2_5_enc_ring_set_wptr, 1917 .emit_frame_size = 1918 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1919 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1920 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1921 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1922 1, /* vcn_v2_0_enc_ring_insert_end */ 1923 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1924 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1925 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1926 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1927 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1928 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1929 .insert_nop = amdgpu_ring_insert_nop, 1930 .insert_end = vcn_v2_0_enc_ring_insert_end, 1931 .pad_ib = amdgpu_ring_generic_pad_ib, 1932 .begin_use = vcn_v2_5_ring_begin_use, 1933 .end_use = vcn_v2_5_ring_end_use, 1934 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1935 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1936 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1937 .reset = amdgpu_vcn_ring_reset, 1938 }; 1939 1940 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev) 1941 { 1942 int i; 1943 1944 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1945 if (adev->vcn.harvest_config & (1 << i)) 1946 continue; 1947 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs; 1948 adev->vcn.inst[i].ring_dec.me = i; 1949 } 1950 } 1951 1952 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev) 1953 { 1954 int i, j; 1955 1956 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { 1957 if (adev->vcn.harvest_config & (1 << j)) 1958 continue; 1959 for (i = 0; i < adev->vcn.inst[j].num_enc_rings; ++i) { 1960 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs; 1961 adev->vcn.inst[j].ring_enc[i].me = j; 1962 } 1963 } 1964 } 1965 1966 static int vcn_v2_5_reset(struct amdgpu_vcn_inst *vinst) 1967 { 1968 int r; 1969 1970 r = vcn_v2_5_stop(vinst); 1971 if (r) 1972 return r; 1973 return vcn_v2_5_start(vinst); 1974 } 1975 1976 static bool vcn_v2_5_is_idle(struct amdgpu_ip_block *ip_block) 1977 { 1978 struct amdgpu_device *adev = ip_block->adev; 1979 int i, ret = 1; 1980 1981 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1982 if (adev->vcn.harvest_config & (1 << i)) 1983 continue; 1984 1985 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1986 } 1987 1988 return ret; 1989 } 1990 1991 static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) 1992 { 1993 struct amdgpu_device *adev = ip_block->adev; 1994 int i, ret = 0; 1995 1996 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1997 if (adev->vcn.harvest_config & (1 << i)) 1998 continue; 1999 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 2000 UVD_STATUS__IDLE); 2001 if (ret) 2002 return ret; 2003 } 2004 2005 return ret; 2006 } 2007 2008 static int vcn_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2009 enum amd_clockgating_state state) 2010 { 2011 struct amdgpu_device *adev = ip_block->adev; 2012 bool enable = (state == AMD_CG_STATE_GATE); 2013 int i; 2014 2015 if (amdgpu_sriov_vf(adev)) 2016 return 0; 2017 2018 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2019 struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; 2020 2021 if (enable) { 2022 if (!vcn_v2_5_is_idle(ip_block)) 2023 return -EBUSY; 2024 vcn_v2_5_enable_clock_gating(vinst); 2025 } else { 2026 vcn_v2_5_disable_clock_gating(vinst); 2027 } 2028 } 2029 2030 return 0; 2031 } 2032 2033 static int vcn_v2_5_set_pg_state(struct amdgpu_vcn_inst *vinst, 2034 enum amd_powergating_state state) 2035 { 2036 struct amdgpu_device *adev = vinst->adev; 2037 int ret; 2038 2039 if (amdgpu_sriov_vf(adev)) 2040 return 0; 2041 2042 if (state == vinst->cur_state) 2043 return 0; 2044 2045 if (state == AMD_PG_STATE_GATE) 2046 ret = vcn_v2_5_stop(vinst); 2047 else 2048 ret = vcn_v2_5_start(vinst); 2049 2050 if (!ret) 2051 vinst->cur_state = state; 2052 2053 return ret; 2054 } 2055 2056 static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev, 2057 struct amdgpu_irq_src *source, 2058 unsigned type, 2059 enum amdgpu_interrupt_state state) 2060 { 2061 return 0; 2062 } 2063 2064 static int vcn_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev, 2065 struct amdgpu_irq_src *source, 2066 unsigned int type, 2067 enum amdgpu_interrupt_state state) 2068 { 2069 return 0; 2070 } 2071 2072 static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev, 2073 struct amdgpu_irq_src *source, 2074 struct amdgpu_iv_entry *entry) 2075 { 2076 uint32_t ip_instance; 2077 2078 switch (entry->client_id) { 2079 case SOC15_IH_CLIENTID_VCN: 2080 ip_instance = 0; 2081 break; 2082 case SOC15_IH_CLIENTID_VCN1: 2083 ip_instance = 1; 2084 break; 2085 default: 2086 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 2087 return 0; 2088 } 2089 2090 DRM_DEBUG("IH: VCN TRAP\n"); 2091 2092 switch (entry->src_id) { 2093 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 2094 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 2095 break; 2096 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 2097 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 2098 break; 2099 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 2100 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 2101 break; 2102 default: 2103 DRM_ERROR("Unhandled interrupt: %d %d\n", 2104 entry->src_id, entry->src_data[0]); 2105 break; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = { 2112 .set = vcn_v2_5_set_interrupt_state, 2113 .process = vcn_v2_5_process_interrupt, 2114 }; 2115 2116 static const struct amdgpu_irq_src_funcs vcn_v2_6_ras_irq_funcs = { 2117 .set = vcn_v2_6_set_ras_interrupt_state, 2118 .process = amdgpu_vcn_process_poison_irq, 2119 }; 2120 2121 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) 2122 { 2123 int i; 2124 2125 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 2126 if (adev->vcn.harvest_config & (1 << i)) 2127 continue; 2128 adev->vcn.inst[i].irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2129 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs; 2130 2131 adev->vcn.inst[i].ras_poison_irq.num_types = adev->vcn.inst[i].num_enc_rings + 1; 2132 adev->vcn.inst[i].ras_poison_irq.funcs = &vcn_v2_6_ras_irq_funcs; 2133 } 2134 } 2135 2136 static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2137 { 2138 struct amdgpu_device *adev = ip_block->adev; 2139 int i, j; 2140 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 2141 uint32_t inst_off, is_powered; 2142 2143 if (!adev->vcn.ip_dump) 2144 return; 2145 2146 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2147 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2148 if (adev->vcn.harvest_config & (1 << i)) { 2149 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2150 continue; 2151 } 2152 2153 inst_off = i * reg_count; 2154 is_powered = (adev->vcn.ip_dump[inst_off] & 2155 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2156 2157 if (is_powered) { 2158 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2159 for (j = 0; j < reg_count; j++) 2160 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name, 2161 adev->vcn.ip_dump[inst_off + j]); 2162 } else { 2163 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2164 } 2165 } 2166 } 2167 2168 static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block) 2169 { 2170 struct amdgpu_device *adev = ip_block->adev; 2171 int i, j; 2172 bool is_powered; 2173 uint32_t inst_off; 2174 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 2175 2176 if (!adev->vcn.ip_dump) 2177 return; 2178 2179 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2180 if (adev->vcn.harvest_config & (1 << i)) 2181 continue; 2182 2183 inst_off = i * reg_count; 2184 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2185 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 2186 is_powered = (adev->vcn.ip_dump[inst_off] & 2187 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2188 2189 if (is_powered) 2190 for (j = 1; j < reg_count; j++) 2191 adev->vcn.ip_dump[inst_off + j] = 2192 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i)); 2193 } 2194 } 2195 2196 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 2197 .name = "vcn_v2_5", 2198 .early_init = vcn_v2_5_early_init, 2199 .sw_init = vcn_v2_5_sw_init, 2200 .sw_fini = vcn_v2_5_sw_fini, 2201 .hw_init = vcn_v2_5_hw_init, 2202 .hw_fini = vcn_v2_5_hw_fini, 2203 .suspend = vcn_v2_5_suspend, 2204 .resume = vcn_v2_5_resume, 2205 .is_idle = vcn_v2_5_is_idle, 2206 .wait_for_idle = vcn_v2_5_wait_for_idle, 2207 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 2208 .set_powergating_state = vcn_set_powergating_state, 2209 .dump_ip_state = vcn_v2_5_dump_ip_state, 2210 .print_ip_state = vcn_v2_5_print_ip_state, 2211 }; 2212 2213 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { 2214 .name = "vcn_v2_6", 2215 .early_init = vcn_v2_5_early_init, 2216 .sw_init = vcn_v2_5_sw_init, 2217 .sw_fini = vcn_v2_5_sw_fini, 2218 .hw_init = vcn_v2_5_hw_init, 2219 .hw_fini = vcn_v2_5_hw_fini, 2220 .suspend = vcn_v2_5_suspend, 2221 .resume = vcn_v2_5_resume, 2222 .is_idle = vcn_v2_5_is_idle, 2223 .wait_for_idle = vcn_v2_5_wait_for_idle, 2224 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 2225 .set_powergating_state = vcn_set_powergating_state, 2226 .dump_ip_state = vcn_v2_5_dump_ip_state, 2227 .print_ip_state = vcn_v2_5_print_ip_state, 2228 }; 2229 2230 const struct amdgpu_ip_block_version vcn_v2_5_ip_block = 2231 { 2232 .type = AMD_IP_BLOCK_TYPE_VCN, 2233 .major = 2, 2234 .minor = 5, 2235 .rev = 0, 2236 .funcs = &vcn_v2_5_ip_funcs, 2237 }; 2238 2239 const struct amdgpu_ip_block_version vcn_v2_6_ip_block = 2240 { 2241 .type = AMD_IP_BLOCK_TYPE_VCN, 2242 .major = 2, 2243 .minor = 6, 2244 .rev = 0, 2245 .funcs = &vcn_v2_6_ip_funcs, 2246 }; 2247 2248 static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev, 2249 uint32_t instance, uint32_t sub_block) 2250 { 2251 uint32_t poison_stat = 0, reg_value = 0; 2252 2253 switch (sub_block) { 2254 case AMDGPU_VCN_V2_6_VCPU_VCODEC: 2255 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); 2256 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF); 2257 break; 2258 default: 2259 break; 2260 } 2261 2262 if (poison_stat) 2263 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n", 2264 instance, sub_block); 2265 2266 return poison_stat; 2267 } 2268 2269 static bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev) 2270 { 2271 uint32_t inst, sub; 2272 uint32_t poison_stat = 0; 2273 2274 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++) 2275 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++) 2276 poison_stat += 2277 vcn_v2_6_query_poison_by_instance(adev, inst, sub); 2278 2279 return !!poison_stat; 2280 } 2281 2282 const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = { 2283 .query_poison_status = vcn_v2_6_query_poison_status, 2284 }; 2285 2286 static struct amdgpu_vcn_ras vcn_v2_6_ras = { 2287 .ras_block = { 2288 .hw_ops = &vcn_v2_6_ras_hw_ops, 2289 .ras_late_init = amdgpu_vcn_ras_late_init, 2290 }, 2291 }; 2292 2293 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev) 2294 { 2295 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 2296 case IP_VERSION(2, 6, 0): 2297 adev->vcn.ras = &vcn_v2_6_ras; 2298 break; 2299 default: 2300 break; 2301 } 2302 } 2303