1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_psp.h" 33 #include "mmsch_v2_0.h" 34 #include "vcn_v2_0.h" 35 36 #include "vcn/vcn_2_0_0_offset.h" 37 #include "vcn/vcn_2_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 #define VCN1_AON_SOC_ADDRESS_3_0 0x48000 43 44 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 45 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 46 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 47 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 48 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 49 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 50 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 51 52 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 54 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 55 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 56 57 static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = { 58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 63 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 68 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 70 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 84 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 85 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 89 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 90 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 91 }; 92 93 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 94 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 95 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 96 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 97 enum amd_powergating_state state); 98 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 99 struct dpg_pause_state *new_state); 100 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 101 static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst); 102 103 /** 104 * vcn_v2_0_early_init - set function pointers and load microcode 105 * 106 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 107 * 108 * Set ring and irq function pointers 109 * Load microcode from filesystem 110 */ 111 static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block) 112 { 113 struct amdgpu_device *adev = ip_block->adev; 114 115 if (amdgpu_sriov_vf(adev)) 116 adev->vcn.inst[0].num_enc_rings = 1; 117 else 118 adev->vcn.inst[0].num_enc_rings = 2; 119 120 adev->vcn.inst->set_pg_state = vcn_v2_0_set_pg_state; 121 vcn_v2_0_set_dec_ring_funcs(adev); 122 vcn_v2_0_set_enc_ring_funcs(adev); 123 vcn_v2_0_set_irq_funcs(adev); 124 125 return amdgpu_vcn_early_init(adev, 0); 126 } 127 128 /** 129 * vcn_v2_0_sw_init - sw init for VCN block 130 * 131 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 132 * 133 * Load firmware and sw initialization 134 */ 135 static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) 136 { 137 struct amdgpu_ring *ring; 138 int i, r; 139 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 140 uint32_t *ptr; 141 struct amdgpu_device *adev = ip_block->adev; 142 volatile struct amdgpu_fw_shared *fw_shared; 143 144 /* VCN DEC TRAP */ 145 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 146 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 147 &adev->vcn.inst->irq); 148 if (r) 149 return r; 150 151 /* VCN ENC TRAP */ 152 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 153 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 154 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 155 &adev->vcn.inst->irq); 156 if (r) 157 return r; 158 } 159 160 r = amdgpu_vcn_sw_init(adev, 0); 161 if (r) 162 return r; 163 164 amdgpu_vcn_setup_ucode(adev, 0); 165 166 r = amdgpu_vcn_resume(adev, 0); 167 if (r) 168 return r; 169 170 ring = &adev->vcn.inst->ring_dec; 171 172 ring->use_doorbell = true; 173 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 174 ring->vm_hub = AMDGPU_MMHUB0(0); 175 176 sprintf(ring->name, "vcn_dec"); 177 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 178 AMDGPU_RING_PRIO_DEFAULT, NULL); 179 if (r) 180 return r; 181 182 adev->vcn.inst[0].internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 183 adev->vcn.inst[0].internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 184 adev->vcn.inst[0].internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 185 adev->vcn.inst[0].internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 186 adev->vcn.inst[0].internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 187 adev->vcn.inst[0].internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 188 189 adev->vcn.inst[0].internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 190 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 191 adev->vcn.inst[0].internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 192 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 193 adev->vcn.inst[0].internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 194 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 195 adev->vcn.inst[0].internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 196 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 197 adev->vcn.inst[0].internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 198 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 199 200 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 201 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 202 203 ring = &adev->vcn.inst->ring_enc[i]; 204 ring->use_doorbell = true; 205 ring->vm_hub = AMDGPU_MMHUB0(0); 206 if (!amdgpu_sriov_vf(adev)) 207 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 208 else 209 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 210 sprintf(ring->name, "vcn_enc%d", i); 211 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 212 hw_prio, NULL); 213 if (r) 214 return r; 215 } 216 217 adev->vcn.inst[0].pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 218 adev->vcn.inst[0].reset = vcn_v2_0_reset; 219 220 adev->vcn.supported_reset = 221 amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); 222 if (!amdgpu_sriov_vf(adev)) 223 adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 224 225 r = amdgpu_virt_alloc_mm_table(adev); 226 if (r) 227 return r; 228 229 fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 230 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 231 232 if (amdgpu_vcnfw_log) 233 amdgpu_vcn_fwlog_init(adev->vcn.inst); 234 235 /* Allocate memory for VCN IP Dump buffer */ 236 ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 237 if (!ptr) { 238 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 239 adev->vcn.ip_dump = NULL; 240 } else { 241 adev->vcn.ip_dump = ptr; 242 } 243 244 r = amdgpu_vcn_sysfs_reset_mask_init(adev); 245 if (r) 246 return r; 247 248 return 0; 249 } 250 251 /** 252 * vcn_v2_0_sw_fini - sw fini for VCN block 253 * 254 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 255 * 256 * VCN suspend and free up sw allocation 257 */ 258 static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) 259 { 260 int r, idx; 261 struct amdgpu_device *adev = ip_block->adev; 262 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 263 264 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 265 fw_shared->present_flag_0 = 0; 266 drm_dev_exit(idx); 267 } 268 269 amdgpu_virt_free_mm_table(adev); 270 271 r = amdgpu_vcn_suspend(adev, 0); 272 if (r) 273 return r; 274 275 amdgpu_vcn_sysfs_reset_mask_fini(adev); 276 277 r = amdgpu_vcn_sw_fini(adev, 0); 278 279 kfree(adev->vcn.ip_dump); 280 281 return r; 282 } 283 284 /** 285 * vcn_v2_0_hw_init - start and test VCN block 286 * 287 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 288 * 289 * Initialize the hardware, boot up the VCPU and do some testing 290 */ 291 static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block) 292 { 293 struct amdgpu_device *adev = ip_block->adev; 294 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 295 int i, r; 296 297 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 298 ring->doorbell_index, 0); 299 300 if (amdgpu_sriov_vf(adev)) 301 vcn_v2_0_start_sriov(adev); 302 303 r = amdgpu_ring_test_helper(ring); 304 if (r) 305 return r; 306 307 //Disable vcn decode for sriov 308 if (amdgpu_sriov_vf(adev)) 309 ring->sched.ready = false; 310 311 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 312 ring = &adev->vcn.inst->ring_enc[i]; 313 r = amdgpu_ring_test_helper(ring); 314 if (r) 315 return r; 316 } 317 318 return 0; 319 } 320 321 /** 322 * vcn_v2_0_hw_fini - stop the hardware block 323 * 324 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 325 * 326 * Stop the VCN block, mark ring as not ready any more 327 */ 328 static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) 329 { 330 struct amdgpu_device *adev = ip_block->adev; 331 struct amdgpu_vcn_inst *vinst = adev->vcn.inst; 332 333 cancel_delayed_work_sync(&vinst->idle_work); 334 335 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 336 (vinst->cur_state != AMD_PG_STATE_GATE && 337 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 338 vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); 339 340 return 0; 341 } 342 343 /** 344 * vcn_v2_0_suspend - suspend VCN block 345 * 346 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 347 * 348 * HW fini and suspend VCN block 349 */ 350 static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) 351 { 352 int r; 353 354 r = vcn_v2_0_hw_fini(ip_block); 355 if (r) 356 return r; 357 358 r = amdgpu_vcn_suspend(ip_block->adev, 0); 359 360 return r; 361 } 362 363 /** 364 * vcn_v2_0_resume - resume VCN block 365 * 366 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 367 * 368 * Resume firmware and hw init VCN block 369 */ 370 static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block) 371 { 372 int r; 373 374 r = amdgpu_vcn_resume(ip_block->adev, 0); 375 if (r) 376 return r; 377 378 r = vcn_v2_0_hw_init(ip_block); 379 380 return r; 381 } 382 383 /** 384 * vcn_v2_0_mc_resume - memory controller programming 385 * 386 * @vinst: Pointer to the VCN instance structure 387 * 388 * Let the VCN memory controller know it's offsets 389 */ 390 static void vcn_v2_0_mc_resume(struct amdgpu_vcn_inst *vinst) 391 { 392 struct amdgpu_device *adev = vinst->adev; 393 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 394 uint32_t offset; 395 396 if (amdgpu_sriov_vf(adev)) 397 return; 398 399 /* cache window 0: fw */ 400 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 401 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 402 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 403 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 404 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 405 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 406 offset = 0; 407 } else { 408 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 409 lower_32_bits(adev->vcn.inst->gpu_addr)); 410 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 411 upper_32_bits(adev->vcn.inst->gpu_addr)); 412 offset = size; 413 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 414 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 415 } 416 417 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 418 419 /* cache window 1: stack */ 420 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 421 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 422 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 423 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 424 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 425 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 426 427 /* cache window 2: context */ 428 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 429 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 430 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 431 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 432 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 433 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 434 435 /* non-cache window */ 436 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 437 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 438 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 439 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 440 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 441 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 442 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 443 444 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 445 } 446 447 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, 448 bool indirect) 449 { 450 struct amdgpu_device *adev = vinst->adev; 451 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 452 uint32_t offset; 453 454 /* cache window 0: fw */ 455 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 456 if (!indirect) { 457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 459 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 460 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 461 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 463 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 464 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 465 } else { 466 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 467 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 468 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 469 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 470 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 471 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 472 } 473 offset = 0; 474 } else { 475 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 476 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 477 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 478 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 479 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 480 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 481 offset = size; 482 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 483 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 484 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 485 } 486 487 if (!indirect) 488 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 489 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 490 else 491 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 492 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 493 494 /* cache window 1: stack */ 495 if (!indirect) { 496 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 497 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 498 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 499 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 500 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 501 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 502 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 503 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 504 } else { 505 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 506 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 507 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 508 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 509 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 510 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 511 } 512 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 513 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 514 515 /* cache window 2: context */ 516 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 517 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 518 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 519 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 520 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 521 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 522 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 523 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 524 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 525 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 526 527 /* non-cache window */ 528 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 529 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 530 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 531 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 532 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 533 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 534 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 535 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 536 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 537 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 538 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 539 540 /* VCN global tiling registers */ 541 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 542 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 543 } 544 545 /** 546 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 547 * 548 * @vinst: VCN instance 549 * 550 * Disable clock gating for VCN block 551 */ 552 static void vcn_v2_0_disable_clock_gating(struct amdgpu_vcn_inst *vinst) 553 { 554 struct amdgpu_device *adev = vinst->adev; 555 uint32_t data; 556 557 if (amdgpu_sriov_vf(adev)) 558 return; 559 560 /* UVD disable CGC */ 561 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 562 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 563 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 564 else 565 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 566 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 567 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 568 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 569 570 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 571 data &= ~(UVD_CGC_GATE__SYS_MASK 572 | UVD_CGC_GATE__UDEC_MASK 573 | UVD_CGC_GATE__MPEG2_MASK 574 | UVD_CGC_GATE__REGS_MASK 575 | UVD_CGC_GATE__RBC_MASK 576 | UVD_CGC_GATE__LMI_MC_MASK 577 | UVD_CGC_GATE__LMI_UMC_MASK 578 | UVD_CGC_GATE__IDCT_MASK 579 | UVD_CGC_GATE__MPRD_MASK 580 | UVD_CGC_GATE__MPC_MASK 581 | UVD_CGC_GATE__LBSI_MASK 582 | UVD_CGC_GATE__LRBBM_MASK 583 | UVD_CGC_GATE__UDEC_RE_MASK 584 | UVD_CGC_GATE__UDEC_CM_MASK 585 | UVD_CGC_GATE__UDEC_IT_MASK 586 | UVD_CGC_GATE__UDEC_DB_MASK 587 | UVD_CGC_GATE__UDEC_MP_MASK 588 | UVD_CGC_GATE__WCB_MASK 589 | UVD_CGC_GATE__VCPU_MASK 590 | UVD_CGC_GATE__SCPU_MASK); 591 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 592 593 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 594 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 595 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 596 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 597 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 598 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 599 | UVD_CGC_CTRL__SYS_MODE_MASK 600 | UVD_CGC_CTRL__UDEC_MODE_MASK 601 | UVD_CGC_CTRL__MPEG2_MODE_MASK 602 | UVD_CGC_CTRL__REGS_MODE_MASK 603 | UVD_CGC_CTRL__RBC_MODE_MASK 604 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 605 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 606 | UVD_CGC_CTRL__IDCT_MODE_MASK 607 | UVD_CGC_CTRL__MPRD_MODE_MASK 608 | UVD_CGC_CTRL__MPC_MODE_MASK 609 | UVD_CGC_CTRL__LBSI_MODE_MASK 610 | UVD_CGC_CTRL__LRBBM_MODE_MASK 611 | UVD_CGC_CTRL__WCB_MODE_MASK 612 | UVD_CGC_CTRL__VCPU_MODE_MASK 613 | UVD_CGC_CTRL__SCPU_MODE_MASK); 614 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 615 616 /* turn on */ 617 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 618 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 619 | UVD_SUVD_CGC_GATE__SIT_MASK 620 | UVD_SUVD_CGC_GATE__SMP_MASK 621 | UVD_SUVD_CGC_GATE__SCM_MASK 622 | UVD_SUVD_CGC_GATE__SDB_MASK 623 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 624 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 625 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 626 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 627 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 628 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 629 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 630 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 631 | UVD_SUVD_CGC_GATE__SCLR_MASK 632 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 633 | UVD_SUVD_CGC_GATE__ENT_MASK 634 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 635 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 636 | UVD_SUVD_CGC_GATE__SITE_MASK 637 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 638 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 639 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 640 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 641 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 642 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 643 644 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 645 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 646 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 647 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 648 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 649 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 650 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 651 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 652 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 653 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 654 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 655 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 656 } 657 658 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_vcn_inst *vinst, 659 uint8_t sram_sel, uint8_t indirect) 660 { 661 struct amdgpu_device *adev = vinst->adev; 662 uint32_t reg_data = 0; 663 664 /* enable sw clock gating control */ 665 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 666 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 667 else 668 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 669 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 670 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 671 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 674 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 675 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 676 UVD_CGC_CTRL__SYS_MODE_MASK | 677 UVD_CGC_CTRL__UDEC_MODE_MASK | 678 UVD_CGC_CTRL__MPEG2_MODE_MASK | 679 UVD_CGC_CTRL__REGS_MODE_MASK | 680 UVD_CGC_CTRL__RBC_MODE_MASK | 681 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 682 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 683 UVD_CGC_CTRL__IDCT_MODE_MASK | 684 UVD_CGC_CTRL__MPRD_MODE_MASK | 685 UVD_CGC_CTRL__MPC_MODE_MASK | 686 UVD_CGC_CTRL__LBSI_MODE_MASK | 687 UVD_CGC_CTRL__LRBBM_MODE_MASK | 688 UVD_CGC_CTRL__WCB_MODE_MASK | 689 UVD_CGC_CTRL__VCPU_MODE_MASK | 690 UVD_CGC_CTRL__SCPU_MODE_MASK); 691 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 692 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 693 694 /* turn off clock gating */ 695 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 696 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 697 698 /* turn on SUVD clock gating */ 699 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 700 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 701 702 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 703 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 704 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 705 } 706 707 /** 708 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 709 * 710 * @vinst: VCN instance 711 * 712 * Enable clock gating for VCN block 713 */ 714 static void vcn_v2_0_enable_clock_gating(struct amdgpu_vcn_inst *vinst) 715 { 716 struct amdgpu_device *adev = vinst->adev; 717 uint32_t data = 0; 718 719 if (amdgpu_sriov_vf(adev)) 720 return; 721 722 /* enable UVD CGC */ 723 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 724 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 725 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 726 else 727 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 728 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 729 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 730 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 731 732 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 733 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 734 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 735 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 736 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 737 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 738 | UVD_CGC_CTRL__SYS_MODE_MASK 739 | UVD_CGC_CTRL__UDEC_MODE_MASK 740 | UVD_CGC_CTRL__MPEG2_MODE_MASK 741 | UVD_CGC_CTRL__REGS_MODE_MASK 742 | UVD_CGC_CTRL__RBC_MODE_MASK 743 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 744 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 745 | UVD_CGC_CTRL__IDCT_MODE_MASK 746 | UVD_CGC_CTRL__MPRD_MODE_MASK 747 | UVD_CGC_CTRL__MPC_MODE_MASK 748 | UVD_CGC_CTRL__LBSI_MODE_MASK 749 | UVD_CGC_CTRL__LRBBM_MODE_MASK 750 | UVD_CGC_CTRL__WCB_MODE_MASK 751 | UVD_CGC_CTRL__VCPU_MODE_MASK 752 | UVD_CGC_CTRL__SCPU_MODE_MASK); 753 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 754 755 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 756 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 757 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 758 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 763 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 764 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 765 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 766 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 767 } 768 769 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_vcn_inst *vinst) 770 { 771 struct amdgpu_device *adev = vinst->adev; 772 uint32_t data = 0; 773 774 if (amdgpu_sriov_vf(adev)) 775 return; 776 777 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 778 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 779 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 780 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 781 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 782 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 783 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 784 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 785 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 786 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 787 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 788 789 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 791 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 792 } else { 793 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 794 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 795 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 796 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 797 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 798 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 799 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 800 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 801 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 802 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 803 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 804 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 805 } 806 807 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 808 * UVDU_PWR_STATUS are 0 (power on) */ 809 810 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 811 data &= ~0x103; 812 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 813 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 814 UVD_POWER_STATUS__UVD_PG_EN_MASK; 815 816 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 817 } 818 819 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_vcn_inst *vinst) 820 { 821 struct amdgpu_device *adev = vinst->adev; 822 uint32_t data = 0; 823 824 if (amdgpu_sriov_vf(adev)) 825 return; 826 827 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 828 /* Before power off, this indicator has to be turned on */ 829 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 830 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 831 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 832 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 833 834 835 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 836 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 837 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 838 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 839 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 840 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 841 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 842 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 843 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 844 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 845 846 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 847 848 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 849 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 850 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 851 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 852 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 853 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 854 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 855 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 856 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 857 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 858 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 859 } 860 } 861 862 static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect) 863 { 864 struct amdgpu_device *adev = vinst->adev; 865 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 866 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 867 uint32_t rb_bufsz, tmp; 868 int ret; 869 870 vcn_v2_0_enable_static_power_gating(vinst); 871 872 /* enable dynamic power gating mode */ 873 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 874 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 875 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 876 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 877 878 if (indirect) 879 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; 880 881 /* enable clock gating */ 882 vcn_v2_0_clock_gating_dpg_mode(vinst, 0, indirect); 883 884 /* enable VCPU clock */ 885 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 886 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 887 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 888 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 889 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 890 891 /* disable master interupt */ 892 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 893 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 894 895 /* setup mmUVD_LMI_CTRL */ 896 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 897 UVD_LMI_CTRL__REQ_MODE_MASK | 898 UVD_LMI_CTRL__CRC_RESET_MASK | 899 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 900 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 901 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 902 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 903 0x00100000L); 904 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 905 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 906 907 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 908 UVD, 0, mmUVD_MPC_CNTL), 909 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 910 911 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 912 UVD, 0, mmUVD_MPC_SET_MUXA0), 913 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 914 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 915 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 916 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 917 918 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 919 UVD, 0, mmUVD_MPC_SET_MUXB0), 920 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 921 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 922 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 923 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 924 925 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 926 UVD, 0, mmUVD_MPC_SET_MUX), 927 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 928 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 929 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 930 931 vcn_v2_0_mc_resume_dpg_mode(vinst, indirect); 932 933 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 934 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 935 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 936 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 937 938 /* release VCPU reset to boot */ 939 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 940 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 941 942 /* enable LMI MC and UMC channels */ 943 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 944 UVD, 0, mmUVD_LMI_CTRL2), 945 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 946 947 /* enable master interrupt */ 948 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 949 UVD, 0, mmUVD_MASTINT_EN), 950 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 951 952 if (indirect) { 953 ret = amdgpu_vcn_psp_update_sram(adev, 0, 0); 954 if (ret) { 955 dev_err(adev->dev, "vcn sram load failed %d\n", ret); 956 return ret; 957 } 958 } 959 960 /* force RBC into idle state */ 961 rb_bufsz = order_base_2(ring->ring_size); 962 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 963 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 964 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 965 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 966 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 967 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 968 969 /* Stall DPG before WPTR/RPTR reset */ 970 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 971 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 972 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 973 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 974 975 /* set the write pointer delay */ 976 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 977 978 /* set the wb address */ 979 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 980 (upper_32_bits(ring->gpu_addr) >> 2)); 981 982 /* program the RB_BASE for ring buffer */ 983 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 984 lower_32_bits(ring->gpu_addr)); 985 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 986 upper_32_bits(ring->gpu_addr)); 987 988 /* Initialize the ring buffer's read and write pointers */ 989 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 990 991 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 992 993 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 994 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 995 lower_32_bits(ring->wptr)); 996 997 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 998 /* Unstall DPG */ 999 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1000 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1001 1002 /* Keeping one read-back to ensure all register writes are done, 1003 * otherwise it may introduce race conditions. 1004 */ 1005 RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1006 1007 return 0; 1008 } 1009 1010 static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst) 1011 { 1012 struct amdgpu_device *adev = vinst->adev; 1013 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 1014 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 1015 uint32_t rb_bufsz, tmp; 1016 uint32_t lmi_swap_cntl; 1017 int i, j, r; 1018 1019 if (adev->pm.dpm_enabled) 1020 amdgpu_dpm_enable_vcn(adev, true, 0); 1021 1022 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1023 return vcn_v2_0_start_dpg_mode(vinst, adev->vcn.inst->indirect_sram); 1024 1025 vcn_v2_0_disable_static_power_gating(vinst); 1026 1027 /* set uvd status busy */ 1028 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1029 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 1030 1031 /*SW clock gating */ 1032 vcn_v2_0_disable_clock_gating(vinst); 1033 1034 /* enable VCPU clock */ 1035 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 1036 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1037 1038 /* disable master interrupt */ 1039 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 1040 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1041 1042 /* setup mmUVD_LMI_CTRL */ 1043 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 1044 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 1045 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1046 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1047 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1048 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1049 1050 /* setup mmUVD_MPC_CNTL */ 1051 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 1052 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1053 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1054 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 1055 1056 /* setup UVD_MPC_SET_MUXA0 */ 1057 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 1058 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1059 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1060 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1061 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1062 1063 /* setup UVD_MPC_SET_MUXB0 */ 1064 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 1065 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1066 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1067 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1068 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1069 1070 /* setup mmUVD_MPC_SET_MUX */ 1071 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 1072 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1073 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1074 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1075 1076 vcn_v2_0_mc_resume(vinst); 1077 1078 /* release VCPU reset to boot */ 1079 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1080 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1081 1082 /* enable LMI MC and UMC channels */ 1083 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1084 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1085 1086 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1087 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1088 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1089 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1090 1091 /* disable byte swapping */ 1092 lmi_swap_cntl = 0; 1093 #ifdef __BIG_ENDIAN 1094 /* swap (8 in 32) RB and IB */ 1095 lmi_swap_cntl = 0xa; 1096 #endif 1097 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1098 1099 for (i = 0; i < 10; ++i) { 1100 uint32_t status; 1101 1102 for (j = 0; j < 100; ++j) { 1103 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1104 if (status & 2) 1105 break; 1106 mdelay(10); 1107 } 1108 r = 0; 1109 if (status & 2) 1110 break; 1111 1112 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1113 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1114 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1115 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1116 mdelay(10); 1117 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1118 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1119 mdelay(10); 1120 r = -1; 1121 } 1122 1123 if (r) { 1124 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1125 return r; 1126 } 1127 1128 /* enable master interrupt */ 1129 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1130 UVD_MASTINT_EN__VCPU_EN_MASK, 1131 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1132 1133 /* clear the busy bit of VCN_STATUS */ 1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1135 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1136 1137 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1138 1139 /* force RBC into idle state */ 1140 rb_bufsz = order_base_2(ring->ring_size); 1141 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1142 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1143 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1144 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1145 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1146 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1147 1148 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1149 /* program the RB_BASE for ring buffer */ 1150 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1151 lower_32_bits(ring->gpu_addr)); 1152 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1153 upper_32_bits(ring->gpu_addr)); 1154 1155 /* Initialize the ring buffer's read and write pointers */ 1156 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1157 1158 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1159 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1160 lower_32_bits(ring->wptr)); 1161 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1162 1163 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1164 ring = &adev->vcn.inst->ring_enc[0]; 1165 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1166 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1167 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1168 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1169 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1170 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1171 1172 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1173 ring = &adev->vcn.inst->ring_enc[1]; 1174 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1175 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1176 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1177 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1178 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1179 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1180 1181 /* Keeping one read-back to ensure all register writes are done, 1182 * otherwise it may introduce race conditions. 1183 */ 1184 RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1185 1186 return 0; 1187 } 1188 1189 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) 1190 { 1191 struct amdgpu_device *adev = vinst->adev; 1192 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1193 uint32_t tmp; 1194 1195 vcn_v2_0_pause_dpg_mode(vinst, &state); 1196 /* Wait for power status to be 1 */ 1197 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1198 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1199 1200 /* wait for read ptr to be equal to write ptr */ 1201 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1202 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1203 1204 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1205 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1206 1207 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1208 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1209 1210 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1211 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1212 1213 /* disable dynamic power gating mode */ 1214 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1215 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1216 1217 /* Keeping one read-back to ensure all register writes are done, 1218 * otherwise it may introduce race conditions. 1219 */ 1220 RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1221 1222 return 0; 1223 } 1224 1225 static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst) 1226 { 1227 struct amdgpu_device *adev = vinst->adev; 1228 uint32_t tmp; 1229 int r; 1230 1231 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1232 r = vcn_v2_0_stop_dpg_mode(vinst); 1233 if (r) 1234 return r; 1235 goto power_off; 1236 } 1237 1238 /* wait for uvd idle */ 1239 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1240 if (r) 1241 return r; 1242 1243 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1244 UVD_LMI_STATUS__READ_CLEAN_MASK | 1245 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1246 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1247 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1248 if (r) 1249 return r; 1250 1251 /* stall UMC channel */ 1252 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1253 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1254 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1255 1256 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1257 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1258 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1259 if (r) 1260 return r; 1261 1262 /* disable VCPU clock */ 1263 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1264 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1265 1266 /* reset LMI UMC */ 1267 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1268 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1269 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1270 1271 /* reset LMI */ 1272 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1273 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1274 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1275 1276 /* reset VCPU */ 1277 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1278 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1279 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1280 1281 /* clear status */ 1282 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1283 1284 vcn_v2_0_enable_clock_gating(vinst); 1285 vcn_v2_0_enable_static_power_gating(vinst); 1286 1287 /* Keeping one read-back to ensure all register writes are done, 1288 * otherwise it may introduce race conditions. 1289 */ 1290 RREG32_SOC15(VCN, 0, mmUVD_STATUS); 1291 1292 power_off: 1293 if (adev->pm.dpm_enabled) 1294 amdgpu_dpm_enable_vcn(adev, false, 0); 1295 1296 return 0; 1297 } 1298 1299 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 1300 struct dpg_pause_state *new_state) 1301 { 1302 struct amdgpu_device *adev = vinst->adev; 1303 int inst_idx = vinst->inst; 1304 struct amdgpu_ring *ring; 1305 uint32_t reg_data = 0; 1306 int ret_code; 1307 1308 /* pause/unpause if state is changed */ 1309 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1310 DRM_DEBUG("dpg pause state changed %d -> %d", 1311 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1312 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1313 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1314 1315 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1316 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1317 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1318 1319 if (!ret_code) { 1320 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 1321 /* pause DPG */ 1322 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1323 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1324 1325 /* wait for ACK */ 1326 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1327 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1328 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1329 1330 /* Stall DPG before WPTR/RPTR reset */ 1331 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1332 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1333 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1334 /* Restore */ 1335 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1336 ring = &adev->vcn.inst->ring_enc[0]; 1337 ring->wptr = 0; 1338 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1339 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1340 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1341 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1342 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1343 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1344 1345 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1346 ring = &adev->vcn.inst->ring_enc[1]; 1347 ring->wptr = 0; 1348 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1349 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1350 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1351 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1352 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1353 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1354 1355 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1356 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1357 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1358 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1359 /* Unstall DPG */ 1360 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1361 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1362 1363 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1364 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1365 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1366 } 1367 } else { 1368 /* unpause dpg, no need to wait */ 1369 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1370 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1371 } 1372 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int vcn_v2_0_reset(struct amdgpu_vcn_inst *vinst) 1379 { 1380 int r; 1381 1382 r = vcn_v2_0_stop(vinst); 1383 if (r) 1384 return r; 1385 return vcn_v2_0_start(vinst); 1386 } 1387 1388 static bool vcn_v2_0_is_idle(struct amdgpu_ip_block *ip_block) 1389 { 1390 struct amdgpu_device *adev = ip_block->adev; 1391 1392 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1393 } 1394 1395 static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1396 { 1397 struct amdgpu_device *adev = ip_block->adev; 1398 int ret; 1399 1400 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1401 UVD_STATUS__IDLE); 1402 1403 return ret; 1404 } 1405 1406 static int vcn_v2_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1407 enum amd_clockgating_state state) 1408 { 1409 struct amdgpu_device *adev = ip_block->adev; 1410 bool enable = (state == AMD_CG_STATE_GATE); 1411 1412 if (amdgpu_sriov_vf(adev)) 1413 return 0; 1414 1415 if (enable) { 1416 /* wait for STATUS to clear */ 1417 if (!vcn_v2_0_is_idle(ip_block)) 1418 return -EBUSY; 1419 vcn_v2_0_enable_clock_gating(&adev->vcn.inst[0]); 1420 } else { 1421 /* disable HW gating and enable Sw gating */ 1422 vcn_v2_0_disable_clock_gating(&adev->vcn.inst[0]); 1423 } 1424 return 0; 1425 } 1426 1427 /** 1428 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1429 * 1430 * @ring: amdgpu_ring pointer 1431 * 1432 * Returns the current hardware read pointer 1433 */ 1434 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1435 { 1436 struct amdgpu_device *adev = ring->adev; 1437 1438 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1439 } 1440 1441 /** 1442 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1443 * 1444 * @ring: amdgpu_ring pointer 1445 * 1446 * Returns the current hardware write pointer 1447 */ 1448 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1449 { 1450 struct amdgpu_device *adev = ring->adev; 1451 1452 if (ring->use_doorbell) 1453 return *ring->wptr_cpu_addr; 1454 else 1455 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1456 } 1457 1458 /** 1459 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1460 * 1461 * @ring: amdgpu_ring pointer 1462 * 1463 * Commits the write pointer to the hardware 1464 */ 1465 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1466 { 1467 struct amdgpu_device *adev = ring->adev; 1468 1469 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1470 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1471 lower_32_bits(ring->wptr) | 0x80000000); 1472 1473 if (ring->use_doorbell) { 1474 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1475 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1476 } else { 1477 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1478 } 1479 } 1480 1481 /** 1482 * vcn_v2_0_dec_ring_insert_start - insert a start command 1483 * 1484 * @ring: amdgpu_ring pointer 1485 * 1486 * Write a start command to the ring. 1487 */ 1488 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1489 { 1490 struct amdgpu_device *adev = ring->adev; 1491 1492 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1493 amdgpu_ring_write(ring, 0); 1494 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1495 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1496 } 1497 1498 /** 1499 * vcn_v2_0_dec_ring_insert_end - insert a end command 1500 * 1501 * @ring: amdgpu_ring pointer 1502 * 1503 * Write a end command to the ring. 1504 */ 1505 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1506 { 1507 struct amdgpu_device *adev = ring->adev; 1508 1509 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[0].internal.cmd, 0)); 1510 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1511 } 1512 1513 /** 1514 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1515 * 1516 * @ring: amdgpu_ring pointer 1517 * @count: the number of NOP packets to insert 1518 * 1519 * Write a nop command to the ring. 1520 */ 1521 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1522 { 1523 struct amdgpu_device *adev = ring->adev; 1524 int i; 1525 1526 WARN_ON(ring->wptr % 2 || count % 2); 1527 1528 for (i = 0; i < count / 2; i++) { 1529 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.nop, 0)); 1530 amdgpu_ring_write(ring, 0); 1531 } 1532 } 1533 1534 /** 1535 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1536 * 1537 * @ring: amdgpu_ring pointer 1538 * @addr: address 1539 * @seq: sequence number 1540 * @flags: fence related flags 1541 * 1542 * Write a fence and a trap command to the ring. 1543 */ 1544 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1545 unsigned flags) 1546 { 1547 struct amdgpu_device *adev = ring->adev; 1548 1549 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1550 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.context_id, 0)); 1551 amdgpu_ring_write(ring, seq); 1552 1553 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1554 amdgpu_ring_write(ring, addr & 0xffffffff); 1555 1556 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1557 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1558 1559 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1560 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1561 1562 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1563 amdgpu_ring_write(ring, 0); 1564 1565 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1566 amdgpu_ring_write(ring, 0); 1567 1568 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1569 1570 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1571 } 1572 1573 /** 1574 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1575 * 1576 * @ring: amdgpu_ring pointer 1577 * @job: job to retrieve vmid from 1578 * @ib: indirect buffer to execute 1579 * @flags: unused 1580 * 1581 * Write ring commands to execute the indirect buffer 1582 */ 1583 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1584 struct amdgpu_job *job, 1585 struct amdgpu_ib *ib, 1586 uint32_t flags) 1587 { 1588 struct amdgpu_device *adev = ring->adev; 1589 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1590 1591 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_vmid, 0)); 1592 amdgpu_ring_write(ring, vmid); 1593 1594 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_low, 0)); 1595 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1596 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_bar_high, 0)); 1597 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1598 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.ib_size, 0)); 1599 amdgpu_ring_write(ring, ib->length_dw); 1600 } 1601 1602 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1603 uint32_t val, uint32_t mask) 1604 { 1605 struct amdgpu_device *adev = ring->adev; 1606 1607 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1608 amdgpu_ring_write(ring, reg << 2); 1609 1610 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1611 amdgpu_ring_write(ring, val); 1612 1613 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.gp_scratch8, 0)); 1614 amdgpu_ring_write(ring, mask); 1615 1616 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1617 1618 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1619 } 1620 1621 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1622 unsigned vmid, uint64_t pd_addr) 1623 { 1624 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1625 uint32_t data0, data1, mask; 1626 1627 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1628 1629 /* wait for register write */ 1630 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1631 data1 = lower_32_bits(pd_addr); 1632 mask = 0xffffffff; 1633 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1634 } 1635 1636 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1637 uint32_t reg, uint32_t val) 1638 { 1639 struct amdgpu_device *adev = ring->adev; 1640 1641 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data0, 0)); 1642 amdgpu_ring_write(ring, reg << 2); 1643 1644 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.data1, 0)); 1645 amdgpu_ring_write(ring, val); 1646 1647 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1648 1649 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1650 } 1651 1652 /** 1653 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1654 * 1655 * @ring: amdgpu_ring pointer 1656 * 1657 * Returns the current hardware enc read pointer 1658 */ 1659 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1660 { 1661 struct amdgpu_device *adev = ring->adev; 1662 1663 if (ring == &adev->vcn.inst->ring_enc[0]) 1664 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1665 else 1666 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1667 } 1668 1669 /** 1670 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1671 * 1672 * @ring: amdgpu_ring pointer 1673 * 1674 * Returns the current hardware enc write pointer 1675 */ 1676 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1677 { 1678 struct amdgpu_device *adev = ring->adev; 1679 1680 if (ring == &adev->vcn.inst->ring_enc[0]) { 1681 if (ring->use_doorbell) 1682 return *ring->wptr_cpu_addr; 1683 else 1684 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1685 } else { 1686 if (ring->use_doorbell) 1687 return *ring->wptr_cpu_addr; 1688 else 1689 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1690 } 1691 } 1692 1693 /** 1694 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1695 * 1696 * @ring: amdgpu_ring pointer 1697 * 1698 * Commits the enc write pointer to the hardware 1699 */ 1700 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 1704 if (ring == &adev->vcn.inst->ring_enc[0]) { 1705 if (ring->use_doorbell) { 1706 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1707 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1708 } else { 1709 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1710 } 1711 } else { 1712 if (ring->use_doorbell) { 1713 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1714 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1715 } else { 1716 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1717 } 1718 } 1719 } 1720 1721 /** 1722 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1723 * 1724 * @ring: amdgpu_ring pointer 1725 * @addr: address 1726 * @seq: sequence number 1727 * @flags: fence related flags 1728 * 1729 * Write enc a fence and a trap command to the ring. 1730 */ 1731 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1732 u64 seq, unsigned flags) 1733 { 1734 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1735 1736 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1737 amdgpu_ring_write(ring, addr); 1738 amdgpu_ring_write(ring, upper_32_bits(addr)); 1739 amdgpu_ring_write(ring, seq); 1740 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1741 } 1742 1743 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1744 { 1745 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1746 } 1747 1748 /** 1749 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1750 * 1751 * @ring: amdgpu_ring pointer 1752 * @job: job to retrive vmid from 1753 * @ib: indirect buffer to execute 1754 * @flags: unused 1755 * 1756 * Write enc ring commands to execute the indirect buffer 1757 */ 1758 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1759 struct amdgpu_job *job, 1760 struct amdgpu_ib *ib, 1761 uint32_t flags) 1762 { 1763 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1764 1765 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1766 amdgpu_ring_write(ring, vmid); 1767 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1768 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1769 amdgpu_ring_write(ring, ib->length_dw); 1770 } 1771 1772 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1773 uint32_t val, uint32_t mask) 1774 { 1775 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1776 amdgpu_ring_write(ring, reg << 2); 1777 amdgpu_ring_write(ring, mask); 1778 amdgpu_ring_write(ring, val); 1779 } 1780 1781 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1782 unsigned int vmid, uint64_t pd_addr) 1783 { 1784 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1785 1786 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1787 1788 /* wait for reg writes */ 1789 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1790 vmid * hub->ctx_addr_distance, 1791 lower_32_bits(pd_addr), 0xffffffff); 1792 } 1793 1794 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1795 { 1796 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1797 amdgpu_ring_write(ring, reg << 2); 1798 amdgpu_ring_write(ring, val); 1799 } 1800 1801 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1802 struct amdgpu_irq_src *source, 1803 unsigned type, 1804 enum amdgpu_interrupt_state state) 1805 { 1806 return 0; 1807 } 1808 1809 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1810 struct amdgpu_irq_src *source, 1811 struct amdgpu_iv_entry *entry) 1812 { 1813 DRM_DEBUG("IH: VCN TRAP\n"); 1814 1815 switch (entry->src_id) { 1816 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1817 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1818 break; 1819 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1820 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1821 break; 1822 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1823 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1824 break; 1825 default: 1826 DRM_ERROR("Unhandled interrupt: %d %d\n", 1827 entry->src_id, entry->src_data[0]); 1828 break; 1829 } 1830 1831 return 0; 1832 } 1833 1834 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1835 { 1836 struct amdgpu_device *adev = ring->adev; 1837 uint32_t tmp = 0; 1838 unsigned i; 1839 int r; 1840 1841 if (amdgpu_sriov_vf(adev)) 1842 return 0; 1843 1844 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1845 r = amdgpu_ring_alloc(ring, 4); 1846 if (r) 1847 return r; 1848 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.cmd, 0)); 1849 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1850 amdgpu_ring_write(ring, PACKET0(adev->vcn.inst[ring->me].internal.scratch9, 0)); 1851 amdgpu_ring_write(ring, 0xDEADBEEF); 1852 amdgpu_ring_commit(ring); 1853 for (i = 0; i < adev->usec_timeout; i++) { 1854 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1855 if (tmp == 0xDEADBEEF) 1856 break; 1857 udelay(1); 1858 } 1859 1860 if (i >= adev->usec_timeout) 1861 r = -ETIMEDOUT; 1862 1863 return r; 1864 } 1865 1866 1867 static int vcn_v2_0_set_pg_state(struct amdgpu_vcn_inst *vinst, 1868 enum amd_powergating_state state) 1869 { 1870 /* This doesn't actually powergate the VCN block. 1871 * That's done in the dpm code via the SMC. This 1872 * just re-inits the block as necessary. The actual 1873 * gating still happens in the dpm code. We should 1874 * revisit this when there is a cleaner line between 1875 * the smc and the hw blocks 1876 */ 1877 int ret; 1878 struct amdgpu_device *adev = vinst->adev; 1879 1880 if (amdgpu_sriov_vf(adev)) { 1881 vinst->cur_state = AMD_PG_STATE_UNGATE; 1882 return 0; 1883 } 1884 1885 if (state == vinst->cur_state) 1886 return 0; 1887 1888 if (state == AMD_PG_STATE_GATE) 1889 ret = vcn_v2_0_stop(vinst); 1890 else 1891 ret = vcn_v2_0_start(vinst); 1892 1893 if (!ret) 1894 vinst->cur_state = state; 1895 1896 return ret; 1897 } 1898 1899 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1900 struct amdgpu_mm_table *table) 1901 { 1902 uint32_t data = 0, loop; 1903 uint64_t addr = table->gpu_addr; 1904 struct mmsch_v2_0_init_header *header; 1905 uint32_t size; 1906 int i; 1907 1908 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1909 size = header->header_size + header->vcn_table_size; 1910 1911 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1912 * of memory descriptor location 1913 */ 1914 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1915 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1916 1917 /* 2, update vmid of descriptor */ 1918 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1919 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1920 /* use domain0 for MM scheduler */ 1921 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1922 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1923 1924 /* 3, notify mmsch about the size of this descriptor */ 1925 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1926 1927 /* 4, set resp to zero */ 1928 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1929 1930 adev->vcn.inst->ring_dec.wptr = 0; 1931 adev->vcn.inst->ring_dec.wptr_old = 0; 1932 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1933 1934 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) { 1935 adev->vcn.inst->ring_enc[i].wptr = 0; 1936 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1937 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1938 } 1939 1940 /* 5, kick off the initialization and wait until 1941 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1942 */ 1943 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1944 1945 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1946 loop = 1000; 1947 while ((data & 0x10000002) != 0x10000002) { 1948 udelay(10); 1949 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1950 loop--; 1951 if (!loop) 1952 break; 1953 } 1954 1955 if (!loop) { 1956 DRM_ERROR("failed to init MMSCH, " \ 1957 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1958 return -EBUSY; 1959 } 1960 1961 return 0; 1962 } 1963 1964 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1965 { 1966 int r; 1967 uint32_t tmp; 1968 struct amdgpu_ring *ring; 1969 uint32_t offset, size; 1970 uint32_t table_size = 0; 1971 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1972 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1973 struct mmsch_v2_0_cmd_end end = { {0} }; 1974 struct mmsch_v2_0_init_header *header; 1975 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1976 uint8_t i = 0; 1977 1978 header = (struct mmsch_v2_0_init_header *)init_table; 1979 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1980 direct_rd_mod_wt.cmd_header.command_type = 1981 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1982 end.cmd_header.command_type = MMSCH_COMMAND__END; 1983 1984 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1985 header->version = MMSCH_VERSION; 1986 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1987 1988 header->vcn_table_offset = header->header_size; 1989 1990 init_table += header->vcn_table_offset; 1991 1992 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); 1993 1994 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1995 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1996 0xFFFFFFFF, 0x00000004); 1997 1998 /* mc resume*/ 1999 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 2000 MMSCH_V2_0_INSERT_DIRECT_WT( 2001 SOC15_REG_OFFSET(UVD, i, 2002 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 2003 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); 2004 MMSCH_V2_0_INSERT_DIRECT_WT( 2005 SOC15_REG_OFFSET(UVD, i, 2006 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 2007 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); 2008 offset = 0; 2009 } else { 2010 MMSCH_V2_0_INSERT_DIRECT_WT( 2011 SOC15_REG_OFFSET(UVD, i, 2012 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 2013 lower_32_bits(adev->vcn.inst->gpu_addr)); 2014 MMSCH_V2_0_INSERT_DIRECT_WT( 2015 SOC15_REG_OFFSET(UVD, i, 2016 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 2017 upper_32_bits(adev->vcn.inst->gpu_addr)); 2018 offset = size; 2019 } 2020 2021 MMSCH_V2_0_INSERT_DIRECT_WT( 2022 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 2023 0); 2024 MMSCH_V2_0_INSERT_DIRECT_WT( 2025 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 2026 size); 2027 2028 MMSCH_V2_0_INSERT_DIRECT_WT( 2029 SOC15_REG_OFFSET(UVD, i, 2030 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 2031 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 2032 MMSCH_V2_0_INSERT_DIRECT_WT( 2033 SOC15_REG_OFFSET(UVD, i, 2034 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 2035 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 2036 MMSCH_V2_0_INSERT_DIRECT_WT( 2037 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 2038 0); 2039 MMSCH_V2_0_INSERT_DIRECT_WT( 2040 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 2041 AMDGPU_VCN_STACK_SIZE); 2042 2043 MMSCH_V2_0_INSERT_DIRECT_WT( 2044 SOC15_REG_OFFSET(UVD, i, 2045 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 2046 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 2047 AMDGPU_VCN_STACK_SIZE)); 2048 MMSCH_V2_0_INSERT_DIRECT_WT( 2049 SOC15_REG_OFFSET(UVD, i, 2050 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 2051 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 2052 AMDGPU_VCN_STACK_SIZE)); 2053 MMSCH_V2_0_INSERT_DIRECT_WT( 2054 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 2055 0); 2056 MMSCH_V2_0_INSERT_DIRECT_WT( 2057 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 2058 AMDGPU_VCN_CONTEXT_SIZE); 2059 2060 for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) { 2061 ring = &adev->vcn.inst->ring_enc[r]; 2062 ring->wptr = 0; 2063 MMSCH_V2_0_INSERT_DIRECT_WT( 2064 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 2065 lower_32_bits(ring->gpu_addr)); 2066 MMSCH_V2_0_INSERT_DIRECT_WT( 2067 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 2068 upper_32_bits(ring->gpu_addr)); 2069 MMSCH_V2_0_INSERT_DIRECT_WT( 2070 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 2071 ring->ring_size / 4); 2072 } 2073 2074 ring = &adev->vcn.inst->ring_dec; 2075 ring->wptr = 0; 2076 MMSCH_V2_0_INSERT_DIRECT_WT( 2077 SOC15_REG_OFFSET(UVD, i, 2078 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 2079 lower_32_bits(ring->gpu_addr)); 2080 MMSCH_V2_0_INSERT_DIRECT_WT( 2081 SOC15_REG_OFFSET(UVD, i, 2082 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 2083 upper_32_bits(ring->gpu_addr)); 2084 /* force RBC into idle state */ 2085 tmp = order_base_2(ring->ring_size); 2086 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 2087 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 2088 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 2089 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 2090 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 2091 MMSCH_V2_0_INSERT_DIRECT_WT( 2092 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 2093 2094 /* add end packet */ 2095 tmp = sizeof(struct mmsch_v2_0_cmd_end); 2096 memcpy((void *)init_table, &end, tmp); 2097 table_size += (tmp / 4); 2098 header->vcn_table_size = table_size; 2099 2100 } 2101 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 2102 } 2103 2104 static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 2105 { 2106 struct amdgpu_device *adev = ip_block->adev; 2107 int i, j; 2108 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 2109 uint32_t inst_off, is_powered; 2110 2111 if (!adev->vcn.ip_dump) 2112 return; 2113 2114 drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); 2115 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2116 if (adev->vcn.harvest_config & (1 << i)) { 2117 drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); 2118 continue; 2119 } 2120 2121 inst_off = i * reg_count; 2122 is_powered = (adev->vcn.ip_dump[inst_off] & 2123 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2124 2125 if (is_powered) { 2126 drm_printf(p, "\nActive Instance:VCN%d\n", i); 2127 for (j = 0; j < reg_count; j++) 2128 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name, 2129 adev->vcn.ip_dump[inst_off + j]); 2130 } else { 2131 drm_printf(p, "\nInactive Instance:VCN%d\n", i); 2132 } 2133 } 2134 } 2135 2136 static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block) 2137 { 2138 struct amdgpu_device *adev = ip_block->adev; 2139 int i, j; 2140 bool is_powered; 2141 uint32_t inst_off; 2142 uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); 2143 2144 if (!adev->vcn.ip_dump) 2145 return; 2146 2147 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 2148 if (adev->vcn.harvest_config & (1 << i)) 2149 continue; 2150 2151 inst_off = i * reg_count; 2152 /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 2153 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 2154 is_powered = (adev->vcn.ip_dump[inst_off] & 2155 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 2156 2157 if (is_powered) 2158 for (j = 1; j < reg_count; j++) 2159 adev->vcn.ip_dump[inst_off + j] = 2160 RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i)); 2161 } 2162 } 2163 2164 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 2165 .name = "vcn_v2_0", 2166 .early_init = vcn_v2_0_early_init, 2167 .sw_init = vcn_v2_0_sw_init, 2168 .sw_fini = vcn_v2_0_sw_fini, 2169 .hw_init = vcn_v2_0_hw_init, 2170 .hw_fini = vcn_v2_0_hw_fini, 2171 .suspend = vcn_v2_0_suspend, 2172 .resume = vcn_v2_0_resume, 2173 .is_idle = vcn_v2_0_is_idle, 2174 .wait_for_idle = vcn_v2_0_wait_for_idle, 2175 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2176 .set_powergating_state = vcn_set_powergating_state, 2177 .dump_ip_state = vcn_v2_0_dump_ip_state, 2178 .print_ip_state = vcn_v2_0_print_ip_state, 2179 }; 2180 2181 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2182 .type = AMDGPU_RING_TYPE_VCN_DEC, 2183 .align_mask = 0xf, 2184 .secure_submission_supported = true, 2185 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2186 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2187 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2188 .emit_frame_size = 2189 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2190 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2191 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2192 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2193 6, 2194 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2195 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2196 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2197 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2198 .test_ring = vcn_v2_0_dec_ring_test_ring, 2199 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2200 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2201 .insert_start = vcn_v2_0_dec_ring_insert_start, 2202 .insert_end = vcn_v2_0_dec_ring_insert_end, 2203 .pad_ib = amdgpu_ring_generic_pad_ib, 2204 .begin_use = amdgpu_vcn_ring_begin_use, 2205 .end_use = amdgpu_vcn_ring_end_use, 2206 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2207 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2208 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2209 .reset = amdgpu_vcn_ring_reset, 2210 }; 2211 2212 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2213 .type = AMDGPU_RING_TYPE_VCN_ENC, 2214 .align_mask = 0x3f, 2215 .nop = VCN_ENC_CMD_NO_OP, 2216 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2217 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2218 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2219 .emit_frame_size = 2220 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2221 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2222 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2223 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2224 1, /* vcn_v2_0_enc_ring_insert_end */ 2225 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2226 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2227 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2228 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2229 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2230 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2231 .insert_nop = amdgpu_ring_insert_nop, 2232 .insert_end = vcn_v2_0_enc_ring_insert_end, 2233 .pad_ib = amdgpu_ring_generic_pad_ib, 2234 .begin_use = amdgpu_vcn_ring_begin_use, 2235 .end_use = amdgpu_vcn_ring_end_use, 2236 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2237 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2238 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2239 .reset = amdgpu_vcn_ring_reset, 2240 }; 2241 2242 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2243 { 2244 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2245 } 2246 2247 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2248 { 2249 int i; 2250 2251 for (i = 0; i < adev->vcn.inst[0].num_enc_rings; ++i) 2252 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2253 } 2254 2255 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2256 .set = vcn_v2_0_set_interrupt_state, 2257 .process = vcn_v2_0_process_interrupt, 2258 }; 2259 2260 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2261 { 2262 adev->vcn.inst->irq.num_types = adev->vcn.inst[0].num_enc_rings + 1; 2263 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2264 } 2265 2266 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2267 { 2268 .type = AMD_IP_BLOCK_TYPE_VCN, 2269 .major = 2, 2270 .minor = 0, 2271 .rev = 0, 2272 .funcs = &vcn_v2_0_ip_funcs, 2273 }; 2274