1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drm_drv.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_vcn.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "amdgpu_pm.h" 32 #include "amdgpu_psp.h" 33 #include "mmsch_v2_0.h" 34 #include "vcn_v2_0.h" 35 36 #include "vcn/vcn_2_0_0_offset.h" 37 #include "vcn/vcn_2_0_0_sh_mask.h" 38 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 39 40 #define VCN_VID_SOC_ADDRESS_2_0 0x1fa00 41 #define VCN1_VID_SOC_ADDRESS_3_0 0x48200 42 43 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 44 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 45 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 46 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 47 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 48 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 49 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 50 51 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 52 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 53 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 54 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 55 56 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 57 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 58 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 59 static int vcn_v2_0_set_powergating_state(void *handle, 60 enum amd_powergating_state state); 61 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 62 int inst_idx, struct dpg_pause_state *new_state); 63 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 64 /** 65 * vcn_v2_0_early_init - set function pointers and load microcode 66 * 67 * @handle: amdgpu_device pointer 68 * 69 * Set ring and irq function pointers 70 * Load microcode from filesystem 71 */ 72 static int vcn_v2_0_early_init(void *handle) 73 { 74 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 75 76 if (amdgpu_sriov_vf(adev)) 77 adev->vcn.num_enc_rings = 1; 78 else 79 adev->vcn.num_enc_rings = 2; 80 81 vcn_v2_0_set_dec_ring_funcs(adev); 82 vcn_v2_0_set_enc_ring_funcs(adev); 83 vcn_v2_0_set_irq_funcs(adev); 84 85 return amdgpu_vcn_early_init(adev); 86 } 87 88 /** 89 * vcn_v2_0_sw_init - sw init for VCN block 90 * 91 * @handle: amdgpu_device pointer 92 * 93 * Load firmware and sw initialization 94 */ 95 static int vcn_v2_0_sw_init(void *handle) 96 { 97 struct amdgpu_ring *ring; 98 int i, r; 99 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 100 volatile struct amdgpu_fw_shared *fw_shared; 101 102 /* VCN DEC TRAP */ 103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 104 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 105 &adev->vcn.inst->irq); 106 if (r) 107 return r; 108 109 /* VCN ENC TRAP */ 110 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 112 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 113 &adev->vcn.inst->irq); 114 if (r) 115 return r; 116 } 117 118 r = amdgpu_vcn_sw_init(adev); 119 if (r) 120 return r; 121 122 amdgpu_vcn_setup_ucode(adev); 123 124 r = amdgpu_vcn_resume(adev); 125 if (r) 126 return r; 127 128 ring = &adev->vcn.inst->ring_dec; 129 130 ring->use_doorbell = true; 131 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 132 ring->vm_hub = AMDGPU_MMHUB0(0); 133 134 sprintf(ring->name, "vcn_dec"); 135 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 136 AMDGPU_RING_PRIO_DEFAULT, NULL); 137 if (r) 138 return r; 139 140 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 141 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 142 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 143 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 144 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 145 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 146 147 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 148 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 149 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 150 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 151 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 152 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 153 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 154 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 155 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 156 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 157 158 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 159 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 160 161 ring = &adev->vcn.inst->ring_enc[i]; 162 ring->use_doorbell = true; 163 ring->vm_hub = AMDGPU_MMHUB0(0); 164 if (!amdgpu_sriov_vf(adev)) 165 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 166 else 167 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 168 sprintf(ring->name, "vcn_enc%d", i); 169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 170 hw_prio, NULL); 171 if (r) 172 return r; 173 } 174 175 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 176 177 r = amdgpu_virt_alloc_mm_table(adev); 178 if (r) 179 return r; 180 181 fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 182 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 183 184 if (amdgpu_vcnfw_log) 185 amdgpu_vcn_fwlog_init(adev->vcn.inst); 186 187 return 0; 188 } 189 190 /** 191 * vcn_v2_0_sw_fini - sw fini for VCN block 192 * 193 * @handle: amdgpu_device pointer 194 * 195 * VCN suspend and free up sw allocation 196 */ 197 static int vcn_v2_0_sw_fini(void *handle) 198 { 199 int r, idx; 200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 201 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 202 203 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 204 fw_shared->present_flag_0 = 0; 205 drm_dev_exit(idx); 206 } 207 208 amdgpu_virt_free_mm_table(adev); 209 210 r = amdgpu_vcn_suspend(adev); 211 if (r) 212 return r; 213 214 r = amdgpu_vcn_sw_fini(adev); 215 216 return r; 217 } 218 219 /** 220 * vcn_v2_0_hw_init - start and test VCN block 221 * 222 * @handle: amdgpu_device pointer 223 * 224 * Initialize the hardware, boot up the VCPU and do some testing 225 */ 226 static int vcn_v2_0_hw_init(void *handle) 227 { 228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 229 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 230 int i, r; 231 232 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 233 ring->doorbell_index, 0); 234 235 if (amdgpu_sriov_vf(adev)) 236 vcn_v2_0_start_sriov(adev); 237 238 r = amdgpu_ring_test_helper(ring); 239 if (r) 240 return r; 241 242 //Disable vcn decode for sriov 243 if (amdgpu_sriov_vf(adev)) 244 ring->sched.ready = false; 245 246 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 247 ring = &adev->vcn.inst->ring_enc[i]; 248 r = amdgpu_ring_test_helper(ring); 249 if (r) 250 return r; 251 } 252 253 return 0; 254 } 255 256 /** 257 * vcn_v2_0_hw_fini - stop the hardware block 258 * 259 * @handle: amdgpu_device pointer 260 * 261 * Stop the VCN block, mark ring as not ready any more 262 */ 263 static int vcn_v2_0_hw_fini(void *handle) 264 { 265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 266 267 cancel_delayed_work_sync(&adev->vcn.idle_work); 268 269 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 270 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 271 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 272 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 273 274 return 0; 275 } 276 277 /** 278 * vcn_v2_0_suspend - suspend VCN block 279 * 280 * @handle: amdgpu_device pointer 281 * 282 * HW fini and suspend VCN block 283 */ 284 static int vcn_v2_0_suspend(void *handle) 285 { 286 int r; 287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 288 289 r = vcn_v2_0_hw_fini(adev); 290 if (r) 291 return r; 292 293 r = amdgpu_vcn_suspend(adev); 294 295 return r; 296 } 297 298 /** 299 * vcn_v2_0_resume - resume VCN block 300 * 301 * @handle: amdgpu_device pointer 302 * 303 * Resume firmware and hw init VCN block 304 */ 305 static int vcn_v2_0_resume(void *handle) 306 { 307 int r; 308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309 310 r = amdgpu_vcn_resume(adev); 311 if (r) 312 return r; 313 314 r = vcn_v2_0_hw_init(adev); 315 316 return r; 317 } 318 319 /** 320 * vcn_v2_0_mc_resume - memory controller programming 321 * 322 * @adev: amdgpu_device pointer 323 * 324 * Let the VCN memory controller know it's offsets 325 */ 326 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 327 { 328 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); 329 uint32_t offset; 330 331 if (amdgpu_sriov_vf(adev)) 332 return; 333 334 /* cache window 0: fw */ 335 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 336 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 337 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 339 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 340 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 341 offset = 0; 342 } else { 343 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 344 lower_32_bits(adev->vcn.inst->gpu_addr)); 345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 346 upper_32_bits(adev->vcn.inst->gpu_addr)); 347 offset = size; 348 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 349 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 350 } 351 352 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 353 354 /* cache window 1: stack */ 355 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 356 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 357 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 358 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 359 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 360 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 361 362 /* cache window 2: context */ 363 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 364 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 365 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 366 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 367 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 368 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 369 370 /* non-cache window */ 371 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 372 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 373 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 374 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); 375 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 376 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 377 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 378 379 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 380 } 381 382 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 383 { 384 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); 385 uint32_t offset; 386 387 /* cache window 0: fw */ 388 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 389 if (!indirect) { 390 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 391 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 392 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 393 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 394 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 395 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 396 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 397 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 398 } else { 399 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 400 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 401 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 402 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 403 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 404 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 405 } 406 offset = 0; 407 } else { 408 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 409 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 410 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 411 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 412 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 413 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 414 offset = size; 415 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 416 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 417 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 418 } 419 420 if (!indirect) 421 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 422 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 423 else 424 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 425 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 426 427 /* cache window 1: stack */ 428 if (!indirect) { 429 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 430 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 431 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 432 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 433 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 434 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 435 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 436 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 437 } else { 438 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 439 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 440 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 441 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 442 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 443 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 444 } 445 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 446 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 447 448 /* cache window 2: context */ 449 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 450 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 451 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 452 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 453 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 454 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 455 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 456 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 457 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 458 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 459 460 /* non-cache window */ 461 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 462 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 463 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 464 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 465 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 466 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); 467 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 468 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 469 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 470 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 471 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 472 473 /* VCN global tiling registers */ 474 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 475 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 476 } 477 478 /** 479 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 480 * 481 * @adev: amdgpu_device pointer 482 * 483 * Disable clock gating for VCN block 484 */ 485 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 486 { 487 uint32_t data; 488 489 if (amdgpu_sriov_vf(adev)) 490 return; 491 492 /* UVD disable CGC */ 493 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 494 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 495 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 496 else 497 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 498 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 499 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 500 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 501 502 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 503 data &= ~(UVD_CGC_GATE__SYS_MASK 504 | UVD_CGC_GATE__UDEC_MASK 505 | UVD_CGC_GATE__MPEG2_MASK 506 | UVD_CGC_GATE__REGS_MASK 507 | UVD_CGC_GATE__RBC_MASK 508 | UVD_CGC_GATE__LMI_MC_MASK 509 | UVD_CGC_GATE__LMI_UMC_MASK 510 | UVD_CGC_GATE__IDCT_MASK 511 | UVD_CGC_GATE__MPRD_MASK 512 | UVD_CGC_GATE__MPC_MASK 513 | UVD_CGC_GATE__LBSI_MASK 514 | UVD_CGC_GATE__LRBBM_MASK 515 | UVD_CGC_GATE__UDEC_RE_MASK 516 | UVD_CGC_GATE__UDEC_CM_MASK 517 | UVD_CGC_GATE__UDEC_IT_MASK 518 | UVD_CGC_GATE__UDEC_DB_MASK 519 | UVD_CGC_GATE__UDEC_MP_MASK 520 | UVD_CGC_GATE__WCB_MASK 521 | UVD_CGC_GATE__VCPU_MASK 522 | UVD_CGC_GATE__SCPU_MASK); 523 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 524 525 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 526 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 527 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 528 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 529 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 530 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 531 | UVD_CGC_CTRL__SYS_MODE_MASK 532 | UVD_CGC_CTRL__UDEC_MODE_MASK 533 | UVD_CGC_CTRL__MPEG2_MODE_MASK 534 | UVD_CGC_CTRL__REGS_MODE_MASK 535 | UVD_CGC_CTRL__RBC_MODE_MASK 536 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 537 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 538 | UVD_CGC_CTRL__IDCT_MODE_MASK 539 | UVD_CGC_CTRL__MPRD_MODE_MASK 540 | UVD_CGC_CTRL__MPC_MODE_MASK 541 | UVD_CGC_CTRL__LBSI_MODE_MASK 542 | UVD_CGC_CTRL__LRBBM_MODE_MASK 543 | UVD_CGC_CTRL__WCB_MODE_MASK 544 | UVD_CGC_CTRL__VCPU_MODE_MASK 545 | UVD_CGC_CTRL__SCPU_MODE_MASK); 546 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 547 548 /* turn on */ 549 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 550 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 551 | UVD_SUVD_CGC_GATE__SIT_MASK 552 | UVD_SUVD_CGC_GATE__SMP_MASK 553 | UVD_SUVD_CGC_GATE__SCM_MASK 554 | UVD_SUVD_CGC_GATE__SDB_MASK 555 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 556 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 557 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 558 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 559 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 560 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 561 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 562 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 563 | UVD_SUVD_CGC_GATE__SCLR_MASK 564 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 565 | UVD_SUVD_CGC_GATE__ENT_MASK 566 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 567 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 568 | UVD_SUVD_CGC_GATE__SITE_MASK 569 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 570 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 571 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 572 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 573 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 574 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 575 576 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 577 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 578 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 579 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 580 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 581 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 582 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 583 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 584 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 585 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 586 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 587 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 588 } 589 590 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 591 uint8_t sram_sel, uint8_t indirect) 592 { 593 uint32_t reg_data = 0; 594 595 /* enable sw clock gating control */ 596 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 597 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 598 else 599 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 600 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 601 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 602 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 603 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 604 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 605 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 606 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 607 UVD_CGC_CTRL__SYS_MODE_MASK | 608 UVD_CGC_CTRL__UDEC_MODE_MASK | 609 UVD_CGC_CTRL__MPEG2_MODE_MASK | 610 UVD_CGC_CTRL__REGS_MODE_MASK | 611 UVD_CGC_CTRL__RBC_MODE_MASK | 612 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 613 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 614 UVD_CGC_CTRL__IDCT_MODE_MASK | 615 UVD_CGC_CTRL__MPRD_MODE_MASK | 616 UVD_CGC_CTRL__MPC_MODE_MASK | 617 UVD_CGC_CTRL__LBSI_MODE_MASK | 618 UVD_CGC_CTRL__LRBBM_MODE_MASK | 619 UVD_CGC_CTRL__WCB_MODE_MASK | 620 UVD_CGC_CTRL__VCPU_MODE_MASK | 621 UVD_CGC_CTRL__SCPU_MODE_MASK); 622 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 623 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 624 625 /* turn off clock gating */ 626 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 627 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 628 629 /* turn on SUVD clock gating */ 630 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 631 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 632 633 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 634 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 635 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 636 } 637 638 /** 639 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 640 * 641 * @adev: amdgpu_device pointer 642 * 643 * Enable clock gating for VCN block 644 */ 645 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 646 { 647 uint32_t data = 0; 648 649 if (amdgpu_sriov_vf(adev)) 650 return; 651 652 /* enable UVD CGC */ 653 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 654 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 655 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 else 657 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 658 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 659 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 660 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 661 662 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 663 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 664 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 665 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 666 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 667 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 668 | UVD_CGC_CTRL__SYS_MODE_MASK 669 | UVD_CGC_CTRL__UDEC_MODE_MASK 670 | UVD_CGC_CTRL__MPEG2_MODE_MASK 671 | UVD_CGC_CTRL__REGS_MODE_MASK 672 | UVD_CGC_CTRL__RBC_MODE_MASK 673 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 674 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 675 | UVD_CGC_CTRL__IDCT_MODE_MASK 676 | UVD_CGC_CTRL__MPRD_MODE_MASK 677 | UVD_CGC_CTRL__MPC_MODE_MASK 678 | UVD_CGC_CTRL__LBSI_MODE_MASK 679 | UVD_CGC_CTRL__LRBBM_MODE_MASK 680 | UVD_CGC_CTRL__WCB_MODE_MASK 681 | UVD_CGC_CTRL__VCPU_MODE_MASK 682 | UVD_CGC_CTRL__SCPU_MODE_MASK); 683 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 684 685 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 686 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 687 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 688 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 689 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 690 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 691 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 692 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 693 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 694 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 695 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 696 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 697 } 698 699 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 700 { 701 uint32_t data = 0; 702 703 if (amdgpu_sriov_vf(adev)) 704 return; 705 706 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 707 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 716 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 717 718 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 719 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 720 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 721 } else { 722 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 730 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 731 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 732 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 733 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 734 } 735 736 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 737 * UVDU_PWR_STATUS are 0 (power on) */ 738 739 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 740 data &= ~0x103; 741 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 742 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 743 UVD_POWER_STATUS__UVD_PG_EN_MASK; 744 745 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 746 } 747 748 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 749 { 750 uint32_t data = 0; 751 752 if (amdgpu_sriov_vf(adev)) 753 return; 754 755 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 756 /* Before power off, this indicator has to be turned on */ 757 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 758 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 759 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 760 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 761 762 763 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 770 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 771 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 772 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 773 774 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 775 776 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 781 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 782 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 783 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 784 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 785 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 786 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 787 } 788 } 789 790 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 791 { 792 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 793 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 794 uint32_t rb_bufsz, tmp; 795 796 vcn_v2_0_enable_static_power_gating(adev); 797 798 /* enable dynamic power gating mode */ 799 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 800 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 801 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 802 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 803 804 if (indirect) 805 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst->dpg_sram_cpu_addr; 806 807 /* enable clock gating */ 808 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 809 810 /* enable VCPU clock */ 811 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 812 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 813 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 814 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 815 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 816 817 /* disable master interupt */ 818 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 819 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 820 821 /* setup mmUVD_LMI_CTRL */ 822 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 823 UVD_LMI_CTRL__REQ_MODE_MASK | 824 UVD_LMI_CTRL__CRC_RESET_MASK | 825 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 826 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 827 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 828 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 829 0x00100000L); 830 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 831 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 832 833 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 834 UVD, 0, mmUVD_MPC_CNTL), 835 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 836 837 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 838 UVD, 0, mmUVD_MPC_SET_MUXA0), 839 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 840 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 841 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 842 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 843 844 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 845 UVD, 0, mmUVD_MPC_SET_MUXB0), 846 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 847 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 848 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 849 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 850 851 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 852 UVD, 0, mmUVD_MPC_SET_MUX), 853 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 854 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 855 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 856 857 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 858 859 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 860 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 861 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 862 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 863 864 /* release VCPU reset to boot */ 865 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 866 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 867 868 /* enable LMI MC and UMC channels */ 869 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 870 UVD, 0, mmUVD_LMI_CTRL2), 871 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 872 873 /* enable master interrupt */ 874 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 875 UVD, 0, mmUVD_MASTINT_EN), 876 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 877 878 if (indirect) 879 amdgpu_vcn_psp_update_sram(adev, 0, 0); 880 881 /* force RBC into idle state */ 882 rb_bufsz = order_base_2(ring->ring_size); 883 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 884 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 885 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 886 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 887 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 888 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 889 890 /* Stall DPG before WPTR/RPTR reset */ 891 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 892 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 893 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 894 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 895 896 /* set the write pointer delay */ 897 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 898 899 /* set the wb address */ 900 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 901 (upper_32_bits(ring->gpu_addr) >> 2)); 902 903 /* program the RB_BASE for ring buffer */ 904 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 905 lower_32_bits(ring->gpu_addr)); 906 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 907 upper_32_bits(ring->gpu_addr)); 908 909 /* Initialize the ring buffer's read and write pointers */ 910 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 911 912 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 913 914 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 915 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 916 lower_32_bits(ring->wptr)); 917 918 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 919 /* Unstall DPG */ 920 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 921 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 922 return 0; 923 } 924 925 static int vcn_v2_0_start(struct amdgpu_device *adev) 926 { 927 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 928 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 929 uint32_t rb_bufsz, tmp; 930 uint32_t lmi_swap_cntl; 931 int i, j, r; 932 933 if (adev->pm.dpm_enabled) 934 amdgpu_dpm_enable_uvd(adev, true); 935 936 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 937 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 938 939 vcn_v2_0_disable_static_power_gating(adev); 940 941 /* set uvd status busy */ 942 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 943 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 944 945 /*SW clock gating */ 946 vcn_v2_0_disable_clock_gating(adev); 947 948 /* enable VCPU clock */ 949 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 950 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 951 952 /* disable master interrupt */ 953 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 954 ~UVD_MASTINT_EN__VCPU_EN_MASK); 955 956 /* setup mmUVD_LMI_CTRL */ 957 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 958 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 959 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 960 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 961 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 962 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 963 964 /* setup mmUVD_MPC_CNTL */ 965 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 966 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 967 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 968 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 969 970 /* setup UVD_MPC_SET_MUXA0 */ 971 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 972 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 973 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 974 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 975 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 976 977 /* setup UVD_MPC_SET_MUXB0 */ 978 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 979 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 980 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 981 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 982 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 983 984 /* setup mmUVD_MPC_SET_MUX */ 985 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 986 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 987 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 988 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 989 990 vcn_v2_0_mc_resume(adev); 991 992 /* release VCPU reset to boot */ 993 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 994 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 995 996 /* enable LMI MC and UMC channels */ 997 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 998 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 999 1000 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1001 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1002 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1003 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1004 1005 /* disable byte swapping */ 1006 lmi_swap_cntl = 0; 1007 #ifdef __BIG_ENDIAN 1008 /* swap (8 in 32) RB and IB */ 1009 lmi_swap_cntl = 0xa; 1010 #endif 1011 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1012 1013 for (i = 0; i < 10; ++i) { 1014 uint32_t status; 1015 1016 for (j = 0; j < 100; ++j) { 1017 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1018 if (status & 2) 1019 break; 1020 mdelay(10); 1021 } 1022 r = 0; 1023 if (status & 2) 1024 break; 1025 1026 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1027 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1028 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1029 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1030 mdelay(10); 1031 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1032 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1033 mdelay(10); 1034 r = -1; 1035 } 1036 1037 if (r) { 1038 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1039 return r; 1040 } 1041 1042 /* enable master interrupt */ 1043 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1044 UVD_MASTINT_EN__VCPU_EN_MASK, 1045 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1046 1047 /* clear the busy bit of VCN_STATUS */ 1048 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1049 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1050 1051 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1052 1053 /* force RBC into idle state */ 1054 rb_bufsz = order_base_2(ring->ring_size); 1055 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1056 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1057 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1060 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1061 1062 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1063 /* program the RB_BASE for ring buffer */ 1064 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1065 lower_32_bits(ring->gpu_addr)); 1066 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1067 upper_32_bits(ring->gpu_addr)); 1068 1069 /* Initialize the ring buffer's read and write pointers */ 1070 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1071 1072 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1073 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1074 lower_32_bits(ring->wptr)); 1075 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1076 1077 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1078 ring = &adev->vcn.inst->ring_enc[0]; 1079 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1080 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1081 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1082 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1083 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1084 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1085 1086 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1087 ring = &adev->vcn.inst->ring_enc[1]; 1088 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1089 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1090 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1091 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1092 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1093 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1094 1095 return 0; 1096 } 1097 1098 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1099 { 1100 struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 1101 uint32_t tmp; 1102 1103 vcn_v2_0_pause_dpg_mode(adev, 0, &state); 1104 /* Wait for power status to be 1 */ 1105 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1106 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1107 1108 /* wait for read ptr to be equal to write ptr */ 1109 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1110 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1111 1112 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1113 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1114 1115 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1117 1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1119 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1120 1121 /* disable dynamic power gating mode */ 1122 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1123 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1124 1125 return 0; 1126 } 1127 1128 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1129 { 1130 uint32_t tmp; 1131 int r; 1132 1133 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1134 r = vcn_v2_0_stop_dpg_mode(adev); 1135 if (r) 1136 return r; 1137 goto power_off; 1138 } 1139 1140 /* wait for uvd idle */ 1141 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1142 if (r) 1143 return r; 1144 1145 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1146 UVD_LMI_STATUS__READ_CLEAN_MASK | 1147 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1148 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1149 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1150 if (r) 1151 return r; 1152 1153 /* stall UMC channel */ 1154 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1155 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1156 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1157 1158 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1159 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1160 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1161 if (r) 1162 return r; 1163 1164 /* disable VCPU clock */ 1165 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1166 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1167 1168 /* reset LMI UMC */ 1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1170 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1171 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1172 1173 /* reset LMI */ 1174 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1175 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1176 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1177 1178 /* reset VCPU */ 1179 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1180 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1181 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1182 1183 /* clear status */ 1184 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1185 1186 vcn_v2_0_enable_clock_gating(adev); 1187 vcn_v2_0_enable_static_power_gating(adev); 1188 1189 power_off: 1190 if (adev->pm.dpm_enabled) 1191 amdgpu_dpm_enable_uvd(adev, false); 1192 1193 return 0; 1194 } 1195 1196 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1197 int inst_idx, struct dpg_pause_state *new_state) 1198 { 1199 struct amdgpu_ring *ring; 1200 uint32_t reg_data = 0; 1201 int ret_code; 1202 1203 /* pause/unpause if state is changed */ 1204 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1205 DRM_DEBUG("dpg pause state changed %d -> %d", 1206 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1207 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1208 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1209 1210 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1211 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1212 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1213 1214 if (!ret_code) { 1215 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 1216 /* pause DPG */ 1217 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1218 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1219 1220 /* wait for ACK */ 1221 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1222 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1223 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1224 1225 /* Stall DPG before WPTR/RPTR reset */ 1226 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1227 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1228 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1229 /* Restore */ 1230 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1231 ring = &adev->vcn.inst->ring_enc[0]; 1232 ring->wptr = 0; 1233 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1235 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1238 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1239 1240 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1241 ring = &adev->vcn.inst->ring_enc[1]; 1242 ring->wptr = 0; 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1248 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1249 1250 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1251 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1252 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1253 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1254 /* Unstall DPG */ 1255 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1256 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1257 1258 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1259 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1260 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1261 } 1262 } else { 1263 /* unpause dpg, no need to wait */ 1264 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1265 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1266 } 1267 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static bool vcn_v2_0_is_idle(void *handle) 1274 { 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 1277 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1278 } 1279 1280 static int vcn_v2_0_wait_for_idle(void *handle) 1281 { 1282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1283 int ret; 1284 1285 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1286 UVD_STATUS__IDLE); 1287 1288 return ret; 1289 } 1290 1291 static int vcn_v2_0_set_clockgating_state(void *handle, 1292 enum amd_clockgating_state state) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 bool enable = (state == AMD_CG_STATE_GATE); 1296 1297 if (amdgpu_sriov_vf(adev)) 1298 return 0; 1299 1300 if (enable) { 1301 /* wait for STATUS to clear */ 1302 if (!vcn_v2_0_is_idle(handle)) 1303 return -EBUSY; 1304 vcn_v2_0_enable_clock_gating(adev); 1305 } else { 1306 /* disable HW gating and enable Sw gating */ 1307 vcn_v2_0_disable_clock_gating(adev); 1308 } 1309 return 0; 1310 } 1311 1312 /** 1313 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1314 * 1315 * @ring: amdgpu_ring pointer 1316 * 1317 * Returns the current hardware read pointer 1318 */ 1319 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1320 { 1321 struct amdgpu_device *adev = ring->adev; 1322 1323 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1324 } 1325 1326 /** 1327 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1328 * 1329 * @ring: amdgpu_ring pointer 1330 * 1331 * Returns the current hardware write pointer 1332 */ 1333 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1334 { 1335 struct amdgpu_device *adev = ring->adev; 1336 1337 if (ring->use_doorbell) 1338 return *ring->wptr_cpu_addr; 1339 else 1340 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1341 } 1342 1343 /** 1344 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1345 * 1346 * @ring: amdgpu_ring pointer 1347 * 1348 * Commits the write pointer to the hardware 1349 */ 1350 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1351 { 1352 struct amdgpu_device *adev = ring->adev; 1353 1354 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1355 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1356 lower_32_bits(ring->wptr) | 0x80000000); 1357 1358 if (ring->use_doorbell) { 1359 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1360 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1361 } else { 1362 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1363 } 1364 } 1365 1366 /** 1367 * vcn_v2_0_dec_ring_insert_start - insert a start command 1368 * 1369 * @ring: amdgpu_ring pointer 1370 * 1371 * Write a start command to the ring. 1372 */ 1373 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1374 { 1375 struct amdgpu_device *adev = ring->adev; 1376 1377 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1378 amdgpu_ring_write(ring, 0); 1379 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1380 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1381 } 1382 1383 /** 1384 * vcn_v2_0_dec_ring_insert_end - insert a end command 1385 * 1386 * @ring: amdgpu_ring pointer 1387 * 1388 * Write a end command to the ring. 1389 */ 1390 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1391 { 1392 struct amdgpu_device *adev = ring->adev; 1393 1394 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1395 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1396 } 1397 1398 /** 1399 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1400 * 1401 * @ring: amdgpu_ring pointer 1402 * @count: the number of NOP packets to insert 1403 * 1404 * Write a nop command to the ring. 1405 */ 1406 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1407 { 1408 struct amdgpu_device *adev = ring->adev; 1409 int i; 1410 1411 WARN_ON(ring->wptr % 2 || count % 2); 1412 1413 for (i = 0; i < count / 2; i++) { 1414 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); 1415 amdgpu_ring_write(ring, 0); 1416 } 1417 } 1418 1419 /** 1420 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1421 * 1422 * @ring: amdgpu_ring pointer 1423 * @addr: address 1424 * @seq: sequence number 1425 * @flags: fence related flags 1426 * 1427 * Write a fence and a trap command to the ring. 1428 */ 1429 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1430 unsigned flags) 1431 { 1432 struct amdgpu_device *adev = ring->adev; 1433 1434 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1435 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); 1436 amdgpu_ring_write(ring, seq); 1437 1438 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1439 amdgpu_ring_write(ring, addr & 0xffffffff); 1440 1441 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1442 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1443 1444 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1445 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1446 1447 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1448 amdgpu_ring_write(ring, 0); 1449 1450 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1451 amdgpu_ring_write(ring, 0); 1452 1453 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1454 1455 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1456 } 1457 1458 /** 1459 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1460 * 1461 * @ring: amdgpu_ring pointer 1462 * @job: job to retrieve vmid from 1463 * @ib: indirect buffer to execute 1464 * @flags: unused 1465 * 1466 * Write ring commands to execute the indirect buffer 1467 */ 1468 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1469 struct amdgpu_job *job, 1470 struct amdgpu_ib *ib, 1471 uint32_t flags) 1472 { 1473 struct amdgpu_device *adev = ring->adev; 1474 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1475 1476 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); 1477 amdgpu_ring_write(ring, vmid); 1478 1479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); 1480 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1481 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); 1482 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1483 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); 1484 amdgpu_ring_write(ring, ib->length_dw); 1485 } 1486 1487 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1488 uint32_t val, uint32_t mask) 1489 { 1490 struct amdgpu_device *adev = ring->adev; 1491 1492 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1493 amdgpu_ring_write(ring, reg << 2); 1494 1495 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1496 amdgpu_ring_write(ring, val); 1497 1498 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); 1499 amdgpu_ring_write(ring, mask); 1500 1501 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1502 1503 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1504 } 1505 1506 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1507 unsigned vmid, uint64_t pd_addr) 1508 { 1509 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1510 uint32_t data0, data1, mask; 1511 1512 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1513 1514 /* wait for register write */ 1515 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1516 data1 = lower_32_bits(pd_addr); 1517 mask = 0xffffffff; 1518 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1519 } 1520 1521 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1522 uint32_t reg, uint32_t val) 1523 { 1524 struct amdgpu_device *adev = ring->adev; 1525 1526 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1527 amdgpu_ring_write(ring, reg << 2); 1528 1529 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1530 amdgpu_ring_write(ring, val); 1531 1532 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1533 1534 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1535 } 1536 1537 /** 1538 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1539 * 1540 * @ring: amdgpu_ring pointer 1541 * 1542 * Returns the current hardware enc read pointer 1543 */ 1544 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1545 { 1546 struct amdgpu_device *adev = ring->adev; 1547 1548 if (ring == &adev->vcn.inst->ring_enc[0]) 1549 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1550 else 1551 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1552 } 1553 1554 /** 1555 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1556 * 1557 * @ring: amdgpu_ring pointer 1558 * 1559 * Returns the current hardware enc write pointer 1560 */ 1561 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1562 { 1563 struct amdgpu_device *adev = ring->adev; 1564 1565 if (ring == &adev->vcn.inst->ring_enc[0]) { 1566 if (ring->use_doorbell) 1567 return *ring->wptr_cpu_addr; 1568 else 1569 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1570 } else { 1571 if (ring->use_doorbell) 1572 return *ring->wptr_cpu_addr; 1573 else 1574 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1575 } 1576 } 1577 1578 /** 1579 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1580 * 1581 * @ring: amdgpu_ring pointer 1582 * 1583 * Commits the enc write pointer to the hardware 1584 */ 1585 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1586 { 1587 struct amdgpu_device *adev = ring->adev; 1588 1589 if (ring == &adev->vcn.inst->ring_enc[0]) { 1590 if (ring->use_doorbell) { 1591 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1592 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1593 } else { 1594 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1595 } 1596 } else { 1597 if (ring->use_doorbell) { 1598 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 1599 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1600 } else { 1601 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1602 } 1603 } 1604 } 1605 1606 /** 1607 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1608 * 1609 * @ring: amdgpu_ring pointer 1610 * @addr: address 1611 * @seq: sequence number 1612 * @flags: fence related flags 1613 * 1614 * Write enc a fence and a trap command to the ring. 1615 */ 1616 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1617 u64 seq, unsigned flags) 1618 { 1619 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1620 1621 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1622 amdgpu_ring_write(ring, addr); 1623 amdgpu_ring_write(ring, upper_32_bits(addr)); 1624 amdgpu_ring_write(ring, seq); 1625 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1626 } 1627 1628 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1629 { 1630 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1631 } 1632 1633 /** 1634 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1635 * 1636 * @ring: amdgpu_ring pointer 1637 * @job: job to retrive vmid from 1638 * @ib: indirect buffer to execute 1639 * @flags: unused 1640 * 1641 * Write enc ring commands to execute the indirect buffer 1642 */ 1643 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1644 struct amdgpu_job *job, 1645 struct amdgpu_ib *ib, 1646 uint32_t flags) 1647 { 1648 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1649 1650 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1651 amdgpu_ring_write(ring, vmid); 1652 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1653 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1654 amdgpu_ring_write(ring, ib->length_dw); 1655 } 1656 1657 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1658 uint32_t val, uint32_t mask) 1659 { 1660 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1661 amdgpu_ring_write(ring, reg << 2); 1662 amdgpu_ring_write(ring, mask); 1663 amdgpu_ring_write(ring, val); 1664 } 1665 1666 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1667 unsigned int vmid, uint64_t pd_addr) 1668 { 1669 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1670 1671 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1672 1673 /* wait for reg writes */ 1674 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1675 vmid * hub->ctx_addr_distance, 1676 lower_32_bits(pd_addr), 0xffffffff); 1677 } 1678 1679 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1680 { 1681 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1682 amdgpu_ring_write(ring, reg << 2); 1683 amdgpu_ring_write(ring, val); 1684 } 1685 1686 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1687 struct amdgpu_irq_src *source, 1688 unsigned type, 1689 enum amdgpu_interrupt_state state) 1690 { 1691 return 0; 1692 } 1693 1694 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1695 struct amdgpu_irq_src *source, 1696 struct amdgpu_iv_entry *entry) 1697 { 1698 DRM_DEBUG("IH: VCN TRAP\n"); 1699 1700 switch (entry->src_id) { 1701 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1702 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1703 break; 1704 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1705 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1706 break; 1707 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1708 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1709 break; 1710 default: 1711 DRM_ERROR("Unhandled interrupt: %d %d\n", 1712 entry->src_id, entry->src_data[0]); 1713 break; 1714 } 1715 1716 return 0; 1717 } 1718 1719 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1720 { 1721 struct amdgpu_device *adev = ring->adev; 1722 uint32_t tmp = 0; 1723 unsigned i; 1724 int r; 1725 1726 if (amdgpu_sriov_vf(adev)) 1727 return 0; 1728 1729 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1730 r = amdgpu_ring_alloc(ring, 4); 1731 if (r) 1732 return r; 1733 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1734 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1735 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 1736 amdgpu_ring_write(ring, 0xDEADBEEF); 1737 amdgpu_ring_commit(ring); 1738 for (i = 0; i < adev->usec_timeout; i++) { 1739 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1740 if (tmp == 0xDEADBEEF) 1741 break; 1742 udelay(1); 1743 } 1744 1745 if (i >= adev->usec_timeout) 1746 r = -ETIMEDOUT; 1747 1748 return r; 1749 } 1750 1751 1752 static int vcn_v2_0_set_powergating_state(void *handle, 1753 enum amd_powergating_state state) 1754 { 1755 /* This doesn't actually powergate the VCN block. 1756 * That's done in the dpm code via the SMC. This 1757 * just re-inits the block as necessary. The actual 1758 * gating still happens in the dpm code. We should 1759 * revisit this when there is a cleaner line between 1760 * the smc and the hw blocks 1761 */ 1762 int ret; 1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1764 1765 if (amdgpu_sriov_vf(adev)) { 1766 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1767 return 0; 1768 } 1769 1770 if (state == adev->vcn.cur_state) 1771 return 0; 1772 1773 if (state == AMD_PG_STATE_GATE) 1774 ret = vcn_v2_0_stop(adev); 1775 else 1776 ret = vcn_v2_0_start(adev); 1777 1778 if (!ret) 1779 adev->vcn.cur_state = state; 1780 return ret; 1781 } 1782 1783 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1784 struct amdgpu_mm_table *table) 1785 { 1786 uint32_t data = 0, loop; 1787 uint64_t addr = table->gpu_addr; 1788 struct mmsch_v2_0_init_header *header; 1789 uint32_t size; 1790 int i; 1791 1792 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1793 size = header->header_size + header->vcn_table_size; 1794 1795 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1796 * of memory descriptor location 1797 */ 1798 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1799 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1800 1801 /* 2, update vmid of descriptor */ 1802 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1803 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1804 /* use domain0 for MM scheduler */ 1805 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1806 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1807 1808 /* 3, notify mmsch about the size of this descriptor */ 1809 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1810 1811 /* 4, set resp to zero */ 1812 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1813 1814 adev->vcn.inst->ring_dec.wptr = 0; 1815 adev->vcn.inst->ring_dec.wptr_old = 0; 1816 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1817 1818 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1819 adev->vcn.inst->ring_enc[i].wptr = 0; 1820 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1821 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1822 } 1823 1824 /* 5, kick off the initialization and wait until 1825 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1826 */ 1827 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1828 1829 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1830 loop = 1000; 1831 while ((data & 0x10000002) != 0x10000002) { 1832 udelay(10); 1833 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1834 loop--; 1835 if (!loop) 1836 break; 1837 } 1838 1839 if (!loop) { 1840 DRM_ERROR("failed to init MMSCH, " \ 1841 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1842 return -EBUSY; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1849 { 1850 int r; 1851 uint32_t tmp; 1852 struct amdgpu_ring *ring; 1853 uint32_t offset, size; 1854 uint32_t table_size = 0; 1855 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1856 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1857 struct mmsch_v2_0_cmd_end end = { {0} }; 1858 struct mmsch_v2_0_init_header *header; 1859 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1860 uint8_t i = 0; 1861 1862 header = (struct mmsch_v2_0_init_header *)init_table; 1863 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1864 direct_rd_mod_wt.cmd_header.command_type = 1865 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1866 end.cmd_header.command_type = MMSCH_COMMAND__END; 1867 1868 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1869 header->version = MMSCH_VERSION; 1870 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1871 1872 header->vcn_table_offset = header->header_size; 1873 1874 init_table += header->vcn_table_offset; 1875 1876 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[0]->size + 4); 1877 1878 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1879 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1880 0xFFFFFFFF, 0x00000004); 1881 1882 /* mc resume*/ 1883 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1884 MMSCH_V2_0_INSERT_DIRECT_WT( 1885 SOC15_REG_OFFSET(UVD, i, 1886 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1887 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); 1888 MMSCH_V2_0_INSERT_DIRECT_WT( 1889 SOC15_REG_OFFSET(UVD, i, 1890 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1891 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); 1892 offset = 0; 1893 } else { 1894 MMSCH_V2_0_INSERT_DIRECT_WT( 1895 SOC15_REG_OFFSET(UVD, i, 1896 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1897 lower_32_bits(adev->vcn.inst->gpu_addr)); 1898 MMSCH_V2_0_INSERT_DIRECT_WT( 1899 SOC15_REG_OFFSET(UVD, i, 1900 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1901 upper_32_bits(adev->vcn.inst->gpu_addr)); 1902 offset = size; 1903 } 1904 1905 MMSCH_V2_0_INSERT_DIRECT_WT( 1906 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 1907 0); 1908 MMSCH_V2_0_INSERT_DIRECT_WT( 1909 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 1910 size); 1911 1912 MMSCH_V2_0_INSERT_DIRECT_WT( 1913 SOC15_REG_OFFSET(UVD, i, 1914 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1915 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 1916 MMSCH_V2_0_INSERT_DIRECT_WT( 1917 SOC15_REG_OFFSET(UVD, i, 1918 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1919 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 1920 MMSCH_V2_0_INSERT_DIRECT_WT( 1921 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 1922 0); 1923 MMSCH_V2_0_INSERT_DIRECT_WT( 1924 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 1925 AMDGPU_VCN_STACK_SIZE); 1926 1927 MMSCH_V2_0_INSERT_DIRECT_WT( 1928 SOC15_REG_OFFSET(UVD, i, 1929 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1930 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 1931 AMDGPU_VCN_STACK_SIZE)); 1932 MMSCH_V2_0_INSERT_DIRECT_WT( 1933 SOC15_REG_OFFSET(UVD, i, 1934 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1935 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 1936 AMDGPU_VCN_STACK_SIZE)); 1937 MMSCH_V2_0_INSERT_DIRECT_WT( 1938 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 1939 0); 1940 MMSCH_V2_0_INSERT_DIRECT_WT( 1941 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 1942 AMDGPU_VCN_CONTEXT_SIZE); 1943 1944 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { 1945 ring = &adev->vcn.inst->ring_enc[r]; 1946 ring->wptr = 0; 1947 MMSCH_V2_0_INSERT_DIRECT_WT( 1948 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 1949 lower_32_bits(ring->gpu_addr)); 1950 MMSCH_V2_0_INSERT_DIRECT_WT( 1951 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 1952 upper_32_bits(ring->gpu_addr)); 1953 MMSCH_V2_0_INSERT_DIRECT_WT( 1954 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 1955 ring->ring_size / 4); 1956 } 1957 1958 ring = &adev->vcn.inst->ring_dec; 1959 ring->wptr = 0; 1960 MMSCH_V2_0_INSERT_DIRECT_WT( 1961 SOC15_REG_OFFSET(UVD, i, 1962 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1963 lower_32_bits(ring->gpu_addr)); 1964 MMSCH_V2_0_INSERT_DIRECT_WT( 1965 SOC15_REG_OFFSET(UVD, i, 1966 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1967 upper_32_bits(ring->gpu_addr)); 1968 /* force RBC into idle state */ 1969 tmp = order_base_2(ring->ring_size); 1970 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1971 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1972 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1973 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1974 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1975 MMSCH_V2_0_INSERT_DIRECT_WT( 1976 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 1977 1978 /* add end packet */ 1979 tmp = sizeof(struct mmsch_v2_0_cmd_end); 1980 memcpy((void *)init_table, &end, tmp); 1981 table_size += (tmp / 4); 1982 header->vcn_table_size = table_size; 1983 1984 } 1985 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 1986 } 1987 1988 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 1989 .name = "vcn_v2_0", 1990 .early_init = vcn_v2_0_early_init, 1991 .late_init = NULL, 1992 .sw_init = vcn_v2_0_sw_init, 1993 .sw_fini = vcn_v2_0_sw_fini, 1994 .hw_init = vcn_v2_0_hw_init, 1995 .hw_fini = vcn_v2_0_hw_fini, 1996 .suspend = vcn_v2_0_suspend, 1997 .resume = vcn_v2_0_resume, 1998 .is_idle = vcn_v2_0_is_idle, 1999 .wait_for_idle = vcn_v2_0_wait_for_idle, 2000 .check_soft_reset = NULL, 2001 .pre_soft_reset = NULL, 2002 .soft_reset = NULL, 2003 .post_soft_reset = NULL, 2004 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 2005 .set_powergating_state = vcn_v2_0_set_powergating_state, 2006 .dump_ip_state = NULL, 2007 .print_ip_state = NULL, 2008 }; 2009 2010 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2011 .type = AMDGPU_RING_TYPE_VCN_DEC, 2012 .align_mask = 0xf, 2013 .secure_submission_supported = true, 2014 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2015 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2016 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2017 .emit_frame_size = 2018 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2019 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2020 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2021 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2022 6, 2023 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2024 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2025 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2026 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2027 .test_ring = vcn_v2_0_dec_ring_test_ring, 2028 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2029 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2030 .insert_start = vcn_v2_0_dec_ring_insert_start, 2031 .insert_end = vcn_v2_0_dec_ring_insert_end, 2032 .pad_ib = amdgpu_ring_generic_pad_ib, 2033 .begin_use = amdgpu_vcn_ring_begin_use, 2034 .end_use = amdgpu_vcn_ring_end_use, 2035 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2036 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2037 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2038 }; 2039 2040 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2041 .type = AMDGPU_RING_TYPE_VCN_ENC, 2042 .align_mask = 0x3f, 2043 .nop = VCN_ENC_CMD_NO_OP, 2044 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2045 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2046 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2047 .emit_frame_size = 2048 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2049 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2050 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2051 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2052 1, /* vcn_v2_0_enc_ring_insert_end */ 2053 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2054 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2055 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2056 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2057 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2058 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2059 .insert_nop = amdgpu_ring_insert_nop, 2060 .insert_end = vcn_v2_0_enc_ring_insert_end, 2061 .pad_ib = amdgpu_ring_generic_pad_ib, 2062 .begin_use = amdgpu_vcn_ring_begin_use, 2063 .end_use = amdgpu_vcn_ring_end_use, 2064 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2065 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2066 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2067 }; 2068 2069 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2070 { 2071 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2072 } 2073 2074 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2075 { 2076 int i; 2077 2078 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2079 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2080 } 2081 2082 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2083 .set = vcn_v2_0_set_interrupt_state, 2084 .process = vcn_v2_0_process_interrupt, 2085 }; 2086 2087 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2088 { 2089 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; 2090 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2091 } 2092 2093 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2094 { 2095 .type = AMD_IP_BLOCK_TYPE_VCN, 2096 .major = 2, 2097 .minor = 0, 2098 .rev = 0, 2099 .funcs = &vcn_v2_0_ip_funcs, 2100 }; 2101