1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_uvd.h" 28 #include "amdgpu_cs.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 #include "mmsch_v1_0.h" 33 34 #include "uvd/uvd_7_0_offset.h" 35 #include "uvd/uvd_7_0_sh_mask.h" 36 #include "vce/vce_4_0_offset.h" 37 #include "vce/vce_4_0_default.h" 38 #include "vce/vce_4_0_sh_mask.h" 39 #include "nbif/nbif_6_1_offset.h" 40 #include "mmhub/mmhub_1_0_offset.h" 41 #include "mmhub/mmhub_1_0_sh_mask.h" 42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 43 44 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 46 //UVD_PG0_CC_UVD_HARVESTING 47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 49 50 #define UVD7_MAX_HW_INSTANCES_VEGA20 2 51 52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int uvd_v7_0_start(struct amdgpu_device *adev); 56 static void uvd_v7_0_stop(struct amdgpu_device *adev); 57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 58 59 static int amdgpu_ih_clientid_uvds[] = { 60 SOC15_IH_CLIENTID_UVD, 61 SOC15_IH_CLIENTID_UVD1 62 }; 63 64 /** 65 * uvd_v7_0_ring_get_rptr - get read pointer 66 * 67 * @ring: amdgpu_ring pointer 68 * 69 * Returns the current hardware read pointer 70 */ 71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 72 { 73 struct amdgpu_device *adev = ring->adev; 74 75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 76 } 77 78 /** 79 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 80 * 81 * @ring: amdgpu_ring pointer 82 * 83 * Returns the current hardware enc read pointer 84 */ 85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 86 { 87 struct amdgpu_device *adev = ring->adev; 88 89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 91 else 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 93 } 94 95 /** 96 * uvd_v7_0_ring_get_wptr - get write pointer 97 * 98 * @ring: amdgpu_ring pointer 99 * 100 * Returns the current hardware write pointer 101 */ 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 103 { 104 struct amdgpu_device *adev = ring->adev; 105 106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 107 } 108 109 /** 110 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 111 * 112 * @ring: amdgpu_ring pointer 113 * 114 * Returns the current hardware enc write pointer 115 */ 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 117 { 118 struct amdgpu_device *adev = ring->adev; 119 120 if (ring->use_doorbell) 121 return *ring->wptr_cpu_addr; 122 123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 125 else 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 127 } 128 129 /** 130 * uvd_v7_0_ring_set_wptr - set write pointer 131 * 132 * @ring: amdgpu_ring pointer 133 * 134 * Commits the write pointer to the hardware 135 */ 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 137 { 138 struct amdgpu_device *adev = ring->adev; 139 140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 141 } 142 143 /** 144 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 145 * 146 * @ring: amdgpu_ring pointer 147 * 148 * Commits the enc write pointer to the hardware 149 */ 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 151 { 152 struct amdgpu_device *adev = ring->adev; 153 154 if (ring->use_doorbell) { 155 /* XXX check if swapping is necessary on BE */ 156 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); 157 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 158 return; 159 } 160 161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 163 lower_32_bits(ring->wptr)); 164 else 165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 166 lower_32_bits(ring->wptr)); 167 } 168 169 /** 170 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 171 * 172 * @ring: the engine to test on 173 * 174 */ 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 176 { 177 struct amdgpu_device *adev = ring->adev; 178 uint32_t rptr; 179 unsigned i; 180 int r; 181 182 if (amdgpu_sriov_vf(adev)) 183 return 0; 184 185 r = amdgpu_ring_alloc(ring, 16); 186 if (r) 187 return r; 188 189 rptr = amdgpu_ring_get_rptr(ring); 190 191 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 192 amdgpu_ring_commit(ring); 193 194 for (i = 0; i < adev->usec_timeout; i++) { 195 if (amdgpu_ring_get_rptr(ring) != rptr) 196 break; 197 udelay(1); 198 } 199 200 if (i >= adev->usec_timeout) 201 r = -ETIMEDOUT; 202 203 return r; 204 } 205 206 /** 207 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 208 * 209 * @ring: ring we should submit the msg to 210 * @handle: session handle to use 211 * @bo: amdgpu object for which we query the offset 212 * @fence: optional fence to return 213 * 214 * Open up a stream for HW test 215 */ 216 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle, 217 struct amdgpu_bo *bo, 218 struct dma_fence **fence) 219 { 220 const unsigned ib_size_dw = 16; 221 struct amdgpu_job *job; 222 struct amdgpu_ib *ib; 223 struct dma_fence *f = NULL; 224 uint64_t addr; 225 int i, r; 226 227 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 228 AMDGPU_IB_POOL_DIRECT, 229 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 230 &job); 231 if (r) 232 return r; 233 234 ib = &job->ibs[0]; 235 addr = amdgpu_bo_gpu_offset(bo); 236 237 ib->length_dw = 0; 238 ib->ptr[ib->length_dw++] = 0x00000018; 239 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 240 ib->ptr[ib->length_dw++] = handle; 241 ib->ptr[ib->length_dw++] = 0x00000000; 242 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 243 ib->ptr[ib->length_dw++] = addr; 244 245 ib->ptr[ib->length_dw++] = 0x00000014; 246 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 247 ib->ptr[ib->length_dw++] = 0x0000001c; 248 ib->ptr[ib->length_dw++] = 0x00000000; 249 ib->ptr[ib->length_dw++] = 0x00000000; 250 251 ib->ptr[ib->length_dw++] = 0x00000008; 252 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 253 254 for (i = ib->length_dw; i < ib_size_dw; ++i) 255 ib->ptr[i] = 0x0; 256 257 r = amdgpu_job_submit_direct(job, ring, &f); 258 if (r) 259 goto err; 260 261 if (fence) 262 *fence = dma_fence_get(f); 263 dma_fence_put(f); 264 return 0; 265 266 err: 267 amdgpu_job_free(job); 268 return r; 269 } 270 271 /** 272 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 273 * 274 * @ring: ring we should submit the msg to 275 * @handle: session handle to use 276 * @bo: amdgpu object for which we query the offset 277 * @fence: optional fence to return 278 * 279 * Close up a stream for HW test or if userspace failed to do so 280 */ 281 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle, 282 struct amdgpu_bo *bo, 283 struct dma_fence **fence) 284 { 285 const unsigned ib_size_dw = 16; 286 struct amdgpu_job *job; 287 struct amdgpu_ib *ib; 288 struct dma_fence *f = NULL; 289 uint64_t addr; 290 int i, r; 291 292 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 293 AMDGPU_IB_POOL_DIRECT, 294 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 295 &job); 296 if (r) 297 return r; 298 299 ib = &job->ibs[0]; 300 addr = amdgpu_bo_gpu_offset(bo); 301 302 ib->length_dw = 0; 303 ib->ptr[ib->length_dw++] = 0x00000018; 304 ib->ptr[ib->length_dw++] = 0x00000001; 305 ib->ptr[ib->length_dw++] = handle; 306 ib->ptr[ib->length_dw++] = 0x00000000; 307 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 308 ib->ptr[ib->length_dw++] = addr; 309 310 ib->ptr[ib->length_dw++] = 0x00000014; 311 ib->ptr[ib->length_dw++] = 0x00000002; 312 ib->ptr[ib->length_dw++] = 0x0000001c; 313 ib->ptr[ib->length_dw++] = 0x00000000; 314 ib->ptr[ib->length_dw++] = 0x00000000; 315 316 ib->ptr[ib->length_dw++] = 0x00000008; 317 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 318 319 for (i = ib->length_dw; i < ib_size_dw; ++i) 320 ib->ptr[i] = 0x0; 321 322 r = amdgpu_job_submit_direct(job, ring, &f); 323 if (r) 324 goto err; 325 326 if (fence) 327 *fence = dma_fence_get(f); 328 dma_fence_put(f); 329 return 0; 330 331 err: 332 amdgpu_job_free(job); 333 return r; 334 } 335 336 /** 337 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 338 * 339 * @ring: the engine to test on 340 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 341 * 342 */ 343 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 344 { 345 struct dma_fence *fence = NULL; 346 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo; 347 long r; 348 349 r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL); 350 if (r) 351 goto error; 352 353 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence); 354 if (r) 355 goto error; 356 357 r = dma_fence_wait_timeout(fence, false, timeout); 358 if (r == 0) 359 r = -ETIMEDOUT; 360 else if (r > 0) 361 r = 0; 362 363 error: 364 dma_fence_put(fence); 365 return r; 366 } 367 368 static int uvd_v7_0_early_init(struct amdgpu_ip_block *ip_block) 369 { 370 struct amdgpu_device *adev = ip_block->adev; 371 372 if (adev->asic_type == CHIP_VEGA20) { 373 u32 harvest; 374 int i; 375 376 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 377 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 378 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 379 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 380 adev->uvd.harvest_config |= 1 << i; 381 } 382 } 383 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 384 AMDGPU_UVD_HARVEST_UVD1)) 385 /* both instances are harvested, disable the block */ 386 return -ENOENT; 387 } else { 388 adev->uvd.num_uvd_inst = 1; 389 } 390 391 if (amdgpu_sriov_vf(adev)) 392 adev->uvd.num_enc_rings = 1; 393 else 394 adev->uvd.num_enc_rings = 2; 395 uvd_v7_0_set_ring_funcs(adev); 396 uvd_v7_0_set_enc_ring_funcs(adev); 397 uvd_v7_0_set_irq_funcs(adev); 398 399 return 0; 400 } 401 402 static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 403 { 404 struct amdgpu_ring *ring; 405 406 int i, j, r; 407 struct amdgpu_device *adev = ip_block->adev; 408 409 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 410 if (adev->uvd.harvest_config & (1 << j)) 411 continue; 412 /* UVD TRAP */ 413 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 414 if (r) 415 return r; 416 417 /* UVD ENC TRAP */ 418 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 419 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 420 if (r) 421 return r; 422 } 423 } 424 425 r = amdgpu_uvd_sw_init(adev); 426 if (r) 427 return r; 428 429 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 430 const struct common_firmware_header *hdr; 431 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 432 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 433 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 434 adev->firmware.fw_size += 435 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 436 437 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 438 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 439 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 440 adev->firmware.fw_size += 441 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 442 } 443 drm_info(adev_to_drm(adev), "PSP loading UVD firmware\n"); 444 } 445 446 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 447 if (adev->uvd.harvest_config & (1 << j)) 448 continue; 449 if (!amdgpu_sriov_vf(adev)) { 450 ring = &adev->uvd.inst[j].ring; 451 ring->vm_hub = AMDGPU_MMHUB0(0); 452 sprintf(ring->name, "uvd_%d", ring->me); 453 r = amdgpu_ring_init(adev, ring, 512, 454 &adev->uvd.inst[j].irq, 0, 455 AMDGPU_RING_PRIO_DEFAULT, NULL); 456 if (r) 457 return r; 458 } 459 460 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 461 ring = &adev->uvd.inst[j].ring_enc[i]; 462 ring->vm_hub = AMDGPU_MMHUB0(0); 463 sprintf(ring->name, "uvd_enc_%d.%d", ring->me, i); 464 if (amdgpu_sriov_vf(adev)) { 465 ring->use_doorbell = true; 466 467 /* currently only use the first enconding ring for 468 * sriov, so set unused location for other unused rings. 469 */ 470 if (i == 0) 471 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2; 472 else 473 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1; 474 } 475 r = amdgpu_ring_init(adev, ring, 512, 476 &adev->uvd.inst[j].irq, 0, 477 AMDGPU_RING_PRIO_DEFAULT, NULL); 478 if (r) 479 return r; 480 } 481 } 482 483 r = amdgpu_uvd_resume(adev); 484 if (r) 485 return r; 486 487 r = amdgpu_virt_alloc_mm_table(adev); 488 if (r) 489 return r; 490 491 return r; 492 } 493 494 static int uvd_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 495 { 496 int i, j, r; 497 struct amdgpu_device *adev = ip_block->adev; 498 499 amdgpu_virt_free_mm_table(adev); 500 501 r = amdgpu_uvd_suspend(adev); 502 if (r) 503 return r; 504 505 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 506 if (adev->uvd.harvest_config & (1 << j)) 507 continue; 508 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 509 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 510 } 511 return amdgpu_uvd_sw_fini(adev); 512 } 513 514 /** 515 * uvd_v7_0_hw_init - start and test UVD block 516 * 517 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 518 * 519 * Initialize the hardware, boot up the VCPU and do some testing 520 */ 521 static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 522 { 523 struct amdgpu_device *adev = ip_block->adev; 524 struct amdgpu_ring *ring; 525 uint32_t tmp; 526 int i, j, r; 527 528 if (amdgpu_sriov_vf(adev)) 529 r = uvd_v7_0_sriov_start(adev); 530 else 531 r = uvd_v7_0_start(adev); 532 if (r) 533 goto done; 534 535 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 536 if (adev->uvd.harvest_config & (1 << j)) 537 continue; 538 ring = &adev->uvd.inst[j].ring; 539 540 if (!amdgpu_sriov_vf(adev)) { 541 r = amdgpu_ring_test_helper(ring); 542 if (r) 543 goto done; 544 545 r = amdgpu_ring_alloc(ring, 10); 546 if (r) { 547 drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); 548 goto done; 549 } 550 551 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 552 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 553 amdgpu_ring_write(ring, tmp); 554 amdgpu_ring_write(ring, 0xFFFFF); 555 556 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 557 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 558 amdgpu_ring_write(ring, tmp); 559 amdgpu_ring_write(ring, 0xFFFFF); 560 561 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 562 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 563 amdgpu_ring_write(ring, tmp); 564 amdgpu_ring_write(ring, 0xFFFFF); 565 566 /* Clear timeout status bits */ 567 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 568 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 569 amdgpu_ring_write(ring, 0x8); 570 571 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 572 mmUVD_SEMA_CNTL), 0)); 573 amdgpu_ring_write(ring, 3); 574 575 amdgpu_ring_commit(ring); 576 } 577 578 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 579 ring = &adev->uvd.inst[j].ring_enc[i]; 580 r = amdgpu_ring_test_helper(ring); 581 if (r) 582 goto done; 583 } 584 } 585 done: 586 if (!r) 587 drm_info(adev_to_drm(adev), "UVD and UVD ENC initialized successfully.\n"); 588 589 return r; 590 } 591 592 /** 593 * uvd_v7_0_hw_fini - stop the hardware block 594 * 595 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 596 * 597 * Stop the UVD block, mark ring as not ready any more 598 */ 599 static int uvd_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 600 { 601 struct amdgpu_device *adev = ip_block->adev; 602 603 cancel_delayed_work_sync(&adev->uvd.idle_work); 604 605 if (!amdgpu_sriov_vf(adev)) 606 uvd_v7_0_stop(adev); 607 else { 608 /* full access mode, so don't touch any UVD register */ 609 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 610 } 611 612 return 0; 613 } 614 615 static int uvd_v7_0_prepare_suspend(struct amdgpu_ip_block *ip_block) 616 { 617 struct amdgpu_device *adev = ip_block->adev; 618 619 return amdgpu_uvd_prepare_suspend(adev); 620 } 621 622 static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) 623 { 624 int r; 625 struct amdgpu_device *adev = ip_block->adev; 626 627 /* 628 * Proper cleanups before halting the HW engine: 629 * - cancel the delayed idle work 630 * - enable powergating 631 * - enable clockgating 632 * - disable dpm 633 * 634 * TODO: to align with the VCN implementation, move the 635 * jobs for clockgating/powergating/dpm setting to 636 * ->set_powergating_state(). 637 */ 638 cancel_delayed_work_sync(&adev->uvd.idle_work); 639 640 if (adev->pm.dpm_enabled) { 641 amdgpu_dpm_enable_uvd(adev, false); 642 } else { 643 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 644 /* shutdown the UVD block */ 645 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 646 AMD_PG_STATE_GATE); 647 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 648 AMD_CG_STATE_GATE); 649 } 650 651 r = uvd_v7_0_hw_fini(ip_block); 652 if (r) 653 return r; 654 655 return amdgpu_uvd_suspend(adev); 656 } 657 658 static int uvd_v7_0_resume(struct amdgpu_ip_block *ip_block) 659 { 660 int r; 661 662 r = amdgpu_uvd_resume(ip_block->adev); 663 if (r) 664 return r; 665 666 return uvd_v7_0_hw_init(ip_block); 667 } 668 669 /** 670 * uvd_v7_0_mc_resume - memory controller programming 671 * 672 * @adev: amdgpu_device pointer 673 * 674 * Let the UVD memory controller know it's offsets 675 */ 676 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 677 { 678 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 679 uint32_t offset; 680 int i; 681 682 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 683 if (adev->uvd.harvest_config & (1 << i)) 684 continue; 685 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 686 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 687 i == 0 ? 688 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo : 689 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 690 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 691 i == 0 ? 692 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi : 693 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 695 offset = 0; 696 } else { 697 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 698 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 699 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 700 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 701 offset = size; 702 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 703 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 704 } 705 706 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 707 708 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 709 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 710 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 711 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 712 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 713 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 714 715 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 716 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 717 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 718 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 719 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 720 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 721 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 722 723 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 724 adev->gfx.config.gb_addr_config); 725 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 726 adev->gfx.config.gb_addr_config); 727 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 728 adev->gfx.config.gb_addr_config); 729 730 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 731 } 732 } 733 734 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 735 struct amdgpu_mm_table *table) 736 { 737 uint32_t data = 0, loop; 738 uint64_t addr = table->gpu_addr; 739 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 740 uint32_t size; 741 int i; 742 743 size = header->header_size + header->vce_table_size + header->uvd_table_size; 744 745 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 746 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 747 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 748 749 /* 2, update vmid of descriptor */ 750 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 751 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 752 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 753 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 754 755 /* 3, notify mmsch about the size of this descriptor */ 756 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 757 758 /* 4, set resp to zero */ 759 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 760 761 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 762 if (adev->uvd.harvest_config & (1 << i)) 763 continue; 764 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 765 *adev->uvd.inst[i].ring_enc[0].wptr_cpu_addr = 0; 766 adev->uvd.inst[i].ring_enc[0].wptr = 0; 767 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 768 } 769 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 770 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 771 772 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 773 loop = 1000; 774 while ((data & 0x10000002) != 0x10000002) { 775 udelay(10); 776 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 777 loop--; 778 if (!loop) 779 break; 780 } 781 782 if (!loop) { 783 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 784 return -EBUSY; 785 } 786 787 return 0; 788 } 789 790 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 791 { 792 struct amdgpu_ring *ring; 793 uint32_t offset, size, tmp; 794 uint32_t table_size = 0; 795 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 796 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 797 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 798 struct mmsch_v1_0_cmd_end end = { {0} }; 799 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 800 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 801 uint8_t i = 0; 802 803 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 804 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 805 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 806 end.cmd_header.command_type = MMSCH_COMMAND__END; 807 808 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 809 header->version = MMSCH_VERSION; 810 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 811 812 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 813 header->uvd_table_offset = header->header_size; 814 else 815 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 816 817 init_table += header->uvd_table_offset; 818 819 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 820 if (adev->uvd.harvest_config & (1 << i)) 821 continue; 822 ring = &adev->uvd.inst[i].ring; 823 ring->wptr = 0; 824 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 825 826 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 827 0xFFFFFFFF, 0x00000004); 828 /* mc resume*/ 829 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 831 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 832 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 834 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 835 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 837 offset = 0; 838 } else { 839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 840 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 842 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 843 offset = size; 844 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 845 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 846 847 } 848 849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 850 851 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 852 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 853 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 854 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 855 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 856 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 857 858 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 859 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 860 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 861 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 862 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 863 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 864 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 865 866 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 867 /* mc resume end*/ 868 869 /* disable clock gating */ 870 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 871 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 872 873 /* disable interupt */ 874 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 875 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 876 877 /* stall UMC and register bus before resetting VCPU */ 878 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 879 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 880 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 881 882 /* put LMI, VCPU, RBC etc... into reset */ 883 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 884 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 885 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 886 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 887 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 888 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 889 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 890 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 891 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 892 893 /* initialize UVD memory controller */ 894 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 895 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 896 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 897 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 898 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 899 UVD_LMI_CTRL__REQ_MODE_MASK | 900 0x00100000L)); 901 902 /* take all subblocks out of reset, except VCPU */ 903 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 904 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 905 906 /* enable VCPU clock */ 907 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 908 UVD_VCPU_CNTL__CLK_EN_MASK); 909 910 /* enable master interrupt */ 911 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 912 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 913 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 914 915 /* clear the bit 4 of UVD_STATUS */ 916 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 917 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 918 919 /* force RBC into idle state */ 920 size = order_base_2(ring->ring_size); 921 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 922 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 924 925 ring = &adev->uvd.inst[i].ring_enc[0]; 926 ring->wptr = 0; 927 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 928 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 929 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 930 931 /* boot up the VCPU */ 932 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 933 934 /* enable UMC */ 935 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 936 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 937 938 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 939 } 940 /* add end packet */ 941 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 942 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 943 header->uvd_table_size = table_size; 944 945 } 946 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 947 } 948 949 /** 950 * uvd_v7_0_start - start UVD block 951 * 952 * @adev: amdgpu_device pointer 953 * 954 * Setup and start the UVD block 955 */ 956 static int uvd_v7_0_start(struct amdgpu_device *adev) 957 { 958 struct amdgpu_ring *ring; 959 uint32_t rb_bufsz, tmp; 960 uint32_t lmi_swap_cntl; 961 uint32_t mp_swap_cntl; 962 int i, j, k, r; 963 964 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 965 if (adev->uvd.harvest_config & (1 << k)) 966 continue; 967 /* disable DPG */ 968 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 969 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 970 } 971 972 /* disable byte swapping */ 973 lmi_swap_cntl = 0; 974 mp_swap_cntl = 0; 975 976 uvd_v7_0_mc_resume(adev); 977 978 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 979 if (adev->uvd.harvest_config & (1 << k)) 980 continue; 981 ring = &adev->uvd.inst[k].ring; 982 /* disable clock gating */ 983 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 984 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 985 986 /* disable interupt */ 987 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 988 ~UVD_MASTINT_EN__VCPU_EN_MASK); 989 990 /* stall UMC and register bus before resetting VCPU */ 991 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 992 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 993 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 994 mdelay(1); 995 996 /* put LMI, VCPU, RBC etc... into reset */ 997 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 998 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 999 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 1000 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 1001 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 1002 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 1003 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 1004 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 1005 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1006 mdelay(5); 1007 1008 /* initialize UVD memory controller */ 1009 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 1010 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1011 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1012 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1013 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1014 UVD_LMI_CTRL__REQ_MODE_MASK | 1015 0x00100000L); 1016 1017 #ifdef __BIG_ENDIAN 1018 /* swap (8 in 32) RB and IB */ 1019 lmi_swap_cntl = 0xa; 1020 mp_swap_cntl = 0; 1021 #endif 1022 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1023 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 1024 1025 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 1026 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 1027 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 1028 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1029 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1030 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1031 1032 /* take all subblocks out of reset, except VCPU */ 1033 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1034 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1035 mdelay(5); 1036 1037 /* enable VCPU clock */ 1038 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1039 UVD_VCPU_CNTL__CLK_EN_MASK); 1040 1041 /* enable UMC */ 1042 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1043 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1044 1045 /* boot up the VCPU */ 1046 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1047 mdelay(10); 1048 1049 for (i = 0; i < 10; ++i) { 1050 uint32_t status; 1051 1052 for (j = 0; j < 100; ++j) { 1053 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1054 if (status & 2) 1055 break; 1056 mdelay(10); 1057 } 1058 r = 0; 1059 if (status & 2) 1060 break; 1061 1062 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1063 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1064 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1065 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1066 mdelay(10); 1067 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1068 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1069 mdelay(10); 1070 r = -1; 1071 } 1072 1073 if (r) { 1074 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1075 return r; 1076 } 1077 /* enable master interrupt */ 1078 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1079 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1080 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1081 1082 /* clear the bit 4 of UVD_STATUS */ 1083 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1084 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1085 1086 /* force RBC into idle state */ 1087 rb_bufsz = order_base_2(ring->ring_size); 1088 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1089 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1090 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1091 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1092 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1093 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1095 1096 /* set the write pointer delay */ 1097 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1098 1099 /* set the wb address */ 1100 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1101 (upper_32_bits(ring->gpu_addr) >> 2)); 1102 1103 /* program the RB_BASE for ring buffer */ 1104 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1105 lower_32_bits(ring->gpu_addr)); 1106 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1107 upper_32_bits(ring->gpu_addr)); 1108 1109 /* Initialize the ring buffer's read and write pointers */ 1110 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1111 1112 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1113 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1114 lower_32_bits(ring->wptr)); 1115 1116 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1117 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1118 1119 ring = &adev->uvd.inst[k].ring_enc[0]; 1120 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1121 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1122 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1123 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1124 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1125 1126 ring = &adev->uvd.inst[k].ring_enc[1]; 1127 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1128 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1129 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1130 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1131 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1132 } 1133 return 0; 1134 } 1135 1136 /** 1137 * uvd_v7_0_stop - stop UVD block 1138 * 1139 * @adev: amdgpu_device pointer 1140 * 1141 * stop the UVD block 1142 */ 1143 static void uvd_v7_0_stop(struct amdgpu_device *adev) 1144 { 1145 uint8_t i = 0; 1146 1147 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1148 if (adev->uvd.harvest_config & (1 << i)) 1149 continue; 1150 /* force RBC into idle state */ 1151 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1152 1153 /* Stall UMC and register bus before resetting VCPU */ 1154 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1155 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1156 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1157 mdelay(1); 1158 1159 /* put VCPU into reset */ 1160 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1161 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1162 mdelay(5); 1163 1164 /* disable VCPU clock */ 1165 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1166 1167 /* Unstall UMC and register bus */ 1168 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1169 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1170 } 1171 } 1172 1173 /** 1174 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1175 * 1176 * @ring: amdgpu_ring pointer 1177 * @addr: address 1178 * @seq: sequence number 1179 * @flags: fence related flags 1180 * 1181 * Write a fence and a trap command to the ring. 1182 */ 1183 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1184 unsigned flags) 1185 { 1186 struct amdgpu_device *adev = ring->adev; 1187 1188 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1189 1190 amdgpu_ring_write(ring, 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1192 amdgpu_ring_write(ring, seq); 1193 amdgpu_ring_write(ring, 1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1195 amdgpu_ring_write(ring, addr & 0xffffffff); 1196 amdgpu_ring_write(ring, 1197 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1198 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1199 amdgpu_ring_write(ring, 1200 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1201 amdgpu_ring_write(ring, 0); 1202 1203 amdgpu_ring_write(ring, 1204 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1205 amdgpu_ring_write(ring, 0); 1206 amdgpu_ring_write(ring, 1207 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1208 amdgpu_ring_write(ring, 0); 1209 amdgpu_ring_write(ring, 1210 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1211 amdgpu_ring_write(ring, 2); 1212 } 1213 1214 /** 1215 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1216 * 1217 * @ring: amdgpu_ring pointer 1218 * @addr: address 1219 * @seq: sequence number 1220 * @flags: fence related flags 1221 * 1222 * Write enc a fence and a trap command to the ring. 1223 */ 1224 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1225 u64 seq, unsigned flags) 1226 { 1227 1228 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1229 1230 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1231 amdgpu_ring_write(ring, addr); 1232 amdgpu_ring_write(ring, upper_32_bits(addr)); 1233 amdgpu_ring_write(ring, seq); 1234 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1235 } 1236 1237 /** 1238 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1239 * 1240 * @ring: amdgpu_ring pointer 1241 */ 1242 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1243 { 1244 /* The firmware doesn't seem to like touching registers at this point. */ 1245 } 1246 1247 /** 1248 * uvd_v7_0_ring_test_ring - register write test 1249 * 1250 * @ring: amdgpu_ring pointer 1251 * 1252 * Test if we can successfully write to the context register 1253 */ 1254 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1255 { 1256 struct amdgpu_device *adev = ring->adev; 1257 uint32_t tmp = 0; 1258 unsigned i; 1259 int r; 1260 1261 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1262 r = amdgpu_ring_alloc(ring, 3); 1263 if (r) 1264 return r; 1265 1266 amdgpu_ring_write(ring, 1267 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1268 amdgpu_ring_write(ring, 0xDEADBEEF); 1269 amdgpu_ring_commit(ring); 1270 for (i = 0; i < adev->usec_timeout; i++) { 1271 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1272 if (tmp == 0xDEADBEEF) 1273 break; 1274 udelay(1); 1275 } 1276 1277 if (i >= adev->usec_timeout) 1278 r = -ETIMEDOUT; 1279 1280 return r; 1281 } 1282 1283 /** 1284 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1285 * 1286 * @p: the CS parser with the IBs 1287 * @job: which job this ib is in 1288 * @ib: which IB to patch 1289 * 1290 */ 1291 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1292 struct amdgpu_job *job, 1293 struct amdgpu_ib *ib) 1294 { 1295 struct amdgpu_ring *ring = amdgpu_job_ring(job); 1296 unsigned i; 1297 1298 /* No patching necessary for the first instance */ 1299 if (!ring->me) 1300 return 0; 1301 1302 for (i = 0; i < ib->length_dw; i += 2) { 1303 uint32_t reg = amdgpu_ib_get_value(ib, i); 1304 1305 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1306 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1307 1308 amdgpu_ib_set_value(ib, i, reg); 1309 } 1310 return 0; 1311 } 1312 1313 /** 1314 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1315 * 1316 * @ring: amdgpu_ring pointer 1317 * @job: job to retrieve vmid from 1318 * @ib: indirect buffer to execute 1319 * @flags: unused 1320 * 1321 * Write ring commands to execute the indirect buffer 1322 */ 1323 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1324 struct amdgpu_job *job, 1325 struct amdgpu_ib *ib, 1326 uint32_t flags) 1327 { 1328 struct amdgpu_device *adev = ring->adev; 1329 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1330 1331 amdgpu_ring_write(ring, 1332 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1333 amdgpu_ring_write(ring, vmid); 1334 1335 amdgpu_ring_write(ring, 1336 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1337 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1338 amdgpu_ring_write(ring, 1339 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1340 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1341 amdgpu_ring_write(ring, 1342 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1343 amdgpu_ring_write(ring, ib->length_dw); 1344 } 1345 1346 /** 1347 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1348 * 1349 * @ring: amdgpu_ring pointer 1350 * @job: job to retrive vmid from 1351 * @ib: indirect buffer to execute 1352 * @flags: unused 1353 * 1354 * Write enc ring commands to execute the indirect buffer 1355 */ 1356 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1357 struct amdgpu_job *job, 1358 struct amdgpu_ib *ib, 1359 uint32_t flags) 1360 { 1361 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1362 1363 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1364 amdgpu_ring_write(ring, vmid); 1365 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1366 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1367 amdgpu_ring_write(ring, ib->length_dw); 1368 } 1369 1370 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1371 uint32_t reg, uint32_t val) 1372 { 1373 struct amdgpu_device *adev = ring->adev; 1374 1375 amdgpu_ring_write(ring, 1376 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1377 amdgpu_ring_write(ring, reg << 2); 1378 amdgpu_ring_write(ring, 1379 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1380 amdgpu_ring_write(ring, val); 1381 amdgpu_ring_write(ring, 1382 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1383 amdgpu_ring_write(ring, 8); 1384 } 1385 1386 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1387 uint32_t val, uint32_t mask) 1388 { 1389 struct amdgpu_device *adev = ring->adev; 1390 1391 amdgpu_ring_write(ring, 1392 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1393 amdgpu_ring_write(ring, reg << 2); 1394 amdgpu_ring_write(ring, 1395 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1396 amdgpu_ring_write(ring, val); 1397 amdgpu_ring_write(ring, 1398 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1399 amdgpu_ring_write(ring, mask); 1400 amdgpu_ring_write(ring, 1401 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1402 amdgpu_ring_write(ring, 12); 1403 } 1404 1405 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1406 unsigned vmid, uint64_t pd_addr) 1407 { 1408 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1409 uint32_t data0, data1, mask; 1410 1411 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1412 1413 /* wait for reg writes */ 1414 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1415 data1 = lower_32_bits(pd_addr); 1416 mask = 0xffffffff; 1417 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1418 } 1419 1420 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1421 { 1422 struct amdgpu_device *adev = ring->adev; 1423 int i; 1424 1425 WARN_ON(ring->wptr % 2 || count % 2); 1426 1427 for (i = 0; i < count / 2; i++) { 1428 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1429 amdgpu_ring_write(ring, 0); 1430 } 1431 } 1432 1433 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1434 { 1435 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1436 } 1437 1438 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1439 uint32_t reg, uint32_t val, 1440 uint32_t mask) 1441 { 1442 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1443 amdgpu_ring_write(ring, reg << 2); 1444 amdgpu_ring_write(ring, mask); 1445 amdgpu_ring_write(ring, val); 1446 } 1447 1448 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1449 unsigned int vmid, uint64_t pd_addr) 1450 { 1451 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1452 1453 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1454 1455 /* wait for reg writes */ 1456 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1457 vmid * hub->ctx_addr_distance, 1458 lower_32_bits(pd_addr), 0xffffffff); 1459 } 1460 1461 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1462 uint32_t reg, uint32_t val) 1463 { 1464 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1465 amdgpu_ring_write(ring, reg << 2); 1466 amdgpu_ring_write(ring, val); 1467 } 1468 1469 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1470 struct amdgpu_irq_src *source, 1471 unsigned type, 1472 enum amdgpu_interrupt_state state) 1473 { 1474 // TODO 1475 return 0; 1476 } 1477 1478 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1479 struct amdgpu_irq_src *source, 1480 struct amdgpu_iv_entry *entry) 1481 { 1482 uint32_t ip_instance; 1483 1484 switch (entry->client_id) { 1485 case SOC15_IH_CLIENTID_UVD: 1486 ip_instance = 0; 1487 break; 1488 case SOC15_IH_CLIENTID_UVD1: 1489 ip_instance = 1; 1490 break; 1491 default: 1492 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1493 return 0; 1494 } 1495 1496 DRM_DEBUG("IH: UVD TRAP\n"); 1497 1498 switch (entry->src_id) { 1499 case 124: 1500 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1501 break; 1502 case 119: 1503 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1504 break; 1505 case 120: 1506 if (!amdgpu_sriov_vf(adev)) 1507 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1508 break; 1509 default: 1510 DRM_ERROR("Unhandled interrupt: %d %d\n", 1511 entry->src_id, entry->src_data[0]); 1512 break; 1513 } 1514 1515 return 0; 1516 } 1517 1518 static int uvd_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1519 enum amd_clockgating_state state) 1520 { 1521 /* needed for driver unload*/ 1522 return 0; 1523 } 1524 1525 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1526 .name = "uvd_v7_0", 1527 .early_init = uvd_v7_0_early_init, 1528 .sw_init = uvd_v7_0_sw_init, 1529 .sw_fini = uvd_v7_0_sw_fini, 1530 .hw_init = uvd_v7_0_hw_init, 1531 .hw_fini = uvd_v7_0_hw_fini, 1532 .prepare_suspend = uvd_v7_0_prepare_suspend, 1533 .suspend = uvd_v7_0_suspend, 1534 .resume = uvd_v7_0_resume, 1535 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1536 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1537 }; 1538 1539 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1540 .type = AMDGPU_RING_TYPE_UVD, 1541 .align_mask = 0xf, 1542 .support_64bit_ptrs = false, 1543 .no_user_fence = true, 1544 .get_rptr = uvd_v7_0_ring_get_rptr, 1545 .get_wptr = uvd_v7_0_ring_get_wptr, 1546 .set_wptr = uvd_v7_0_ring_set_wptr, 1547 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1548 .emit_frame_size = 1549 6 + /* hdp invalidate */ 1550 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1551 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1552 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1553 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1554 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1555 .emit_ib = uvd_v7_0_ring_emit_ib, 1556 .emit_fence = uvd_v7_0_ring_emit_fence, 1557 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1558 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1559 .test_ring = uvd_v7_0_ring_test_ring, 1560 .test_ib = amdgpu_uvd_ring_test_ib, 1561 .insert_nop = uvd_v7_0_ring_insert_nop, 1562 .pad_ib = amdgpu_ring_generic_pad_ib, 1563 .begin_use = amdgpu_uvd_ring_begin_use, 1564 .end_use = amdgpu_uvd_ring_end_use, 1565 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1566 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1567 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1568 }; 1569 1570 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1571 .type = AMDGPU_RING_TYPE_UVD_ENC, 1572 .align_mask = 0x3f, 1573 .nop = HEVC_ENC_CMD_NO_OP, 1574 .support_64bit_ptrs = false, 1575 .no_user_fence = true, 1576 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1577 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1578 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1579 .emit_frame_size = 1580 3 + 3 + /* hdp flush / invalidate */ 1581 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1582 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1583 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1584 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1585 1, /* uvd_v7_0_enc_ring_insert_end */ 1586 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1587 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1588 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1589 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1590 .test_ring = uvd_v7_0_enc_ring_test_ring, 1591 .test_ib = uvd_v7_0_enc_ring_test_ib, 1592 .insert_nop = amdgpu_ring_insert_nop, 1593 .insert_end = uvd_v7_0_enc_ring_insert_end, 1594 .pad_ib = amdgpu_ring_generic_pad_ib, 1595 .begin_use = amdgpu_uvd_ring_begin_use, 1596 .end_use = amdgpu_uvd_ring_end_use, 1597 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1598 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1599 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1600 }; 1601 1602 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1603 { 1604 int i; 1605 1606 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1607 if (adev->uvd.harvest_config & (1 << i)) 1608 continue; 1609 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1610 adev->uvd.inst[i].ring.me = i; 1611 drm_info(adev_to_drm(adev), "UVD(%d) is enabled in VM mode\n", i); 1612 } 1613 } 1614 1615 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1616 { 1617 int i, j; 1618 1619 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1620 if (adev->uvd.harvest_config & (1 << j)) 1621 continue; 1622 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1623 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1624 adev->uvd.inst[j].ring_enc[i].me = j; 1625 } 1626 1627 drm_info(adev_to_drm(adev), "UVD(%d) ENC is enabled in VM mode\n", j); 1628 } 1629 } 1630 1631 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1632 .set = uvd_v7_0_set_interrupt_state, 1633 .process = uvd_v7_0_process_interrupt, 1634 }; 1635 1636 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1637 { 1638 int i; 1639 1640 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1641 if (adev->uvd.harvest_config & (1 << i)) 1642 continue; 1643 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1644 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1645 } 1646 } 1647 1648 const struct amdgpu_ip_block_version uvd_v7_0_ip_block = { 1649 .type = AMD_IP_BLOCK_TYPE_UVD, 1650 .major = 7, 1651 .minor = 0, 1652 .rev = 0, 1653 .funcs = &uvd_v7_0_ip_funcs, 1654 }; 1655