1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "smu/smu_7_1_3_d.h" 35 #include "smu/smu_7_1_3_sh_mask.h" 36 #include "bif/bif_5_1_d.h" 37 #include "gmc/gmc_8_1_d.h" 38 #include "vi.h" 39 #include "ivsrcid/ivsrcid_vislands30.h" 40 41 /* Polaris10/11/12 firmware version */ 42 #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8)) 43 44 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 45 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev); 46 47 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 48 static int uvd_v6_0_start(struct amdgpu_device *adev); 49 static void uvd_v6_0_stop(struct amdgpu_device *adev); 50 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 51 static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 52 enum amd_clockgating_state state); 53 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 54 bool enable); 55 56 /** 57 * uvd_v6_0_enc_support - get encode support status 58 * 59 * @adev: amdgpu_device pointer 60 * 61 * Returns the current hardware encode support status 62 */ 63 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev) 64 { 65 return ((adev->asic_type >= CHIP_POLARIS10) && 66 (adev->asic_type <= CHIP_VEGAM) && 67 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); 68 } 69 70 /** 71 * uvd_v6_0_ring_get_rptr - get read pointer 72 * 73 * @ring: amdgpu_ring pointer 74 * 75 * Returns the current hardware read pointer 76 */ 77 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 78 { 79 struct amdgpu_device *adev = ring->adev; 80 81 return RREG32(mmUVD_RBC_RB_RPTR); 82 } 83 84 /** 85 * uvd_v6_0_enc_ring_get_rptr - get enc read pointer 86 * 87 * @ring: amdgpu_ring pointer 88 * 89 * Returns the current hardware enc read pointer 90 */ 91 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 92 { 93 struct amdgpu_device *adev = ring->adev; 94 95 if (ring == &adev->uvd.inst->ring_enc[0]) 96 return RREG32(mmUVD_RB_RPTR); 97 else 98 return RREG32(mmUVD_RB_RPTR2); 99 } 100 /** 101 * uvd_v6_0_ring_get_wptr - get write pointer 102 * 103 * @ring: amdgpu_ring pointer 104 * 105 * Returns the current hardware write pointer 106 */ 107 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 108 { 109 struct amdgpu_device *adev = ring->adev; 110 111 return RREG32(mmUVD_RBC_RB_WPTR); 112 } 113 114 /** 115 * uvd_v6_0_enc_ring_get_wptr - get enc write pointer 116 * 117 * @ring: amdgpu_ring pointer 118 * 119 * Returns the current hardware enc write pointer 120 */ 121 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 122 { 123 struct amdgpu_device *adev = ring->adev; 124 125 if (ring == &adev->uvd.inst->ring_enc[0]) 126 return RREG32(mmUVD_RB_WPTR); 127 else 128 return RREG32(mmUVD_RB_WPTR2); 129 } 130 131 /** 132 * uvd_v6_0_ring_set_wptr - set write pointer 133 * 134 * @ring: amdgpu_ring pointer 135 * 136 * Commits the write pointer to the hardware 137 */ 138 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 139 { 140 struct amdgpu_device *adev = ring->adev; 141 142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 143 } 144 145 /** 146 * uvd_v6_0_enc_ring_set_wptr - set enc write pointer 147 * 148 * @ring: amdgpu_ring pointer 149 * 150 * Commits the enc write pointer to the hardware 151 */ 152 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 153 { 154 struct amdgpu_device *adev = ring->adev; 155 156 if (ring == &adev->uvd.inst->ring_enc[0]) 157 WREG32(mmUVD_RB_WPTR, 158 lower_32_bits(ring->wptr)); 159 else 160 WREG32(mmUVD_RB_WPTR2, 161 lower_32_bits(ring->wptr)); 162 } 163 164 /** 165 * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working 166 * 167 * @ring: the engine to test on 168 * 169 */ 170 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) 171 { 172 struct amdgpu_device *adev = ring->adev; 173 uint32_t rptr; 174 unsigned i; 175 int r; 176 177 r = amdgpu_ring_alloc(ring, 16); 178 if (r) 179 return r; 180 181 rptr = amdgpu_ring_get_rptr(ring); 182 183 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 184 amdgpu_ring_commit(ring); 185 186 for (i = 0; i < adev->usec_timeout; i++) { 187 if (amdgpu_ring_get_rptr(ring) != rptr) 188 break; 189 udelay(1); 190 } 191 192 if (i >= adev->usec_timeout) 193 r = -ETIMEDOUT; 194 195 return r; 196 } 197 198 /** 199 * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg 200 * 201 * @ring: ring we should submit the msg to 202 * @handle: session handle to use 203 * @bo: amdgpu object for which we query the offset 204 * @fence: optional fence to return 205 * 206 * Open up a stream for HW test 207 */ 208 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 209 struct amdgpu_bo *bo, 210 struct dma_fence **fence) 211 { 212 const unsigned ib_size_dw = 16; 213 struct amdgpu_job *job; 214 struct amdgpu_ib *ib; 215 struct dma_fence *f = NULL; 216 uint64_t addr; 217 int i, r; 218 219 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 220 AMDGPU_IB_POOL_DIRECT, 221 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 222 &job); 223 if (r) 224 return r; 225 226 ib = &job->ibs[0]; 227 addr = amdgpu_bo_gpu_offset(bo); 228 229 ib->length_dw = 0; 230 ib->ptr[ib->length_dw++] = 0x00000018; 231 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 232 ib->ptr[ib->length_dw++] = handle; 233 ib->ptr[ib->length_dw++] = 0x00010000; 234 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 235 ib->ptr[ib->length_dw++] = addr; 236 237 ib->ptr[ib->length_dw++] = 0x00000014; 238 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 239 ib->ptr[ib->length_dw++] = 0x0000001c; 240 ib->ptr[ib->length_dw++] = 0x00000001; 241 ib->ptr[ib->length_dw++] = 0x00000000; 242 243 ib->ptr[ib->length_dw++] = 0x00000008; 244 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 245 246 for (i = ib->length_dw; i < ib_size_dw; ++i) 247 ib->ptr[i] = 0x0; 248 249 r = amdgpu_job_submit_direct(job, ring, &f); 250 if (r) 251 goto err; 252 253 if (fence) 254 *fence = dma_fence_get(f); 255 dma_fence_put(f); 256 return 0; 257 258 err: 259 amdgpu_job_free(job); 260 return r; 261 } 262 263 /** 264 * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 265 * 266 * @ring: ring we should submit the msg to 267 * @handle: session handle to use 268 * @bo: amdgpu object for which we query the offset 269 * @fence: optional fence to return 270 * 271 * Close up a stream for HW test or if userspace failed to do so 272 */ 273 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, 274 uint32_t handle, 275 struct amdgpu_bo *bo, 276 struct dma_fence **fence) 277 { 278 const unsigned ib_size_dw = 16; 279 struct amdgpu_job *job; 280 struct amdgpu_ib *ib; 281 struct dma_fence *f = NULL; 282 uint64_t addr; 283 int i, r; 284 285 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4, 286 AMDGPU_IB_POOL_DIRECT, 287 AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST, 288 &job); 289 if (r) 290 return r; 291 292 ib = &job->ibs[0]; 293 addr = amdgpu_bo_gpu_offset(bo); 294 295 ib->length_dw = 0; 296 ib->ptr[ib->length_dw++] = 0x00000018; 297 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 298 ib->ptr[ib->length_dw++] = handle; 299 ib->ptr[ib->length_dw++] = 0x00010000; 300 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 301 ib->ptr[ib->length_dw++] = addr; 302 303 ib->ptr[ib->length_dw++] = 0x00000014; 304 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 305 ib->ptr[ib->length_dw++] = 0x0000001c; 306 ib->ptr[ib->length_dw++] = 0x00000001; 307 ib->ptr[ib->length_dw++] = 0x00000000; 308 309 ib->ptr[ib->length_dw++] = 0x00000008; 310 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 311 312 for (i = ib->length_dw; i < ib_size_dw; ++i) 313 ib->ptr[i] = 0x0; 314 315 r = amdgpu_job_submit_direct(job, ring, &f); 316 if (r) 317 goto err; 318 319 if (fence) 320 *fence = dma_fence_get(f); 321 dma_fence_put(f); 322 return 0; 323 324 err: 325 amdgpu_job_free(job); 326 return r; 327 } 328 329 /** 330 * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working 331 * 332 * @ring: the engine to test on 333 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 334 * 335 */ 336 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 337 { 338 struct dma_fence *fence = NULL; 339 struct amdgpu_bo *bo = ring->adev->uvd.ib_bo; 340 long r; 341 342 r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL); 343 if (r) 344 goto error; 345 346 r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence); 347 if (r) 348 goto error; 349 350 r = dma_fence_wait_timeout(fence, false, timeout); 351 if (r == 0) 352 r = -ETIMEDOUT; 353 else if (r > 0) 354 r = 0; 355 356 error: 357 dma_fence_put(fence); 358 return r; 359 } 360 361 static int uvd_v6_0_early_init(struct amdgpu_ip_block *ip_block) 362 { 363 struct amdgpu_device *adev = ip_block->adev; 364 adev->uvd.num_uvd_inst = 1; 365 366 if (!(adev->flags & AMD_IS_APU) && 367 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) 368 return -ENOENT; 369 370 uvd_v6_0_set_ring_funcs(adev); 371 372 if (uvd_v6_0_enc_support(adev)) { 373 adev->uvd.num_enc_rings = 2; 374 uvd_v6_0_set_enc_ring_funcs(adev); 375 } 376 377 uvd_v6_0_set_irq_funcs(adev); 378 379 return 0; 380 } 381 382 static int uvd_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 383 { 384 struct amdgpu_ring *ring; 385 int i, r; 386 struct amdgpu_device *adev = ip_block->adev; 387 388 /* UVD TRAP */ 389 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 390 if (r) 391 return r; 392 393 /* UVD ENC TRAP */ 394 if (uvd_v6_0_enc_support(adev)) { 395 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 396 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq); 397 if (r) 398 return r; 399 } 400 } 401 402 r = amdgpu_uvd_sw_init(adev); 403 if (r) 404 return r; 405 406 if (!uvd_v6_0_enc_support(adev)) { 407 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 408 adev->uvd.inst->ring_enc[i].funcs = NULL; 409 410 adev->uvd.inst->irq.num_types = 1; 411 adev->uvd.num_enc_rings = 0; 412 413 drm_info(adev_to_drm(adev), "UVD ENC is disabled\n"); 414 } 415 416 ring = &adev->uvd.inst->ring; 417 sprintf(ring->name, "uvd"); 418 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0, 419 AMDGPU_RING_PRIO_DEFAULT, NULL); 420 if (r) 421 return r; 422 423 r = amdgpu_uvd_resume(adev); 424 if (r) 425 return r; 426 427 if (uvd_v6_0_enc_support(adev)) { 428 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 429 ring = &adev->uvd.inst->ring_enc[i]; 430 sprintf(ring->name, "uvd_enc%d", i); 431 r = amdgpu_ring_init(adev, ring, 512, 432 &adev->uvd.inst->irq, 0, 433 AMDGPU_RING_PRIO_DEFAULT, NULL); 434 if (r) 435 return r; 436 } 437 } 438 439 return r; 440 } 441 442 static int uvd_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 443 { 444 int i, r; 445 struct amdgpu_device *adev = ip_block->adev; 446 447 r = amdgpu_uvd_suspend(adev); 448 if (r) 449 return r; 450 451 if (uvd_v6_0_enc_support(adev)) { 452 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 453 amdgpu_ring_fini(&adev->uvd.inst->ring_enc[i]); 454 } 455 456 return amdgpu_uvd_sw_fini(adev); 457 } 458 459 /** 460 * uvd_v6_0_hw_init - start and test UVD block 461 * 462 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 463 * 464 * Initialize the hardware, boot up the VCPU and do some testing 465 */ 466 static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 467 { 468 struct amdgpu_device *adev = ip_block->adev; 469 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 470 uint32_t tmp; 471 int i, r; 472 473 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 474 uvd_v6_0_set_clockgating_state(ip_block, AMD_CG_STATE_UNGATE); 475 uvd_v6_0_enable_mgcg(adev, true); 476 477 r = amdgpu_ring_test_helper(ring); 478 if (r) 479 goto done; 480 481 r = amdgpu_ring_alloc(ring, 10); 482 if (r) { 483 drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); 484 goto done; 485 } 486 487 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 488 amdgpu_ring_write(ring, tmp); 489 amdgpu_ring_write(ring, 0xFFFFF); 490 491 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 492 amdgpu_ring_write(ring, tmp); 493 amdgpu_ring_write(ring, 0xFFFFF); 494 495 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 496 amdgpu_ring_write(ring, tmp); 497 amdgpu_ring_write(ring, 0xFFFFF); 498 499 /* Clear timeout status bits */ 500 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 501 amdgpu_ring_write(ring, 0x8); 502 503 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 504 amdgpu_ring_write(ring, 3); 505 506 amdgpu_ring_commit(ring); 507 508 if (uvd_v6_0_enc_support(adev)) { 509 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 510 ring = &adev->uvd.inst->ring_enc[i]; 511 r = amdgpu_ring_test_helper(ring); 512 if (r) 513 goto done; 514 } 515 } 516 517 done: 518 if (!r) { 519 if (uvd_v6_0_enc_support(adev)) 520 drm_info(adev_to_drm(adev), "UVD and UVD ENC initialized successfully.\n"); 521 else 522 drm_info(adev_to_drm(adev), "UVD initialized successfully.\n"); 523 } 524 525 return r; 526 } 527 528 /** 529 * uvd_v6_0_hw_fini - stop the hardware block 530 * 531 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. 532 * 533 * Stop the UVD block, mark ring as not ready any more 534 */ 535 static int uvd_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 536 { 537 struct amdgpu_device *adev = ip_block->adev; 538 539 cancel_delayed_work_sync(&adev->uvd.idle_work); 540 541 if (RREG32(mmUVD_STATUS) != 0) 542 uvd_v6_0_stop(adev); 543 544 return 0; 545 } 546 547 static int uvd_v6_0_prepare_suspend(struct amdgpu_ip_block *ip_block) 548 { 549 struct amdgpu_device *adev = ip_block->adev; 550 551 return amdgpu_uvd_prepare_suspend(adev); 552 } 553 554 static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block) 555 { 556 int r; 557 struct amdgpu_device *adev = ip_block->adev; 558 559 /* 560 * Proper cleanups before halting the HW engine: 561 * - cancel the delayed idle work 562 * - enable powergating 563 * - enable clockgating 564 * - disable dpm 565 * 566 * TODO: to align with the VCN implementation, move the 567 * jobs for clockgating/powergating/dpm setting to 568 * ->set_powergating_state(). 569 */ 570 cancel_delayed_work_sync(&adev->uvd.idle_work); 571 572 if (adev->pm.dpm_enabled) { 573 amdgpu_dpm_enable_uvd(adev, false); 574 } else { 575 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 576 /* shutdown the UVD block */ 577 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 578 AMD_PG_STATE_GATE); 579 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 580 AMD_CG_STATE_GATE); 581 } 582 583 r = uvd_v6_0_hw_fini(ip_block); 584 if (r) 585 return r; 586 587 return amdgpu_uvd_suspend(adev); 588 } 589 590 static int uvd_v6_0_resume(struct amdgpu_ip_block *ip_block) 591 { 592 int r; 593 594 r = amdgpu_uvd_resume(ip_block->adev); 595 if (r) 596 return r; 597 598 return uvd_v6_0_hw_init(ip_block); 599 } 600 601 /** 602 * uvd_v6_0_mc_resume - memory controller programming 603 * 604 * @adev: amdgpu_device pointer 605 * 606 * Let the UVD memory controller know it's offsets 607 */ 608 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 609 { 610 uint64_t offset; 611 uint32_t size; 612 613 /* program memory controller bits 0-27 */ 614 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 615 lower_32_bits(adev->uvd.inst->gpu_addr)); 616 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 617 upper_32_bits(adev->uvd.inst->gpu_addr)); 618 619 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 620 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 621 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 622 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 623 624 offset += size; 625 size = AMDGPU_UVD_HEAP_SIZE; 626 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 627 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 628 629 offset += size; 630 size = AMDGPU_UVD_STACK_SIZE + 631 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 632 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 633 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 634 635 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 636 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 637 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 638 639 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 640 } 641 642 #if 0 643 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 644 bool enable) 645 { 646 u32 data, data1; 647 648 data = RREG32(mmUVD_CGC_GATE); 649 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 650 if (enable) { 651 data |= UVD_CGC_GATE__SYS_MASK | 652 UVD_CGC_GATE__UDEC_MASK | 653 UVD_CGC_GATE__MPEG2_MASK | 654 UVD_CGC_GATE__RBC_MASK | 655 UVD_CGC_GATE__LMI_MC_MASK | 656 UVD_CGC_GATE__IDCT_MASK | 657 UVD_CGC_GATE__MPRD_MASK | 658 UVD_CGC_GATE__MPC_MASK | 659 UVD_CGC_GATE__LBSI_MASK | 660 UVD_CGC_GATE__LRBBM_MASK | 661 UVD_CGC_GATE__UDEC_RE_MASK | 662 UVD_CGC_GATE__UDEC_CM_MASK | 663 UVD_CGC_GATE__UDEC_IT_MASK | 664 UVD_CGC_GATE__UDEC_DB_MASK | 665 UVD_CGC_GATE__UDEC_MP_MASK | 666 UVD_CGC_GATE__WCB_MASK | 667 UVD_CGC_GATE__VCPU_MASK | 668 UVD_CGC_GATE__SCPU_MASK; 669 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 670 UVD_SUVD_CGC_GATE__SIT_MASK | 671 UVD_SUVD_CGC_GATE__SMP_MASK | 672 UVD_SUVD_CGC_GATE__SCM_MASK | 673 UVD_SUVD_CGC_GATE__SDB_MASK | 674 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 675 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 676 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 677 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 678 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 679 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 680 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 681 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 682 } else { 683 data &= ~(UVD_CGC_GATE__SYS_MASK | 684 UVD_CGC_GATE__UDEC_MASK | 685 UVD_CGC_GATE__MPEG2_MASK | 686 UVD_CGC_GATE__RBC_MASK | 687 UVD_CGC_GATE__LMI_MC_MASK | 688 UVD_CGC_GATE__LMI_UMC_MASK | 689 UVD_CGC_GATE__IDCT_MASK | 690 UVD_CGC_GATE__MPRD_MASK | 691 UVD_CGC_GATE__MPC_MASK | 692 UVD_CGC_GATE__LBSI_MASK | 693 UVD_CGC_GATE__LRBBM_MASK | 694 UVD_CGC_GATE__UDEC_RE_MASK | 695 UVD_CGC_GATE__UDEC_CM_MASK | 696 UVD_CGC_GATE__UDEC_IT_MASK | 697 UVD_CGC_GATE__UDEC_DB_MASK | 698 UVD_CGC_GATE__UDEC_MP_MASK | 699 UVD_CGC_GATE__WCB_MASK | 700 UVD_CGC_GATE__VCPU_MASK | 701 UVD_CGC_GATE__SCPU_MASK); 702 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 703 UVD_SUVD_CGC_GATE__SIT_MASK | 704 UVD_SUVD_CGC_GATE__SMP_MASK | 705 UVD_SUVD_CGC_GATE__SCM_MASK | 706 UVD_SUVD_CGC_GATE__SDB_MASK | 707 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 708 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 709 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 710 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 711 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 712 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 713 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 714 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 715 } 716 WREG32(mmUVD_CGC_GATE, data); 717 WREG32(mmUVD_SUVD_CGC_GATE, data1); 718 } 719 #endif 720 721 /** 722 * uvd_v6_0_start - start UVD block 723 * 724 * @adev: amdgpu_device pointer 725 * 726 * Setup and start the UVD block 727 */ 728 static int uvd_v6_0_start(struct amdgpu_device *adev) 729 { 730 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 731 uint32_t rb_bufsz, tmp; 732 uint32_t lmi_swap_cntl; 733 uint32_t mp_swap_cntl; 734 int i, j, r; 735 736 /* disable DPG */ 737 WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 738 739 /* disable byte swapping */ 740 lmi_swap_cntl = 0; 741 mp_swap_cntl = 0; 742 743 uvd_v6_0_mc_resume(adev); 744 745 /* disable interupt */ 746 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); 747 748 /* stall UMC and register bus before resetting VCPU */ 749 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); 750 mdelay(1); 751 752 /* put LMI, VCPU, RBC etc... into reset */ 753 WREG32(mmUVD_SOFT_RESET, 754 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 755 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 756 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 757 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 758 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 759 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 760 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 761 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 762 mdelay(5); 763 764 /* take UVD block out of reset */ 765 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); 766 mdelay(5); 767 768 /* initialize UVD memory controller */ 769 WREG32(mmUVD_LMI_CTRL, 770 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 771 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 772 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 773 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 774 UVD_LMI_CTRL__REQ_MODE_MASK | 775 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK); 776 777 #ifdef __BIG_ENDIAN 778 /* swap (8 in 32) RB and IB */ 779 lmi_swap_cntl = 0xa; 780 mp_swap_cntl = 0; 781 #endif 782 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 783 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 784 785 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 786 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 787 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 788 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 789 WREG32(mmUVD_MPC_SET_ALU, 0); 790 WREG32(mmUVD_MPC_SET_MUX, 0x88); 791 792 /* take all subblocks out of reset, except VCPU */ 793 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 794 mdelay(5); 795 796 /* enable VCPU clock */ 797 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 798 799 /* enable UMC */ 800 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); 801 802 /* boot up the VCPU */ 803 WREG32(mmUVD_SOFT_RESET, 0); 804 mdelay(10); 805 806 for (i = 0; i < 10; ++i) { 807 uint32_t status; 808 809 for (j = 0; j < 100; ++j) { 810 status = RREG32(mmUVD_STATUS); 811 if (status & 2) 812 break; 813 mdelay(10); 814 } 815 r = 0; 816 if (status & 2) 817 break; 818 819 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 820 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); 821 mdelay(10); 822 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); 823 mdelay(10); 824 r = -1; 825 } 826 827 if (r) { 828 DRM_ERROR("UVD not responding, giving up!!!\n"); 829 return r; 830 } 831 /* enable master interrupt */ 832 WREG32_P(mmUVD_MASTINT_EN, 833 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 834 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 835 836 /* clear the bit 4 of UVD_STATUS */ 837 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 838 839 /* force RBC into idle state */ 840 rb_bufsz = order_base_2(ring->ring_size); 841 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 842 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 843 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 844 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 845 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 846 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 847 WREG32(mmUVD_RBC_RB_CNTL, tmp); 848 849 /* set the write pointer delay */ 850 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 851 852 /* set the wb address */ 853 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 854 855 /* program the RB_BASE for ring buffer */ 856 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 857 lower_32_bits(ring->gpu_addr)); 858 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 859 upper_32_bits(ring->gpu_addr)); 860 861 /* Initialize the ring buffer's read and write pointers */ 862 WREG32(mmUVD_RBC_RB_RPTR, 0); 863 864 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 865 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 866 867 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); 868 869 if (uvd_v6_0_enc_support(adev)) { 870 ring = &adev->uvd.inst->ring_enc[0]; 871 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 872 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 873 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); 874 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 875 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); 876 877 ring = &adev->uvd.inst->ring_enc[1]; 878 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 879 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 880 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr); 881 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 882 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4); 883 } 884 885 return 0; 886 } 887 888 /** 889 * uvd_v6_0_stop - stop UVD block 890 * 891 * @adev: amdgpu_device pointer 892 * 893 * stop the UVD block 894 */ 895 static void uvd_v6_0_stop(struct amdgpu_device *adev) 896 { 897 /* force RBC into idle state */ 898 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 899 900 /* Stall UMC and register bus before resetting VCPU */ 901 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 902 mdelay(1); 903 904 /* put VCPU into reset */ 905 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 906 mdelay(5); 907 908 /* disable VCPU clock */ 909 WREG32(mmUVD_VCPU_CNTL, 0x0); 910 911 /* Unstall UMC and register bus */ 912 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 913 914 WREG32(mmUVD_STATUS, 0); 915 } 916 917 /** 918 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 919 * 920 * @ring: amdgpu_ring pointer 921 * @addr: address 922 * @seq: sequence number 923 * @flags: fence related flags 924 * 925 * Write a fence and a trap command to the ring. 926 */ 927 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 928 unsigned flags) 929 { 930 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 931 932 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 933 amdgpu_ring_write(ring, seq); 934 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 935 amdgpu_ring_write(ring, addr & 0xffffffff); 936 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 937 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 938 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 939 amdgpu_ring_write(ring, 0); 940 941 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 942 amdgpu_ring_write(ring, 0); 943 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 944 amdgpu_ring_write(ring, 0); 945 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 946 amdgpu_ring_write(ring, 2); 947 } 948 949 /** 950 * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command 951 * 952 * @ring: amdgpu_ring pointer 953 * @addr: address 954 * @seq: sequence number 955 * @flags: fence related flags 956 * 957 * Write enc a fence and a trap command to the ring. 958 */ 959 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 960 u64 seq, unsigned flags) 961 { 962 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 963 964 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 965 amdgpu_ring_write(ring, addr); 966 amdgpu_ring_write(ring, upper_32_bits(addr)); 967 amdgpu_ring_write(ring, seq); 968 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 969 } 970 971 /** 972 * uvd_v6_0_ring_emit_hdp_flush - skip HDP flushing 973 * 974 * @ring: amdgpu_ring pointer 975 */ 976 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 977 { 978 /* The firmware doesn't seem to like touching registers at this point. */ 979 } 980 981 /** 982 * uvd_v6_0_ring_test_ring - register write test 983 * 984 * @ring: amdgpu_ring pointer 985 * 986 * Test if we can successfully write to the context register 987 */ 988 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 989 { 990 struct amdgpu_device *adev = ring->adev; 991 uint32_t tmp = 0; 992 unsigned i; 993 int r; 994 995 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 996 r = amdgpu_ring_alloc(ring, 3); 997 if (r) 998 return r; 999 1000 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 1001 amdgpu_ring_write(ring, 0xDEADBEEF); 1002 amdgpu_ring_commit(ring); 1003 for (i = 0; i < adev->usec_timeout; i++) { 1004 tmp = RREG32(mmUVD_CONTEXT_ID); 1005 if (tmp == 0xDEADBEEF) 1006 break; 1007 udelay(1); 1008 } 1009 1010 if (i >= adev->usec_timeout) 1011 r = -ETIMEDOUT; 1012 1013 return r; 1014 } 1015 1016 /** 1017 * uvd_v6_0_ring_emit_ib - execute indirect buffer 1018 * 1019 * @ring: amdgpu_ring pointer 1020 * @job: job to retrieve vmid from 1021 * @ib: indirect buffer to execute 1022 * @flags: unused 1023 * 1024 * Write ring commands to execute the indirect buffer 1025 */ 1026 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1027 struct amdgpu_job *job, 1028 struct amdgpu_ib *ib, 1029 uint32_t flags) 1030 { 1031 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1032 1033 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); 1034 amdgpu_ring_write(ring, vmid); 1035 1036 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 1037 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1038 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 1039 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1040 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 1041 amdgpu_ring_write(ring, ib->length_dw); 1042 } 1043 1044 /** 1045 * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer 1046 * 1047 * @ring: amdgpu_ring pointer 1048 * @job: job to retrive vmid from 1049 * @ib: indirect buffer to execute 1050 * @flags: unused 1051 * 1052 * Write enc ring commands to execute the indirect buffer 1053 */ 1054 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1055 struct amdgpu_job *job, 1056 struct amdgpu_ib *ib, 1057 uint32_t flags) 1058 { 1059 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1060 1061 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1062 amdgpu_ring_write(ring, vmid); 1063 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1064 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1065 amdgpu_ring_write(ring, ib->length_dw); 1066 } 1067 1068 static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 1069 uint32_t reg, uint32_t val) 1070 { 1071 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1072 amdgpu_ring_write(ring, reg << 2); 1073 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1074 amdgpu_ring_write(ring, val); 1075 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1076 amdgpu_ring_write(ring, 0x8); 1077 } 1078 1079 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1080 unsigned vmid, uint64_t pd_addr) 1081 { 1082 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1083 1084 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1085 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 1086 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1087 amdgpu_ring_write(ring, 0); 1088 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1089 amdgpu_ring_write(ring, 1 << vmid); /* mask */ 1090 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1091 amdgpu_ring_write(ring, 0xC); 1092 } 1093 1094 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1095 { 1096 uint32_t seq = ring->fence_drv.sync_seq; 1097 uint64_t addr = ring->fence_drv.gpu_addr; 1098 1099 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 1100 amdgpu_ring_write(ring, lower_32_bits(addr)); 1101 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 1102 amdgpu_ring_write(ring, upper_32_bits(addr)); 1103 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0)); 1104 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1105 amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0)); 1106 amdgpu_ring_write(ring, seq); 1107 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 1108 amdgpu_ring_write(ring, 0xE); 1109 } 1110 1111 static void uvd_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1112 { 1113 int i; 1114 1115 WARN_ON(ring->wptr % 2 || count % 2); 1116 1117 for (i = 0; i < count / 2; i++) { 1118 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 1119 amdgpu_ring_write(ring, 0); 1120 } 1121 } 1122 1123 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1124 { 1125 uint32_t seq = ring->fence_drv.sync_seq; 1126 uint64_t addr = ring->fence_drv.gpu_addr; 1127 1128 amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE); 1129 amdgpu_ring_write(ring, lower_32_bits(addr)); 1130 amdgpu_ring_write(ring, upper_32_bits(addr)); 1131 amdgpu_ring_write(ring, seq); 1132 } 1133 1134 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1135 { 1136 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1137 } 1138 1139 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1140 unsigned int vmid, uint64_t pd_addr) 1141 { 1142 amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB); 1143 amdgpu_ring_write(ring, vmid); 1144 amdgpu_ring_write(ring, pd_addr >> 12); 1145 1146 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); 1147 amdgpu_ring_write(ring, vmid); 1148 } 1149 1150 static bool uvd_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 1151 { 1152 struct amdgpu_device *adev = ip_block->adev; 1153 1154 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1155 } 1156 1157 static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1158 { 1159 unsigned i; 1160 struct amdgpu_device *adev = ip_block->adev; 1161 1162 for (i = 0; i < adev->usec_timeout; i++) { 1163 if (uvd_v6_0_is_idle(ip_block)) 1164 return 0; 1165 } 1166 return -ETIMEDOUT; 1167 } 1168 1169 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1170 1171 static int uvd_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 1172 { 1173 struct amdgpu_device *adev = ip_block->adev; 1174 u32 srbm_soft_reset; 1175 1176 if (!adev->uvd.inst->srbm_soft_reset) 1177 return 0; 1178 srbm_soft_reset = adev->uvd.inst->srbm_soft_reset; 1179 1180 if (srbm_soft_reset) { 1181 u32 tmp; 1182 1183 tmp = RREG32(mmSRBM_SOFT_RESET); 1184 tmp |= srbm_soft_reset; 1185 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1186 WREG32(mmSRBM_SOFT_RESET, tmp); 1187 tmp = RREG32(mmSRBM_SOFT_RESET); 1188 1189 udelay(50); 1190 1191 tmp &= ~srbm_soft_reset; 1192 WREG32(mmSRBM_SOFT_RESET, tmp); 1193 tmp = RREG32(mmSRBM_SOFT_RESET); 1194 1195 /* Wait a little for things to settle down */ 1196 udelay(50); 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 1203 struct amdgpu_irq_src *source, 1204 unsigned type, 1205 enum amdgpu_interrupt_state state) 1206 { 1207 // TODO 1208 return 0; 1209 } 1210 1211 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 1212 struct amdgpu_irq_src *source, 1213 struct amdgpu_iv_entry *entry) 1214 { 1215 bool int_handled = true; 1216 DRM_DEBUG("IH: UVD TRAP\n"); 1217 1218 switch (entry->src_id) { 1219 case 124: 1220 amdgpu_fence_process(&adev->uvd.inst->ring); 1221 break; 1222 case 119: 1223 if (likely(uvd_v6_0_enc_support(adev))) 1224 amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); 1225 else 1226 int_handled = false; 1227 break; 1228 case 120: 1229 if (likely(uvd_v6_0_enc_support(adev))) 1230 amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]); 1231 else 1232 int_handled = false; 1233 break; 1234 } 1235 1236 if (!int_handled) 1237 DRM_ERROR("Unhandled interrupt: %d %d\n", 1238 entry->src_id, entry->src_data[0]); 1239 1240 return 0; 1241 } 1242 1243 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 1244 { 1245 uint32_t data1, data3; 1246 1247 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1248 data3 = RREG32(mmUVD_CGC_GATE); 1249 1250 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 1251 UVD_SUVD_CGC_GATE__SIT_MASK | 1252 UVD_SUVD_CGC_GATE__SMP_MASK | 1253 UVD_SUVD_CGC_GATE__SCM_MASK | 1254 UVD_SUVD_CGC_GATE__SDB_MASK | 1255 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 1256 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 1257 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 1258 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 1259 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 1260 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 1261 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 1262 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 1263 1264 if (enable) { 1265 data3 |= (UVD_CGC_GATE__SYS_MASK | 1266 UVD_CGC_GATE__UDEC_MASK | 1267 UVD_CGC_GATE__MPEG2_MASK | 1268 UVD_CGC_GATE__RBC_MASK | 1269 UVD_CGC_GATE__LMI_MC_MASK | 1270 UVD_CGC_GATE__LMI_UMC_MASK | 1271 UVD_CGC_GATE__IDCT_MASK | 1272 UVD_CGC_GATE__MPRD_MASK | 1273 UVD_CGC_GATE__MPC_MASK | 1274 UVD_CGC_GATE__LBSI_MASK | 1275 UVD_CGC_GATE__LRBBM_MASK | 1276 UVD_CGC_GATE__UDEC_RE_MASK | 1277 UVD_CGC_GATE__UDEC_CM_MASK | 1278 UVD_CGC_GATE__UDEC_IT_MASK | 1279 UVD_CGC_GATE__UDEC_DB_MASK | 1280 UVD_CGC_GATE__UDEC_MP_MASK | 1281 UVD_CGC_GATE__WCB_MASK | 1282 UVD_CGC_GATE__JPEG_MASK | 1283 UVD_CGC_GATE__SCPU_MASK | 1284 UVD_CGC_GATE__JPEG2_MASK); 1285 /* only in pg enabled, we can gate clock to vcpu*/ 1286 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1287 data3 |= UVD_CGC_GATE__VCPU_MASK; 1288 1289 data3 &= ~UVD_CGC_GATE__REGS_MASK; 1290 } else { 1291 data3 = 0; 1292 } 1293 1294 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1295 WREG32(mmUVD_CGC_GATE, data3); 1296 } 1297 1298 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 1299 { 1300 uint32_t data, data2; 1301 1302 data = RREG32(mmUVD_CGC_CTRL); 1303 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 1304 1305 1306 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1307 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1308 1309 1310 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1311 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1312 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1313 1314 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1315 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1316 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1317 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1318 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1319 UVD_CGC_CTRL__SYS_MODE_MASK | 1320 UVD_CGC_CTRL__UDEC_MODE_MASK | 1321 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1322 UVD_CGC_CTRL__REGS_MODE_MASK | 1323 UVD_CGC_CTRL__RBC_MODE_MASK | 1324 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1325 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1326 UVD_CGC_CTRL__IDCT_MODE_MASK | 1327 UVD_CGC_CTRL__MPRD_MODE_MASK | 1328 UVD_CGC_CTRL__MPC_MODE_MASK | 1329 UVD_CGC_CTRL__LBSI_MODE_MASK | 1330 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1331 UVD_CGC_CTRL__WCB_MODE_MASK | 1332 UVD_CGC_CTRL__VCPU_MODE_MASK | 1333 UVD_CGC_CTRL__JPEG_MODE_MASK | 1334 UVD_CGC_CTRL__SCPU_MODE_MASK | 1335 UVD_CGC_CTRL__JPEG2_MODE_MASK); 1336 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1337 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1338 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1339 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1340 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1341 1342 WREG32(mmUVD_CGC_CTRL, data); 1343 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 1344 } 1345 1346 #if 0 1347 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 1348 { 1349 uint32_t data, data1, cgc_flags, suvd_flags; 1350 1351 data = RREG32(mmUVD_CGC_GATE); 1352 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 1353 1354 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1355 UVD_CGC_GATE__UDEC_MASK | 1356 UVD_CGC_GATE__MPEG2_MASK | 1357 UVD_CGC_GATE__RBC_MASK | 1358 UVD_CGC_GATE__LMI_MC_MASK | 1359 UVD_CGC_GATE__IDCT_MASK | 1360 UVD_CGC_GATE__MPRD_MASK | 1361 UVD_CGC_GATE__MPC_MASK | 1362 UVD_CGC_GATE__LBSI_MASK | 1363 UVD_CGC_GATE__LRBBM_MASK | 1364 UVD_CGC_GATE__UDEC_RE_MASK | 1365 UVD_CGC_GATE__UDEC_CM_MASK | 1366 UVD_CGC_GATE__UDEC_IT_MASK | 1367 UVD_CGC_GATE__UDEC_DB_MASK | 1368 UVD_CGC_GATE__UDEC_MP_MASK | 1369 UVD_CGC_GATE__WCB_MASK | 1370 UVD_CGC_GATE__VCPU_MASK | 1371 UVD_CGC_GATE__SCPU_MASK | 1372 UVD_CGC_GATE__JPEG_MASK | 1373 UVD_CGC_GATE__JPEG2_MASK; 1374 1375 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1376 UVD_SUVD_CGC_GATE__SIT_MASK | 1377 UVD_SUVD_CGC_GATE__SMP_MASK | 1378 UVD_SUVD_CGC_GATE__SCM_MASK | 1379 UVD_SUVD_CGC_GATE__SDB_MASK; 1380 1381 data |= cgc_flags; 1382 data1 |= suvd_flags; 1383 1384 WREG32(mmUVD_CGC_GATE, data); 1385 WREG32(mmUVD_SUVD_CGC_GATE, data1); 1386 } 1387 #endif 1388 1389 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, 1390 bool enable) 1391 { 1392 u32 orig, data; 1393 1394 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 1395 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1396 data |= 0xfff; 1397 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1398 1399 orig = data = RREG32(mmUVD_CGC_CTRL); 1400 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1401 if (orig != data) 1402 WREG32(mmUVD_CGC_CTRL, data); 1403 } else { 1404 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 1405 data &= ~0xfff; 1406 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 1407 1408 orig = data = RREG32(mmUVD_CGC_CTRL); 1409 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 1410 if (orig != data) 1411 WREG32(mmUVD_CGC_CTRL, data); 1412 } 1413 } 1414 1415 static int uvd_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1416 enum amd_clockgating_state state) 1417 { 1418 struct amdgpu_device *adev = ip_block->adev; 1419 bool enable = (state == AMD_CG_STATE_GATE); 1420 1421 if (enable) { 1422 /* wait for STATUS to clear */ 1423 if (uvd_v6_0_wait_for_idle(ip_block)) 1424 return -EBUSY; 1425 uvd_v6_0_enable_clock_gating(adev, true); 1426 /* enable HW gates because UVD is idle */ 1427 /* uvd_v6_0_set_hw_clock_gating(adev); */ 1428 } else { 1429 /* disable HW gating and enable Sw gating */ 1430 uvd_v6_0_enable_clock_gating(adev, false); 1431 } 1432 uvd_v6_0_set_sw_clock_gating(adev); 1433 return 0; 1434 } 1435 1436 static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1437 enum amd_powergating_state state) 1438 { 1439 /* This doesn't actually powergate the UVD block. 1440 * That's done in the dpm code via the SMC. This 1441 * just re-inits the block as necessary. The actual 1442 * gating still happens in the dpm code. We should 1443 * revisit this when there is a cleaner line between 1444 * the smc and the hw blocks 1445 */ 1446 struct amdgpu_device *adev = ip_block->adev; 1447 int ret = 0; 1448 1449 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1450 1451 if (state == AMD_PG_STATE_GATE) { 1452 uvd_v6_0_stop(adev); 1453 } else { 1454 ret = uvd_v6_0_start(adev); 1455 if (ret) 1456 goto out; 1457 } 1458 1459 out: 1460 return ret; 1461 } 1462 1463 static void uvd_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1464 { 1465 struct amdgpu_device *adev = ip_block->adev; 1466 int data; 1467 1468 mutex_lock(&adev->pm.mutex); 1469 1470 if (adev->flags & AMD_IS_APU) 1471 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); 1472 else 1473 data = RREG32_SMC(ixCURRENT_PG_STATUS); 1474 1475 if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 1476 drm_info(adev_to_drm(adev), "Cannot get clockgating state when UVD is powergated.\n"); 1477 goto out; 1478 } 1479 1480 /* AMD_CG_SUPPORT_UVD_MGCG */ 1481 data = RREG32(mmUVD_CGC_CTRL); 1482 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 1483 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 1484 1485 out: 1486 mutex_unlock(&adev->pm.mutex); 1487 } 1488 1489 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 1490 .name = "uvd_v6_0", 1491 .early_init = uvd_v6_0_early_init, 1492 .sw_init = uvd_v6_0_sw_init, 1493 .sw_fini = uvd_v6_0_sw_fini, 1494 .hw_init = uvd_v6_0_hw_init, 1495 .hw_fini = uvd_v6_0_hw_fini, 1496 .prepare_suspend = uvd_v6_0_prepare_suspend, 1497 .suspend = uvd_v6_0_suspend, 1498 .resume = uvd_v6_0_resume, 1499 .is_idle = uvd_v6_0_is_idle, 1500 .wait_for_idle = uvd_v6_0_wait_for_idle, 1501 .soft_reset = uvd_v6_0_soft_reset, 1502 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 1503 .set_powergating_state = uvd_v6_0_set_powergating_state, 1504 .get_clockgating_state = uvd_v6_0_get_clockgating_state, 1505 }; 1506 1507 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { 1508 .type = AMDGPU_RING_TYPE_UVD, 1509 .align_mask = 0xf, 1510 .support_64bit_ptrs = false, 1511 .no_user_fence = true, 1512 .get_rptr = uvd_v6_0_ring_get_rptr, 1513 .get_wptr = uvd_v6_0_ring_get_wptr, 1514 .set_wptr = uvd_v6_0_ring_set_wptr, 1515 .parse_cs = amdgpu_uvd_ring_parse_cs, 1516 .emit_frame_size = 1517 6 + /* hdp invalidate */ 1518 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1519 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ 1520 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1521 .emit_ib = uvd_v6_0_ring_emit_ib, 1522 .emit_fence = uvd_v6_0_ring_emit_fence, 1523 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1524 .test_ring = uvd_v6_0_ring_test_ring, 1525 .test_ib = amdgpu_uvd_ring_test_ib, 1526 .insert_nop = uvd_v6_0_ring_insert_nop, 1527 .pad_ib = amdgpu_ring_generic_pad_ib, 1528 .begin_use = amdgpu_uvd_ring_begin_use, 1529 .end_use = amdgpu_uvd_ring_end_use, 1530 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1531 }; 1532 1533 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { 1534 .type = AMDGPU_RING_TYPE_UVD, 1535 .align_mask = 0xf, 1536 .support_64bit_ptrs = false, 1537 .no_user_fence = true, 1538 .get_rptr = uvd_v6_0_ring_get_rptr, 1539 .get_wptr = uvd_v6_0_ring_get_wptr, 1540 .set_wptr = uvd_v6_0_ring_set_wptr, 1541 .emit_frame_size = 1542 6 + /* hdp invalidate */ 1543 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ 1544 VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */ 1545 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ 1546 .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ 1547 .emit_ib = uvd_v6_0_ring_emit_ib, 1548 .emit_fence = uvd_v6_0_ring_emit_fence, 1549 .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, 1550 .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync, 1551 .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, 1552 .test_ring = uvd_v6_0_ring_test_ring, 1553 .test_ib = amdgpu_uvd_ring_test_ib, 1554 .insert_nop = uvd_v6_0_ring_insert_nop, 1555 .pad_ib = amdgpu_ring_generic_pad_ib, 1556 .begin_use = amdgpu_uvd_ring_begin_use, 1557 .end_use = amdgpu_uvd_ring_end_use, 1558 .emit_wreg = uvd_v6_0_ring_emit_wreg, 1559 }; 1560 1561 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { 1562 .type = AMDGPU_RING_TYPE_UVD_ENC, 1563 .align_mask = 0x3f, 1564 .nop = HEVC_ENC_CMD_NO_OP, 1565 .support_64bit_ptrs = false, 1566 .no_user_fence = true, 1567 .get_rptr = uvd_v6_0_enc_ring_get_rptr, 1568 .get_wptr = uvd_v6_0_enc_ring_get_wptr, 1569 .set_wptr = uvd_v6_0_enc_ring_set_wptr, 1570 .emit_frame_size = 1571 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */ 1572 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */ 1573 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */ 1574 1, /* uvd_v6_0_enc_ring_insert_end */ 1575 .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */ 1576 .emit_ib = uvd_v6_0_enc_ring_emit_ib, 1577 .emit_fence = uvd_v6_0_enc_ring_emit_fence, 1578 .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush, 1579 .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync, 1580 .test_ring = uvd_v6_0_enc_ring_test_ring, 1581 .test_ib = uvd_v6_0_enc_ring_test_ib, 1582 .insert_nop = amdgpu_ring_insert_nop, 1583 .insert_end = uvd_v6_0_enc_ring_insert_end, 1584 .pad_ib = amdgpu_ring_generic_pad_ib, 1585 .begin_use = amdgpu_uvd_ring_begin_use, 1586 .end_use = amdgpu_uvd_ring_end_use, 1587 }; 1588 1589 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1590 { 1591 if (adev->asic_type >= CHIP_POLARIS10) { 1592 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs; 1593 drm_info(adev_to_drm(adev), "UVD is enabled in VM mode\n"); 1594 } else { 1595 adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs; 1596 drm_info(adev_to_drm(adev), "UVD is enabled in physical mode\n"); 1597 } 1598 } 1599 1600 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1601 { 1602 int i; 1603 1604 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 1605 adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs; 1606 1607 drm_info(adev_to_drm(adev), "UVD ENC is enabled in VM mode\n"); 1608 } 1609 1610 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 1611 .set = uvd_v6_0_set_interrupt_state, 1612 .process = uvd_v6_0_process_interrupt, 1613 }; 1614 1615 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1616 { 1617 if (uvd_v6_0_enc_support(adev)) 1618 adev->uvd.inst->irq.num_types = adev->uvd.num_enc_rings + 1; 1619 else 1620 adev->uvd.inst->irq.num_types = 1; 1621 1622 adev->uvd.inst->irq.funcs = &uvd_v6_0_irq_funcs; 1623 } 1624 1625 const struct amdgpu_ip_block_version uvd_v6_0_ip_block = 1626 { 1627 .type = AMD_IP_BLOCK_TYPE_UVD, 1628 .major = 6, 1629 .minor = 0, 1630 .rev = 0, 1631 .funcs = &uvd_v6_0_ip_funcs, 1632 }; 1633 1634 const struct amdgpu_ip_block_version uvd_v6_2_ip_block = 1635 { 1636 .type = AMD_IP_BLOCK_TYPE_UVD, 1637 .major = 6, 1638 .minor = 2, 1639 .rev = 0, 1640 .funcs = &uvd_v6_0_ip_funcs, 1641 }; 1642 1643 const struct amdgpu_ip_block_version uvd_v6_3_ip_block = 1644 { 1645 .type = AMD_IP_BLOCK_TYPE_UVD, 1646 .major = 6, 1647 .minor = 3, 1648 .rev = 0, 1649 .funcs = &uvd_v6_0_ip_funcs, 1650 }; 1651