1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "vid.h" 30 #include "uvd/uvd_6_0_d.h" 31 #include "uvd/uvd_6_0_sh_mask.h" 32 #include "oss/oss_2_0_d.h" 33 #include "oss/oss_2_0_sh_mask.h" 34 #include "vi.h" 35 36 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev); 37 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); 38 static int uvd_v6_0_start(struct amdgpu_device *adev); 39 static void uvd_v6_0_stop(struct amdgpu_device *adev); 40 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 41 42 /** 43 * uvd_v6_0_ring_get_rptr - get read pointer 44 * 45 * @ring: amdgpu_ring pointer 46 * 47 * Returns the current hardware read pointer 48 */ 49 static uint32_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 return RREG32(mmUVD_RBC_RB_RPTR); 54 } 55 56 /** 57 * uvd_v6_0_ring_get_wptr - get write pointer 58 * 59 * @ring: amdgpu_ring pointer 60 * 61 * Returns the current hardware write pointer 62 */ 63 static uint32_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 64 { 65 struct amdgpu_device *adev = ring->adev; 66 67 return RREG32(mmUVD_RBC_RB_WPTR); 68 } 69 70 /** 71 * uvd_v6_0_ring_set_wptr - set write pointer 72 * 73 * @ring: amdgpu_ring pointer 74 * 75 * Commits the write pointer to the hardware 76 */ 77 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring) 78 { 79 struct amdgpu_device *adev = ring->adev; 80 81 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 82 } 83 84 static int uvd_v6_0_early_init(void *handle) 85 { 86 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 87 88 uvd_v6_0_set_ring_funcs(adev); 89 uvd_v6_0_set_irq_funcs(adev); 90 91 return 0; 92 } 93 94 static int uvd_v6_0_sw_init(void *handle) 95 { 96 struct amdgpu_ring *ring; 97 int r; 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 100 /* UVD TRAP */ 101 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 102 if (r) 103 return r; 104 105 r = amdgpu_uvd_sw_init(adev); 106 if (r) 107 return r; 108 109 r = amdgpu_uvd_resume(adev); 110 if (r) 111 return r; 112 113 ring = &adev->uvd.ring; 114 sprintf(ring->name, "uvd"); 115 r = amdgpu_ring_init(adev, ring, 4096, CP_PACKET2, 0xf, 116 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); 117 118 return r; 119 } 120 121 static int uvd_v6_0_sw_fini(void *handle) 122 { 123 int r; 124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 125 126 r = amdgpu_uvd_suspend(adev); 127 if (r) 128 return r; 129 130 r = amdgpu_uvd_sw_fini(adev); 131 if (r) 132 return r; 133 134 return r; 135 } 136 137 /** 138 * uvd_v6_0_hw_init - start and test UVD block 139 * 140 * @adev: amdgpu_device pointer 141 * 142 * Initialize the hardware, boot up the VCPU and do some testing 143 */ 144 static int uvd_v6_0_hw_init(void *handle) 145 { 146 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 147 struct amdgpu_ring *ring = &adev->uvd.ring; 148 uint32_t tmp; 149 int r; 150 151 r = uvd_v6_0_start(adev); 152 if (r) 153 goto done; 154 155 ring->ready = true; 156 r = amdgpu_ring_test_ring(ring); 157 if (r) { 158 ring->ready = false; 159 goto done; 160 } 161 162 r = amdgpu_ring_alloc(ring, 10); 163 if (r) { 164 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 165 goto done; 166 } 167 168 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 169 amdgpu_ring_write(ring, tmp); 170 amdgpu_ring_write(ring, 0xFFFFF); 171 172 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 173 amdgpu_ring_write(ring, tmp); 174 amdgpu_ring_write(ring, 0xFFFFF); 175 176 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 177 amdgpu_ring_write(ring, tmp); 178 amdgpu_ring_write(ring, 0xFFFFF); 179 180 /* Clear timeout status bits */ 181 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 182 amdgpu_ring_write(ring, 0x8); 183 184 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 185 amdgpu_ring_write(ring, 3); 186 187 amdgpu_ring_commit(ring); 188 189 done: 190 if (!r) 191 DRM_INFO("UVD initialized successfully.\n"); 192 193 return r; 194 } 195 196 /** 197 * uvd_v6_0_hw_fini - stop the hardware block 198 * 199 * @adev: amdgpu_device pointer 200 * 201 * Stop the UVD block, mark ring as not ready any more 202 */ 203 static int uvd_v6_0_hw_fini(void *handle) 204 { 205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 206 struct amdgpu_ring *ring = &adev->uvd.ring; 207 208 uvd_v6_0_stop(adev); 209 ring->ready = false; 210 211 return 0; 212 } 213 214 static int uvd_v6_0_suspend(void *handle) 215 { 216 int r; 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 219 r = uvd_v6_0_hw_fini(adev); 220 if (r) 221 return r; 222 223 /* Skip this for APU for now */ 224 if (!(adev->flags & AMD_IS_APU)) { 225 r = amdgpu_uvd_suspend(adev); 226 if (r) 227 return r; 228 } 229 230 return r; 231 } 232 233 static int uvd_v6_0_resume(void *handle) 234 { 235 int r; 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237 238 /* Skip this for APU for now */ 239 if (!(adev->flags & AMD_IS_APU)) { 240 r = amdgpu_uvd_resume(adev); 241 if (r) 242 return r; 243 } 244 r = uvd_v6_0_hw_init(adev); 245 if (r) 246 return r; 247 248 return r; 249 } 250 251 /** 252 * uvd_v6_0_mc_resume - memory controller programming 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Let the UVD memory controller know it's offsets 257 */ 258 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev) 259 { 260 uint64_t offset; 261 uint32_t size; 262 263 /* programm memory controller bits 0-27 */ 264 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 265 lower_32_bits(adev->uvd.gpu_addr)); 266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 267 upper_32_bits(adev->uvd.gpu_addr)); 268 269 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 270 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 271 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 272 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 273 274 offset += size; 275 size = AMDGPU_UVD_HEAP_SIZE; 276 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 277 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 278 279 offset += size; 280 size = AMDGPU_UVD_STACK_SIZE + 281 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 282 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 283 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 284 285 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 286 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 287 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 288 289 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 290 } 291 292 #if 0 293 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev, 294 bool enable) 295 { 296 u32 data, data1; 297 298 data = RREG32(mmUVD_CGC_GATE); 299 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 300 if (enable) { 301 data |= UVD_CGC_GATE__SYS_MASK | 302 UVD_CGC_GATE__UDEC_MASK | 303 UVD_CGC_GATE__MPEG2_MASK | 304 UVD_CGC_GATE__RBC_MASK | 305 UVD_CGC_GATE__LMI_MC_MASK | 306 UVD_CGC_GATE__IDCT_MASK | 307 UVD_CGC_GATE__MPRD_MASK | 308 UVD_CGC_GATE__MPC_MASK | 309 UVD_CGC_GATE__LBSI_MASK | 310 UVD_CGC_GATE__LRBBM_MASK | 311 UVD_CGC_GATE__UDEC_RE_MASK | 312 UVD_CGC_GATE__UDEC_CM_MASK | 313 UVD_CGC_GATE__UDEC_IT_MASK | 314 UVD_CGC_GATE__UDEC_DB_MASK | 315 UVD_CGC_GATE__UDEC_MP_MASK | 316 UVD_CGC_GATE__WCB_MASK | 317 UVD_CGC_GATE__VCPU_MASK | 318 UVD_CGC_GATE__SCPU_MASK; 319 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | 320 UVD_SUVD_CGC_GATE__SIT_MASK | 321 UVD_SUVD_CGC_GATE__SMP_MASK | 322 UVD_SUVD_CGC_GATE__SCM_MASK | 323 UVD_SUVD_CGC_GATE__SDB_MASK | 324 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 325 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 326 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 327 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 328 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 329 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 330 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 331 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; 332 } else { 333 data &= ~(UVD_CGC_GATE__SYS_MASK | 334 UVD_CGC_GATE__UDEC_MASK | 335 UVD_CGC_GATE__MPEG2_MASK | 336 UVD_CGC_GATE__RBC_MASK | 337 UVD_CGC_GATE__LMI_MC_MASK | 338 UVD_CGC_GATE__LMI_UMC_MASK | 339 UVD_CGC_GATE__IDCT_MASK | 340 UVD_CGC_GATE__MPRD_MASK | 341 UVD_CGC_GATE__MPC_MASK | 342 UVD_CGC_GATE__LBSI_MASK | 343 UVD_CGC_GATE__LRBBM_MASK | 344 UVD_CGC_GATE__UDEC_RE_MASK | 345 UVD_CGC_GATE__UDEC_CM_MASK | 346 UVD_CGC_GATE__UDEC_IT_MASK | 347 UVD_CGC_GATE__UDEC_DB_MASK | 348 UVD_CGC_GATE__UDEC_MP_MASK | 349 UVD_CGC_GATE__WCB_MASK | 350 UVD_CGC_GATE__VCPU_MASK | 351 UVD_CGC_GATE__SCPU_MASK); 352 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK | 353 UVD_SUVD_CGC_GATE__SIT_MASK | 354 UVD_SUVD_CGC_GATE__SMP_MASK | 355 UVD_SUVD_CGC_GATE__SCM_MASK | 356 UVD_SUVD_CGC_GATE__SDB_MASK | 357 UVD_SUVD_CGC_GATE__SRE_H264_MASK | 358 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | 359 UVD_SUVD_CGC_GATE__SIT_H264_MASK | 360 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | 361 UVD_SUVD_CGC_GATE__SCM_H264_MASK | 362 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | 363 UVD_SUVD_CGC_GATE__SDB_H264_MASK | 364 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK); 365 } 366 WREG32(mmUVD_CGC_GATE, data); 367 WREG32(mmUVD_SUVD_CGC_GATE, data1); 368 } 369 #endif 370 371 /** 372 * uvd_v6_0_start - start UVD block 373 * 374 * @adev: amdgpu_device pointer 375 * 376 * Setup and start the UVD block 377 */ 378 static int uvd_v6_0_start(struct amdgpu_device *adev) 379 { 380 struct amdgpu_ring *ring = &adev->uvd.ring; 381 uint32_t rb_bufsz, tmp; 382 uint32_t lmi_swap_cntl; 383 uint32_t mp_swap_cntl; 384 int i, j, r; 385 386 /*disable DPG */ 387 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 388 389 /* disable byte swapping */ 390 lmi_swap_cntl = 0; 391 mp_swap_cntl = 0; 392 393 uvd_v6_0_mc_resume(adev); 394 395 /* Set dynamic clock gating in S/W control mode */ 396 if (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG) { 397 uvd_v6_0_set_sw_clock_gating(adev); 398 } else { 399 /* disable clock gating */ 400 uint32_t data = RREG32(mmUVD_CGC_CTRL); 401 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 402 WREG32(mmUVD_CGC_CTRL, data); 403 } 404 405 /* disable interupt */ 406 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 407 408 /* stall UMC and register bus before resetting VCPU */ 409 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 410 mdelay(1); 411 412 /* put LMI, VCPU, RBC etc... into reset */ 413 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 414 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 415 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 416 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 417 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 418 mdelay(5); 419 420 /* take UVD block out of reset */ 421 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 422 mdelay(5); 423 424 /* initialize UVD memory controller */ 425 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 426 (1 << 21) | (1 << 9) | (1 << 20)); 427 428 #ifdef __BIG_ENDIAN 429 /* swap (8 in 32) RB and IB */ 430 lmi_swap_cntl = 0xa; 431 mp_swap_cntl = 0; 432 #endif 433 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 434 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 435 436 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 437 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 438 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 439 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 440 WREG32(mmUVD_MPC_SET_ALU, 0); 441 WREG32(mmUVD_MPC_SET_MUX, 0x88); 442 443 /* take all subblocks out of reset, except VCPU */ 444 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 445 mdelay(5); 446 447 /* enable VCPU clock */ 448 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 449 450 /* enable UMC */ 451 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 452 453 /* boot up the VCPU */ 454 WREG32(mmUVD_SOFT_RESET, 0); 455 mdelay(10); 456 457 for (i = 0; i < 10; ++i) { 458 uint32_t status; 459 460 for (j = 0; j < 100; ++j) { 461 status = RREG32(mmUVD_STATUS); 462 if (status & 2) 463 break; 464 mdelay(10); 465 } 466 r = 0; 467 if (status & 2) 468 break; 469 470 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 471 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 472 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 473 mdelay(10); 474 WREG32_P(mmUVD_SOFT_RESET, 0, 475 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 476 mdelay(10); 477 r = -1; 478 } 479 480 if (r) { 481 DRM_ERROR("UVD not responding, giving up!!!\n"); 482 return r; 483 } 484 /* enable master interrupt */ 485 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 486 487 /* clear the bit 4 of UVD_STATUS */ 488 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 489 490 rb_bufsz = order_base_2(ring->ring_size); 491 tmp = 0; 492 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 493 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 494 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 495 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 496 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 497 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 498 /* force RBC into idle state */ 499 WREG32(mmUVD_RBC_RB_CNTL, tmp); 500 501 /* set the write pointer delay */ 502 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 503 504 /* set the wb address */ 505 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 506 507 /* programm the RB_BASE for ring buffer */ 508 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 509 lower_32_bits(ring->gpu_addr)); 510 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 511 upper_32_bits(ring->gpu_addr)); 512 513 /* Initialize the ring buffer's read and write pointers */ 514 WREG32(mmUVD_RBC_RB_RPTR, 0); 515 516 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 517 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 518 519 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 520 521 return 0; 522 } 523 524 /** 525 * uvd_v6_0_stop - stop UVD block 526 * 527 * @adev: amdgpu_device pointer 528 * 529 * stop the UVD block 530 */ 531 static void uvd_v6_0_stop(struct amdgpu_device *adev) 532 { 533 /* force RBC into idle state */ 534 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 535 536 /* Stall UMC and register bus before resetting VCPU */ 537 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 538 mdelay(1); 539 540 /* put VCPU into reset */ 541 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 542 mdelay(5); 543 544 /* disable VCPU clock */ 545 WREG32(mmUVD_VCPU_CNTL, 0x0); 546 547 /* Unstall UMC and register bus */ 548 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 549 } 550 551 /** 552 * uvd_v6_0_ring_emit_fence - emit an fence & trap command 553 * 554 * @ring: amdgpu_ring pointer 555 * @fence: fence to emit 556 * 557 * Write a fence and a trap command to the ring. 558 */ 559 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 560 unsigned flags) 561 { 562 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 563 564 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 565 amdgpu_ring_write(ring, seq); 566 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 567 amdgpu_ring_write(ring, addr & 0xffffffff); 568 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 569 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 570 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 571 amdgpu_ring_write(ring, 0); 572 573 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 574 amdgpu_ring_write(ring, 0); 575 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 576 amdgpu_ring_write(ring, 0); 577 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 578 amdgpu_ring_write(ring, 2); 579 } 580 581 /** 582 * uvd_v6_0_ring_test_ring - register write test 583 * 584 * @ring: amdgpu_ring pointer 585 * 586 * Test if we can successfully write to the context register 587 */ 588 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring) 589 { 590 struct amdgpu_device *adev = ring->adev; 591 uint32_t tmp = 0; 592 unsigned i; 593 int r; 594 595 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 596 r = amdgpu_ring_alloc(ring, 3); 597 if (r) { 598 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 599 ring->idx, r); 600 return r; 601 } 602 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 603 amdgpu_ring_write(ring, 0xDEADBEEF); 604 amdgpu_ring_commit(ring); 605 for (i = 0; i < adev->usec_timeout; i++) { 606 tmp = RREG32(mmUVD_CONTEXT_ID); 607 if (tmp == 0xDEADBEEF) 608 break; 609 DRM_UDELAY(1); 610 } 611 612 if (i < adev->usec_timeout) { 613 DRM_INFO("ring test on %d succeeded in %d usecs\n", 614 ring->idx, i); 615 } else { 616 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 617 ring->idx, tmp); 618 r = -EINVAL; 619 } 620 return r; 621 } 622 623 /** 624 * uvd_v6_0_ring_emit_ib - execute indirect buffer 625 * 626 * @ring: amdgpu_ring pointer 627 * @ib: indirect buffer to execute 628 * 629 * Write ring commands to execute the indirect buffer 630 */ 631 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 632 struct amdgpu_ib *ib) 633 { 634 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 635 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 636 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 637 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 638 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 639 amdgpu_ring_write(ring, ib->length_dw); 640 } 641 642 /** 643 * uvd_v6_0_ring_test_ib - test ib execution 644 * 645 * @ring: amdgpu_ring pointer 646 * 647 * Test if we can successfully execute an IB 648 */ 649 static int uvd_v6_0_ring_test_ib(struct amdgpu_ring *ring) 650 { 651 struct fence *fence = NULL; 652 int r; 653 654 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 655 if (r) { 656 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r); 657 goto error; 658 } 659 660 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 661 if (r) { 662 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r); 663 goto error; 664 } 665 666 r = fence_wait(fence, false); 667 if (r) { 668 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 669 goto error; 670 } 671 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 672 error: 673 fence_put(fence); 674 return r; 675 } 676 677 static bool uvd_v6_0_is_idle(void *handle) 678 { 679 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 680 681 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 682 } 683 684 static int uvd_v6_0_wait_for_idle(void *handle) 685 { 686 unsigned i; 687 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 688 689 for (i = 0; i < adev->usec_timeout; i++) { 690 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 691 return 0; 692 } 693 return -ETIMEDOUT; 694 } 695 696 static int uvd_v6_0_soft_reset(void *handle) 697 { 698 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 699 700 uvd_v6_0_stop(adev); 701 702 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 703 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 704 mdelay(5); 705 706 return uvd_v6_0_start(adev); 707 } 708 709 static void uvd_v6_0_print_status(void *handle) 710 { 711 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 712 dev_info(adev->dev, "UVD 6.0 registers\n"); 713 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n", 714 RREG32(mmUVD_SEMA_ADDR_LOW)); 715 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n", 716 RREG32(mmUVD_SEMA_ADDR_HIGH)); 717 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n", 718 RREG32(mmUVD_SEMA_CMD)); 719 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n", 720 RREG32(mmUVD_GPCOM_VCPU_CMD)); 721 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n", 722 RREG32(mmUVD_GPCOM_VCPU_DATA0)); 723 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n", 724 RREG32(mmUVD_GPCOM_VCPU_DATA1)); 725 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n", 726 RREG32(mmUVD_ENGINE_CNTL)); 727 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 728 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 729 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 730 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 731 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 732 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 733 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n", 734 RREG32(mmUVD_SEMA_CNTL)); 735 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n", 736 RREG32(mmUVD_LMI_EXT40_ADDR)); 737 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n", 738 RREG32(mmUVD_CTX_INDEX)); 739 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n", 740 RREG32(mmUVD_CTX_DATA)); 741 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n", 742 RREG32(mmUVD_CGC_GATE)); 743 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n", 744 RREG32(mmUVD_CGC_CTRL)); 745 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n", 746 RREG32(mmUVD_LMI_CTRL2)); 747 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n", 748 RREG32(mmUVD_MASTINT_EN)); 749 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n", 750 RREG32(mmUVD_LMI_ADDR_EXT)); 751 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n", 752 RREG32(mmUVD_LMI_CTRL)); 753 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n", 754 RREG32(mmUVD_LMI_SWAP_CNTL)); 755 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n", 756 RREG32(mmUVD_MP_SWAP_CNTL)); 757 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n", 758 RREG32(mmUVD_MPC_SET_MUXA0)); 759 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n", 760 RREG32(mmUVD_MPC_SET_MUXA1)); 761 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n", 762 RREG32(mmUVD_MPC_SET_MUXB0)); 763 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n", 764 RREG32(mmUVD_MPC_SET_MUXB1)); 765 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n", 766 RREG32(mmUVD_MPC_SET_MUX)); 767 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n", 768 RREG32(mmUVD_MPC_SET_ALU)); 769 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n", 770 RREG32(mmUVD_VCPU_CACHE_OFFSET0)); 771 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n", 772 RREG32(mmUVD_VCPU_CACHE_SIZE0)); 773 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n", 774 RREG32(mmUVD_VCPU_CACHE_OFFSET1)); 775 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n", 776 RREG32(mmUVD_VCPU_CACHE_SIZE1)); 777 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n", 778 RREG32(mmUVD_VCPU_CACHE_OFFSET2)); 779 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n", 780 RREG32(mmUVD_VCPU_CACHE_SIZE2)); 781 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n", 782 RREG32(mmUVD_VCPU_CNTL)); 783 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n", 784 RREG32(mmUVD_SOFT_RESET)); 785 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n", 786 RREG32(mmUVD_RBC_IB_SIZE)); 787 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n", 788 RREG32(mmUVD_RBC_RB_RPTR)); 789 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n", 790 RREG32(mmUVD_RBC_RB_WPTR)); 791 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n", 792 RREG32(mmUVD_RBC_RB_WPTR_CNTL)); 793 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n", 794 RREG32(mmUVD_RBC_RB_CNTL)); 795 dev_info(adev->dev, " UVD_STATUS=0x%08X\n", 796 RREG32(mmUVD_STATUS)); 797 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n", 798 RREG32(mmUVD_SEMA_TIMEOUT_STATUS)); 799 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 800 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)); 801 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n", 802 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)); 803 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n", 804 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)); 805 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n", 806 RREG32(mmUVD_CONTEXT_ID)); 807 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n", 808 RREG32(mmUVD_UDEC_ADDR_CONFIG)); 809 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n", 810 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG)); 811 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n", 812 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG)); 813 } 814 815 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 816 struct amdgpu_irq_src *source, 817 unsigned type, 818 enum amdgpu_interrupt_state state) 819 { 820 // TODO 821 return 0; 822 } 823 824 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, 825 struct amdgpu_irq_src *source, 826 struct amdgpu_iv_entry *entry) 827 { 828 DRM_DEBUG("IH: UVD TRAP\n"); 829 amdgpu_fence_process(&adev->uvd.ring); 830 return 0; 831 } 832 833 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 834 { 835 uint32_t data, data1, data2, suvd_flags; 836 837 data = RREG32(mmUVD_CGC_CTRL); 838 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 839 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 840 841 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 842 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 843 844 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 845 UVD_SUVD_CGC_GATE__SIT_MASK | 846 UVD_SUVD_CGC_GATE__SMP_MASK | 847 UVD_SUVD_CGC_GATE__SCM_MASK | 848 UVD_SUVD_CGC_GATE__SDB_MASK; 849 850 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 851 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 852 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 853 854 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 855 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 856 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 857 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 858 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 859 UVD_CGC_CTRL__SYS_MODE_MASK | 860 UVD_CGC_CTRL__UDEC_MODE_MASK | 861 UVD_CGC_CTRL__MPEG2_MODE_MASK | 862 UVD_CGC_CTRL__REGS_MODE_MASK | 863 UVD_CGC_CTRL__RBC_MODE_MASK | 864 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 865 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 866 UVD_CGC_CTRL__IDCT_MODE_MASK | 867 UVD_CGC_CTRL__MPRD_MODE_MASK | 868 UVD_CGC_CTRL__MPC_MODE_MASK | 869 UVD_CGC_CTRL__LBSI_MODE_MASK | 870 UVD_CGC_CTRL__LRBBM_MODE_MASK | 871 UVD_CGC_CTRL__WCB_MODE_MASK | 872 UVD_CGC_CTRL__VCPU_MODE_MASK | 873 UVD_CGC_CTRL__JPEG_MODE_MASK | 874 UVD_CGC_CTRL__SCPU_MODE_MASK | 875 UVD_CGC_CTRL__JPEG2_MODE_MASK); 876 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 877 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 878 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 879 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 880 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 881 data1 |= suvd_flags; 882 883 WREG32(mmUVD_CGC_CTRL, data); 884 WREG32(mmUVD_CGC_GATE, 0); 885 WREG32(mmUVD_SUVD_CGC_GATE, data1); 886 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 887 } 888 889 #if 0 890 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) 891 { 892 uint32_t data, data1, cgc_flags, suvd_flags; 893 894 data = RREG32(mmUVD_CGC_GATE); 895 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 896 897 cgc_flags = UVD_CGC_GATE__SYS_MASK | 898 UVD_CGC_GATE__UDEC_MASK | 899 UVD_CGC_GATE__MPEG2_MASK | 900 UVD_CGC_GATE__RBC_MASK | 901 UVD_CGC_GATE__LMI_MC_MASK | 902 UVD_CGC_GATE__IDCT_MASK | 903 UVD_CGC_GATE__MPRD_MASK | 904 UVD_CGC_GATE__MPC_MASK | 905 UVD_CGC_GATE__LBSI_MASK | 906 UVD_CGC_GATE__LRBBM_MASK | 907 UVD_CGC_GATE__UDEC_RE_MASK | 908 UVD_CGC_GATE__UDEC_CM_MASK | 909 UVD_CGC_GATE__UDEC_IT_MASK | 910 UVD_CGC_GATE__UDEC_DB_MASK | 911 UVD_CGC_GATE__UDEC_MP_MASK | 912 UVD_CGC_GATE__WCB_MASK | 913 UVD_CGC_GATE__VCPU_MASK | 914 UVD_CGC_GATE__SCPU_MASK | 915 UVD_CGC_GATE__JPEG_MASK | 916 UVD_CGC_GATE__JPEG2_MASK; 917 918 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 919 UVD_SUVD_CGC_GATE__SIT_MASK | 920 UVD_SUVD_CGC_GATE__SMP_MASK | 921 UVD_SUVD_CGC_GATE__SCM_MASK | 922 UVD_SUVD_CGC_GATE__SDB_MASK; 923 924 data |= cgc_flags; 925 data1 |= suvd_flags; 926 927 WREG32(mmUVD_CGC_GATE, data); 928 WREG32(mmUVD_SUVD_CGC_GATE, data1); 929 } 930 #endif 931 932 static int uvd_v6_0_set_clockgating_state(void *handle, 933 enum amd_clockgating_state state) 934 { 935 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 936 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 937 static int curstate = -1; 938 939 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 940 return 0; 941 942 if (curstate == state) 943 return 0; 944 945 curstate = state; 946 if (enable) { 947 /* disable HW gating and enable Sw gating */ 948 uvd_v6_0_set_sw_clock_gating(adev); 949 } else { 950 /* wait for STATUS to clear */ 951 if (uvd_v6_0_wait_for_idle(handle)) 952 return -EBUSY; 953 954 /* enable HW gates because UVD is idle */ 955 /* uvd_v6_0_set_hw_clock_gating(adev); */ 956 } 957 958 return 0; 959 } 960 961 static int uvd_v6_0_set_powergating_state(void *handle, 962 enum amd_powergating_state state) 963 { 964 /* This doesn't actually powergate the UVD block. 965 * That's done in the dpm code via the SMC. This 966 * just re-inits the block as necessary. The actual 967 * gating still happens in the dpm code. We should 968 * revisit this when there is a cleaner line between 969 * the smc and the hw blocks 970 */ 971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 972 973 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 974 return 0; 975 976 if (state == AMD_PG_STATE_GATE) { 977 uvd_v6_0_stop(adev); 978 return 0; 979 } else { 980 return uvd_v6_0_start(adev); 981 } 982 } 983 984 const struct amd_ip_funcs uvd_v6_0_ip_funcs = { 985 .early_init = uvd_v6_0_early_init, 986 .late_init = NULL, 987 .sw_init = uvd_v6_0_sw_init, 988 .sw_fini = uvd_v6_0_sw_fini, 989 .hw_init = uvd_v6_0_hw_init, 990 .hw_fini = uvd_v6_0_hw_fini, 991 .suspend = uvd_v6_0_suspend, 992 .resume = uvd_v6_0_resume, 993 .is_idle = uvd_v6_0_is_idle, 994 .wait_for_idle = uvd_v6_0_wait_for_idle, 995 .soft_reset = uvd_v6_0_soft_reset, 996 .print_status = uvd_v6_0_print_status, 997 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 998 .set_powergating_state = uvd_v6_0_set_powergating_state, 999 }; 1000 1001 static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { 1002 .get_rptr = uvd_v6_0_ring_get_rptr, 1003 .get_wptr = uvd_v6_0_ring_get_wptr, 1004 .set_wptr = uvd_v6_0_ring_set_wptr, 1005 .parse_cs = amdgpu_uvd_ring_parse_cs, 1006 .emit_ib = uvd_v6_0_ring_emit_ib, 1007 .emit_fence = uvd_v6_0_ring_emit_fence, 1008 .test_ring = uvd_v6_0_ring_test_ring, 1009 .test_ib = uvd_v6_0_ring_test_ib, 1010 .insert_nop = amdgpu_ring_insert_nop, 1011 .pad_ib = amdgpu_ring_generic_pad_ib, 1012 }; 1013 1014 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) 1015 { 1016 adev->uvd.ring.funcs = &uvd_v6_0_ring_funcs; 1017 } 1018 1019 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { 1020 .set = uvd_v6_0_set_interrupt_state, 1021 .process = uvd_v6_0_process_interrupt, 1022 }; 1023 1024 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1025 { 1026 adev->uvd.irq.num_types = 1; 1027 adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs; 1028 } 1029