1aaa36a97SAlex Deucher /*
2aaa36a97SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc.
3aaa36a97SAlex Deucher *
4aaa36a97SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a
5aaa36a97SAlex Deucher * copy of this software and associated documentation files (the "Software"),
6aaa36a97SAlex Deucher * to deal in the Software without restriction, including without limitation
7aaa36a97SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8aaa36a97SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the
9aaa36a97SAlex Deucher * Software is furnished to do so, subject to the following conditions:
10aaa36a97SAlex Deucher *
11aaa36a97SAlex Deucher * The above copyright notice and this permission notice shall be included in
12aaa36a97SAlex Deucher * all copies or substantial portions of the Software.
13aaa36a97SAlex Deucher *
14aaa36a97SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15aaa36a97SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16aaa36a97SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17aaa36a97SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18aaa36a97SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19aaa36a97SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20aaa36a97SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE.
21aaa36a97SAlex Deucher *
22aaa36a97SAlex Deucher * Authors: Christian König <christian.koenig@amd.com>
23aaa36a97SAlex Deucher */
24aaa36a97SAlex Deucher
25c366be54SSam Ravnborg #include <linux/delay.h>
26aaa36a97SAlex Deucher #include <linux/firmware.h>
27c366be54SSam Ravnborg
28aaa36a97SAlex Deucher #include "amdgpu.h"
29aaa36a97SAlex Deucher #include "amdgpu_uvd.h"
30aaa36a97SAlex Deucher #include "vid.h"
31aaa36a97SAlex Deucher #include "uvd/uvd_5_0_d.h"
32aaa36a97SAlex Deucher #include "uvd/uvd_5_0_sh_mask.h"
33aaa36a97SAlex Deucher #include "oss/oss_2_0_d.h"
34aaa36a97SAlex Deucher #include "oss/oss_2_0_sh_mask.h"
35d5b4e25dSChristian König #include "bif/bif_5_0_d.h"
36be3ecca7STom St Denis #include "vi.h"
374be5097cSRex Zhu #include "smu/smu_7_1_2_d.h"
384be5097cSRex Zhu #include "smu/smu_7_1_2_sh_mask.h"
39091aec0bSAndrey Grodzovsky #include "ivsrcid/ivsrcid_vislands30.h"
40aaa36a97SAlex Deucher
41aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
42aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
43aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev);
44aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev);
45809a6a62SRex Zhu static int uvd_v5_0_set_clockgating_state(void *handle,
46809a6a62SRex Zhu enum amd_clockgating_state state);
47809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
48809a6a62SRex Zhu bool enable);
49aaa36a97SAlex Deucher /**
50aaa36a97SAlex Deucher * uvd_v5_0_ring_get_rptr - get read pointer
51aaa36a97SAlex Deucher *
52aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
53aaa36a97SAlex Deucher *
54aaa36a97SAlex Deucher * Returns the current hardware read pointer
55aaa36a97SAlex Deucher */
uvd_v5_0_ring_get_rptr(struct amdgpu_ring * ring)56536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
57aaa36a97SAlex Deucher {
58aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev;
59aaa36a97SAlex Deucher
60aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_RPTR);
61aaa36a97SAlex Deucher }
62aaa36a97SAlex Deucher
63aaa36a97SAlex Deucher /**
64aaa36a97SAlex Deucher * uvd_v5_0_ring_get_wptr - get write pointer
65aaa36a97SAlex Deucher *
66aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
67aaa36a97SAlex Deucher *
68aaa36a97SAlex Deucher * Returns the current hardware write pointer
69aaa36a97SAlex Deucher */
uvd_v5_0_ring_get_wptr(struct amdgpu_ring * ring)70536fbf94SKen Wang static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
71aaa36a97SAlex Deucher {
72aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev;
73aaa36a97SAlex Deucher
74aaa36a97SAlex Deucher return RREG32(mmUVD_RBC_RB_WPTR);
75aaa36a97SAlex Deucher }
76aaa36a97SAlex Deucher
77aaa36a97SAlex Deucher /**
78aaa36a97SAlex Deucher * uvd_v5_0_ring_set_wptr - set write pointer
79aaa36a97SAlex Deucher *
80aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
81aaa36a97SAlex Deucher *
82aaa36a97SAlex Deucher * Commits the write pointer to the hardware
83aaa36a97SAlex Deucher */
uvd_v5_0_ring_set_wptr(struct amdgpu_ring * ring)84aaa36a97SAlex Deucher static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
85aaa36a97SAlex Deucher {
86aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev;
87aaa36a97SAlex Deucher
88536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
89aaa36a97SAlex Deucher }
90aaa36a97SAlex Deucher
uvd_v5_0_early_init(void * handle)915fc3aeebSyanyang1 static int uvd_v5_0_early_init(void *handle)
92aaa36a97SAlex Deucher {
935fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942bb795f5SJames Zhu adev->uvd.num_uvd_inst = 1;
955fc3aeebSyanyang1
96aaa36a97SAlex Deucher uvd_v5_0_set_ring_funcs(adev);
97aaa36a97SAlex Deucher uvd_v5_0_set_irq_funcs(adev);
98aaa36a97SAlex Deucher
99aaa36a97SAlex Deucher return 0;
100aaa36a97SAlex Deucher }
101aaa36a97SAlex Deucher
uvd_v5_0_sw_init(void * handle)1025fc3aeebSyanyang1 static int uvd_v5_0_sw_init(void *handle)
103aaa36a97SAlex Deucher {
104aaa36a97SAlex Deucher struct amdgpu_ring *ring;
1055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
106aaa36a97SAlex Deucher int r;
107aaa36a97SAlex Deucher
108aaa36a97SAlex Deucher /* UVD TRAP */
1091ffdeca6SChristian König r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
110aaa36a97SAlex Deucher if (r)
111aaa36a97SAlex Deucher return r;
112aaa36a97SAlex Deucher
113aaa36a97SAlex Deucher r = amdgpu_uvd_sw_init(adev);
114aaa36a97SAlex Deucher if (r)
115aaa36a97SAlex Deucher return r;
116aaa36a97SAlex Deucher
1172bb795f5SJames Zhu ring = &adev->uvd.inst->ring;
118aaa36a97SAlex Deucher sprintf(ring->name, "uvd");
1191c6d567bSNirmoy Das r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
120c107171bSChristian König AMDGPU_RING_PRIO_DEFAULT, NULL);
12133d5bd07SEmily Deng if (r)
12233d5bd07SEmily Deng return r;
12333d5bd07SEmily Deng
1243b34c14fSChris Wilson r = amdgpu_uvd_resume(adev);
1253b34c14fSChris Wilson if (r)
1263b34c14fSChris Wilson return r;
1273b34c14fSChris Wilson
128aaa36a97SAlex Deucher return r;
129aaa36a97SAlex Deucher }
130aaa36a97SAlex Deucher
uvd_v5_0_sw_fini(void * handle)1315fc3aeebSyanyang1 static int uvd_v5_0_sw_fini(void *handle)
132aaa36a97SAlex Deucher {
133aaa36a97SAlex Deucher int r;
1345fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
135aaa36a97SAlex Deucher
136aaa36a97SAlex Deucher r = amdgpu_uvd_suspend(adev);
137aaa36a97SAlex Deucher if (r)
138aaa36a97SAlex Deucher return r;
139aaa36a97SAlex Deucher
14050237287SRex Zhu return amdgpu_uvd_sw_fini(adev);
141aaa36a97SAlex Deucher }
142aaa36a97SAlex Deucher
143aaa36a97SAlex Deucher /**
144aaa36a97SAlex Deucher * uvd_v5_0_hw_init - start and test UVD block
145aaa36a97SAlex Deucher *
146c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer
147aaa36a97SAlex Deucher *
148aaa36a97SAlex Deucher * Initialize the hardware, boot up the VCPU and do some testing
149aaa36a97SAlex Deucher */
uvd_v5_0_hw_init(void * handle)1505fc3aeebSyanyang1 static int uvd_v5_0_hw_init(void *handle)
151aaa36a97SAlex Deucher {
1525fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1532bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring;
154aaa36a97SAlex Deucher uint32_t tmp;
155aaa36a97SAlex Deucher int r;
156aaa36a97SAlex Deucher
157e3e672e6SRex Zhu amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
158e3e672e6SRex Zhu uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
159e3e672e6SRex Zhu uvd_v5_0_enable_mgcg(adev, true);
160aaa36a97SAlex Deucher
161c66ed765SAndrey Grodzovsky r = amdgpu_ring_test_helper(ring);
162c66ed765SAndrey Grodzovsky if (r)
163aaa36a97SAlex Deucher goto done;
164aaa36a97SAlex Deucher
165a27de35cSChristian König r = amdgpu_ring_alloc(ring, 10);
166aaa36a97SAlex Deucher if (r) {
167aaa36a97SAlex Deucher DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
168aaa36a97SAlex Deucher goto done;
169aaa36a97SAlex Deucher }
170aaa36a97SAlex Deucher
171aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
172aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp);
173aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF);
174aaa36a97SAlex Deucher
175aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
176aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp);
177aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF);
178aaa36a97SAlex Deucher
179aaa36a97SAlex Deucher tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
180aaa36a97SAlex Deucher amdgpu_ring_write(ring, tmp);
181aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xFFFFF);
182aaa36a97SAlex Deucher
183aaa36a97SAlex Deucher /* Clear timeout status bits */
184aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
185aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0x8);
186aaa36a97SAlex Deucher
187aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
188aaa36a97SAlex Deucher amdgpu_ring_write(ring, 3);
189aaa36a97SAlex Deucher
190a27de35cSChristian König amdgpu_ring_commit(ring);
191e3e672e6SRex Zhu
192aaa36a97SAlex Deucher done:
193aaa36a97SAlex Deucher if (!r)
194aaa36a97SAlex Deucher DRM_INFO("UVD initialized successfully.\n");
195aaa36a97SAlex Deucher
196aaa36a97SAlex Deucher return r;
197e3e672e6SRex Zhu
198aaa36a97SAlex Deucher }
199aaa36a97SAlex Deucher
200aaa36a97SAlex Deucher /**
201aaa36a97SAlex Deucher * uvd_v5_0_hw_fini - stop the hardware block
202aaa36a97SAlex Deucher *
203c890ace5SLee Jones * @handle: handle used to pass amdgpu_device pointer
204aaa36a97SAlex Deucher *
205aaa36a97SAlex Deucher * Stop the UVD block, mark ring as not ready any more
206aaa36a97SAlex Deucher */
uvd_v5_0_hw_fini(void * handle)2075fc3aeebSyanyang1 static int uvd_v5_0_hw_fini(void *handle)
208aaa36a97SAlex Deucher {
2095fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
210aaa36a97SAlex Deucher
211d82e2c24SAndrey Grodzovsky cancel_delayed_work_sync(&adev->uvd.idle_work);
212d82e2c24SAndrey Grodzovsky
213d82e2c24SAndrey Grodzovsky if (RREG32(mmUVD_STATUS) != 0)
214d82e2c24SAndrey Grodzovsky uvd_v5_0_stop(adev);
215d82e2c24SAndrey Grodzovsky
216d82e2c24SAndrey Grodzovsky return 0;
217d82e2c24SAndrey Grodzovsky }
218d82e2c24SAndrey Grodzovsky
uvd_v5_0_prepare_suspend(void * handle)219db998890SMario Limonciello static int uvd_v5_0_prepare_suspend(void *handle)
220db998890SMario Limonciello {
221db998890SMario Limonciello struct amdgpu_device *adev = (struct amdgpu_device *)handle;
222db998890SMario Limonciello
223db998890SMario Limonciello return amdgpu_uvd_prepare_suspend(adev);
224db998890SMario Limonciello }
225db998890SMario Limonciello
uvd_v5_0_suspend(void * handle)226d82e2c24SAndrey Grodzovsky static int uvd_v5_0_suspend(void *handle)
227d82e2c24SAndrey Grodzovsky {
228d82e2c24SAndrey Grodzovsky int r;
229d82e2c24SAndrey Grodzovsky struct amdgpu_device *adev = (struct amdgpu_device *)handle;
230d82e2c24SAndrey Grodzovsky
231859e4659SEvan Quan /*
232859e4659SEvan Quan * Proper cleanups before halting the HW engine:
233859e4659SEvan Quan * - cancel the delayed idle work
234859e4659SEvan Quan * - enable powergating
235859e4659SEvan Quan * - enable clockgating
236859e4659SEvan Quan * - disable dpm
237859e4659SEvan Quan *
238859e4659SEvan Quan * TODO: to align with the VCN implementation, move the
239859e4659SEvan Quan * jobs for clockgating/powergating/dpm setting to
240859e4659SEvan Quan * ->set_powergating_state().
241859e4659SEvan Quan */
242859e4659SEvan Quan cancel_delayed_work_sync(&adev->uvd.idle_work);
243859e4659SEvan Quan
244859e4659SEvan Quan if (adev->pm.dpm_enabled) {
245859e4659SEvan Quan amdgpu_dpm_enable_uvd(adev, false);
246859e4659SEvan Quan } else {
247859e4659SEvan Quan amdgpu_asic_set_uvd_clocks(adev, 0, 0);
248859e4659SEvan Quan /* shutdown the UVD block */
249859e4659SEvan Quan amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
250859e4659SEvan Quan AMD_PG_STATE_GATE);
251859e4659SEvan Quan amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
252859e4659SEvan Quan AMD_CG_STATE_GATE);
253859e4659SEvan Quan }
254859e4659SEvan Quan
2553f99dd81SLeo Liu r = uvd_v5_0_hw_fini(adev);
256aaa36a97SAlex Deucher if (r)
257aaa36a97SAlex Deucher return r;
258aaa36a97SAlex Deucher
25950237287SRex Zhu return amdgpu_uvd_suspend(adev);
260aaa36a97SAlex Deucher }
261aaa36a97SAlex Deucher
uvd_v5_0_resume(void * handle)2625fc3aeebSyanyang1 static int uvd_v5_0_resume(void *handle)
263aaa36a97SAlex Deucher {
264aaa36a97SAlex Deucher int r;
2655fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
266aaa36a97SAlex Deucher
267aaa36a97SAlex Deucher r = amdgpu_uvd_resume(adev);
268aaa36a97SAlex Deucher if (r)
269aaa36a97SAlex Deucher return r;
270aaa36a97SAlex Deucher
27150237287SRex Zhu return uvd_v5_0_hw_init(adev);
272aaa36a97SAlex Deucher }
273aaa36a97SAlex Deucher
274aaa36a97SAlex Deucher /**
275aaa36a97SAlex Deucher * uvd_v5_0_mc_resume - memory controller programming
276aaa36a97SAlex Deucher *
277aaa36a97SAlex Deucher * @adev: amdgpu_device pointer
278aaa36a97SAlex Deucher *
279aaa36a97SAlex Deucher * Let the UVD memory controller know it's offsets
280aaa36a97SAlex Deucher */
uvd_v5_0_mc_resume(struct amdgpu_device * adev)281aaa36a97SAlex Deucher static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
282aaa36a97SAlex Deucher {
283aaa36a97SAlex Deucher uint64_t offset;
284aaa36a97SAlex Deucher uint32_t size;
285aaa36a97SAlex Deucher
286f349f772SBernard Zhao /* program memory controller bits 0-27 */
287aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
2882bb795f5SJames Zhu lower_32_bits(adev->uvd.inst->gpu_addr));
289aaa36a97SAlex Deucher WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
2902bb795f5SJames Zhu upper_32_bits(adev->uvd.inst->gpu_addr));
291aaa36a97SAlex Deucher
292aaa36a97SAlex Deucher offset = AMDGPU_UVD_FIRMWARE_OFFSET;
293c1fe75c9SPiotr Redlewski size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
294aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
295aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
296aaa36a97SAlex Deucher
297aaa36a97SAlex Deucher offset += size;
298c0365541SArindam Nath size = AMDGPU_UVD_HEAP_SIZE;
299aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
300aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
301aaa36a97SAlex Deucher
302aaa36a97SAlex Deucher offset += size;
303c0365541SArindam Nath size = AMDGPU_UVD_STACK_SIZE +
304c0365541SArindam Nath (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
305aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
306aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
307549300ceSAlex Deucher
308549300ceSAlex Deucher WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
309549300ceSAlex Deucher WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
310549300ceSAlex Deucher WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
311aaa36a97SAlex Deucher }
312aaa36a97SAlex Deucher
313aaa36a97SAlex Deucher /**
314aaa36a97SAlex Deucher * uvd_v5_0_start - start UVD block
315aaa36a97SAlex Deucher *
316aaa36a97SAlex Deucher * @adev: amdgpu_device pointer
317aaa36a97SAlex Deucher *
318aaa36a97SAlex Deucher * Setup and start the UVD block
319aaa36a97SAlex Deucher */
uvd_v5_0_start(struct amdgpu_device * adev)320aaa36a97SAlex Deucher static int uvd_v5_0_start(struct amdgpu_device *adev)
321aaa36a97SAlex Deucher {
3222bb795f5SJames Zhu struct amdgpu_ring *ring = &adev->uvd.inst->ring;
323aaa36a97SAlex Deucher uint32_t rb_bufsz, tmp;
324aaa36a97SAlex Deucher uint32_t lmi_swap_cntl;
325aaa36a97SAlex Deucher uint32_t mp_swap_cntl;
326aaa36a97SAlex Deucher int i, j, r;
327aaa36a97SAlex Deucher
328aaa36a97SAlex Deucher /*disable DPG */
329aaa36a97SAlex Deucher WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
330aaa36a97SAlex Deucher
331aaa36a97SAlex Deucher /* disable byte swapping */
332aaa36a97SAlex Deucher lmi_swap_cntl = 0;
333aaa36a97SAlex Deucher mp_swap_cntl = 0;
334aaa36a97SAlex Deucher
335aaa36a97SAlex Deucher uvd_v5_0_mc_resume(adev);
336aaa36a97SAlex Deucher
337aaa36a97SAlex Deucher /* disable interupt */
338aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
339aaa36a97SAlex Deucher
340aaa36a97SAlex Deucher /* stall UMC and register bus before resetting VCPU */
341aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
342aaa36a97SAlex Deucher mdelay(1);
343aaa36a97SAlex Deucher
344aaa36a97SAlex Deucher /* put LMI, VCPU, RBC etc... into reset */
345aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
346aaa36a97SAlex Deucher UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
347aaa36a97SAlex Deucher UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
348aaa36a97SAlex Deucher UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
349aaa36a97SAlex Deucher UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
350aaa36a97SAlex Deucher mdelay(5);
351aaa36a97SAlex Deucher
352aaa36a97SAlex Deucher /* take UVD block out of reset */
353aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
354aaa36a97SAlex Deucher mdelay(5);
355aaa36a97SAlex Deucher
356aaa36a97SAlex Deucher /* initialize UVD memory controller */
357aaa36a97SAlex Deucher WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
358aaa36a97SAlex Deucher (1 << 21) | (1 << 9) | (1 << 20));
359aaa36a97SAlex Deucher
360aaa36a97SAlex Deucher #ifdef __BIG_ENDIAN
361aaa36a97SAlex Deucher /* swap (8 in 32) RB and IB */
362aaa36a97SAlex Deucher lmi_swap_cntl = 0xa;
363aaa36a97SAlex Deucher mp_swap_cntl = 0;
364aaa36a97SAlex Deucher #endif
365aaa36a97SAlex Deucher WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
366aaa36a97SAlex Deucher WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
367aaa36a97SAlex Deucher
368aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
369aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
370aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
371aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
372aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_ALU, 0);
373aaa36a97SAlex Deucher WREG32(mmUVD_MPC_SET_MUX, 0x88);
374aaa36a97SAlex Deucher
375aaa36a97SAlex Deucher /* take all subblocks out of reset, except VCPU */
376aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
377aaa36a97SAlex Deucher mdelay(5);
378aaa36a97SAlex Deucher
379aaa36a97SAlex Deucher /* enable VCPU clock */
380aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 1 << 9);
381aaa36a97SAlex Deucher
382aaa36a97SAlex Deucher /* enable UMC */
383aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
384aaa36a97SAlex Deucher
385aaa36a97SAlex Deucher /* boot up the VCPU */
386aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, 0);
387aaa36a97SAlex Deucher mdelay(10);
388aaa36a97SAlex Deucher
389aaa36a97SAlex Deucher for (i = 0; i < 10; ++i) {
390aaa36a97SAlex Deucher uint32_t status;
391aaa36a97SAlex Deucher for (j = 0; j < 100; ++j) {
392aaa36a97SAlex Deucher status = RREG32(mmUVD_STATUS);
393aaa36a97SAlex Deucher if (status & 2)
394aaa36a97SAlex Deucher break;
395aaa36a97SAlex Deucher mdelay(10);
396aaa36a97SAlex Deucher }
397aaa36a97SAlex Deucher r = 0;
398aaa36a97SAlex Deucher if (status & 2)
399aaa36a97SAlex Deucher break;
400aaa36a97SAlex Deucher
401aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
402aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
403aaa36a97SAlex Deucher ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
404aaa36a97SAlex Deucher mdelay(10);
405aaa36a97SAlex Deucher WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
406aaa36a97SAlex Deucher mdelay(10);
407aaa36a97SAlex Deucher r = -1;
408aaa36a97SAlex Deucher }
409aaa36a97SAlex Deucher
410aaa36a97SAlex Deucher if (r) {
411aaa36a97SAlex Deucher DRM_ERROR("UVD not responding, giving up!!!\n");
412aaa36a97SAlex Deucher return r;
413aaa36a97SAlex Deucher }
414aaa36a97SAlex Deucher /* enable master interrupt */
415aaa36a97SAlex Deucher WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
416aaa36a97SAlex Deucher
417aaa36a97SAlex Deucher /* clear the bit 4 of UVD_STATUS */
418aaa36a97SAlex Deucher WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
419aaa36a97SAlex Deucher
420aaa36a97SAlex Deucher rb_bufsz = order_base_2(ring->ring_size);
421aaa36a97SAlex Deucher tmp = 0;
422aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
423aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
424aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
425aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
426aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
427aaa36a97SAlex Deucher tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
428aaa36a97SAlex Deucher /* force RBC into idle state */
429aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, tmp);
430aaa36a97SAlex Deucher
431aaa36a97SAlex Deucher /* set the write pointer delay */
432aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
433aaa36a97SAlex Deucher
434aaa36a97SAlex Deucher /* set the wb address */
435aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
436aaa36a97SAlex Deucher
437f349f772SBernard Zhao /* program the RB_BASE for ring buffer */
438aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
439aaa36a97SAlex Deucher lower_32_bits(ring->gpu_addr));
440aaa36a97SAlex Deucher WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
441aaa36a97SAlex Deucher upper_32_bits(ring->gpu_addr));
442aaa36a97SAlex Deucher
443aaa36a97SAlex Deucher /* Initialize the ring buffer's read and write pointers */
444aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_RPTR, 0);
445aaa36a97SAlex Deucher
446aaa36a97SAlex Deucher ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
447536fbf94SKen Wang WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
448aaa36a97SAlex Deucher
449aaa36a97SAlex Deucher WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
450aaa36a97SAlex Deucher
451aaa36a97SAlex Deucher return 0;
452aaa36a97SAlex Deucher }
453aaa36a97SAlex Deucher
454aaa36a97SAlex Deucher /**
455aaa36a97SAlex Deucher * uvd_v5_0_stop - stop UVD block
456aaa36a97SAlex Deucher *
457aaa36a97SAlex Deucher * @adev: amdgpu_device pointer
458aaa36a97SAlex Deucher *
459aaa36a97SAlex Deucher * stop the UVD block
460aaa36a97SAlex Deucher */
uvd_v5_0_stop(struct amdgpu_device * adev)461aaa36a97SAlex Deucher static void uvd_v5_0_stop(struct amdgpu_device *adev)
462aaa36a97SAlex Deucher {
463aaa36a97SAlex Deucher /* force RBC into idle state */
464aaa36a97SAlex Deucher WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
465aaa36a97SAlex Deucher
466aaa36a97SAlex Deucher /* Stall UMC and register bus before resetting VCPU */
467aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
468aaa36a97SAlex Deucher mdelay(1);
469aaa36a97SAlex Deucher
470aaa36a97SAlex Deucher /* put VCPU into reset */
471aaa36a97SAlex Deucher WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
472aaa36a97SAlex Deucher mdelay(5);
473aaa36a97SAlex Deucher
474aaa36a97SAlex Deucher /* disable VCPU clock */
475aaa36a97SAlex Deucher WREG32(mmUVD_VCPU_CNTL, 0x0);
476aaa36a97SAlex Deucher
477aaa36a97SAlex Deucher /* Unstall UMC and register bus */
478aaa36a97SAlex Deucher WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
479e3e672e6SRex Zhu
480e3e672e6SRex Zhu WREG32(mmUVD_STATUS, 0);
481aaa36a97SAlex Deucher }
482aaa36a97SAlex Deucher
483aaa36a97SAlex Deucher /**
484aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_fence - emit an fence & trap command
485aaa36a97SAlex Deucher *
486aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
487c890ace5SLee Jones * @addr: address
488c890ace5SLee Jones * @seq: sequence number
489c890ace5SLee Jones * @flags: fence related flags
490aaa36a97SAlex Deucher *
491aaa36a97SAlex Deucher * Write a fence and a trap command to the ring.
492aaa36a97SAlex Deucher */
uvd_v5_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)493aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
494890ee23fSChunming Zhou unsigned flags)
495aaa36a97SAlex Deucher {
496890ee23fSChunming Zhou WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
497aaa36a97SAlex Deucher
498aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
499aaa36a97SAlex Deucher amdgpu_ring_write(ring, seq);
500aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
501aaa36a97SAlex Deucher amdgpu_ring_write(ring, addr & 0xffffffff);
502aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
503aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
504aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
505aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0);
506aaa36a97SAlex Deucher
507aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
508aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0);
509aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
510aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0);
511aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
512aaa36a97SAlex Deucher amdgpu_ring_write(ring, 2);
513aaa36a97SAlex Deucher }
514aaa36a97SAlex Deucher
515aaa36a97SAlex Deucher /**
516aaa36a97SAlex Deucher * uvd_v5_0_ring_test_ring - register write test
517aaa36a97SAlex Deucher *
518aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
519aaa36a97SAlex Deucher *
520aaa36a97SAlex Deucher * Test if we can successfully write to the context register
521aaa36a97SAlex Deucher */
uvd_v5_0_ring_test_ring(struct amdgpu_ring * ring)522aaa36a97SAlex Deucher static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
523aaa36a97SAlex Deucher {
524aaa36a97SAlex Deucher struct amdgpu_device *adev = ring->adev;
525aaa36a97SAlex Deucher uint32_t tmp = 0;
526aaa36a97SAlex Deucher unsigned i;
527aaa36a97SAlex Deucher int r;
528aaa36a97SAlex Deucher
529aaa36a97SAlex Deucher WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
530a27de35cSChristian König r = amdgpu_ring_alloc(ring, 3);
531dc9eeff8SChristian König if (r)
532aaa36a97SAlex Deucher return r;
533aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
534aaa36a97SAlex Deucher amdgpu_ring_write(ring, 0xDEADBEEF);
535a27de35cSChristian König amdgpu_ring_commit(ring);
536aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) {
537aaa36a97SAlex Deucher tmp = RREG32(mmUVD_CONTEXT_ID);
538aaa36a97SAlex Deucher if (tmp == 0xDEADBEEF)
539aaa36a97SAlex Deucher break;
540c366be54SSam Ravnborg udelay(1);
541aaa36a97SAlex Deucher }
542aaa36a97SAlex Deucher
543dc9eeff8SChristian König if (i >= adev->usec_timeout)
544dc9eeff8SChristian König r = -ETIMEDOUT;
545dc9eeff8SChristian König
546aaa36a97SAlex Deucher return r;
547aaa36a97SAlex Deucher }
548aaa36a97SAlex Deucher
549aaa36a97SAlex Deucher /**
550aaa36a97SAlex Deucher * uvd_v5_0_ring_emit_ib - execute indirect buffer
551aaa36a97SAlex Deucher *
552aaa36a97SAlex Deucher * @ring: amdgpu_ring pointer
553c890ace5SLee Jones * @job: job to retrieve vmid from
554aaa36a97SAlex Deucher * @ib: indirect buffer to execute
555c890ace5SLee Jones * @flags: unused
556aaa36a97SAlex Deucher *
557aaa36a97SAlex Deucher * Write ring commands to execute the indirect buffer
558aaa36a97SAlex Deucher */
uvd_v5_0_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)559aaa36a97SAlex Deucher static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
56034955e03SRex Zhu struct amdgpu_job *job,
561d88bf583SChristian König struct amdgpu_ib *ib,
562c4c905ecSJack Xiao uint32_t flags)
563aaa36a97SAlex Deucher {
564aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
565aaa36a97SAlex Deucher amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
566aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
567aaa36a97SAlex Deucher amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
568aaa36a97SAlex Deucher amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
569aaa36a97SAlex Deucher amdgpu_ring_write(ring, ib->length_dw);
570aaa36a97SAlex Deucher }
571aaa36a97SAlex Deucher
uvd_v5_0_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)5720232e306SLeo Liu static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
5730232e306SLeo Liu {
5740232e306SLeo Liu int i;
5750232e306SLeo Liu
5760232e306SLeo Liu WARN_ON(ring->wptr % 2 || count % 2);
5770232e306SLeo Liu
5780232e306SLeo Liu for (i = 0; i < count / 2; i++) {
5790232e306SLeo Liu amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
5800232e306SLeo Liu amdgpu_ring_write(ring, 0);
5810232e306SLeo Liu }
5820232e306SLeo Liu }
5830232e306SLeo Liu
uvd_v5_0_is_idle(void * handle)5845fc3aeebSyanyang1 static bool uvd_v5_0_is_idle(void *handle)
585aaa36a97SAlex Deucher {
5865fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5875fc3aeebSyanyang1
588aaa36a97SAlex Deucher return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
589aaa36a97SAlex Deucher }
590aaa36a97SAlex Deucher
uvd_v5_0_wait_for_idle(void * handle)5915fc3aeebSyanyang1 static int uvd_v5_0_wait_for_idle(void *handle)
592aaa36a97SAlex Deucher {
593aaa36a97SAlex Deucher unsigned i;
5945fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
595aaa36a97SAlex Deucher
596aaa36a97SAlex Deucher for (i = 0; i < adev->usec_timeout; i++) {
597aaa36a97SAlex Deucher if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
598aaa36a97SAlex Deucher return 0;
599aaa36a97SAlex Deucher }
600aaa36a97SAlex Deucher return -ETIMEDOUT;
601aaa36a97SAlex Deucher }
602aaa36a97SAlex Deucher
uvd_v5_0_soft_reset(void * handle)6035fc3aeebSyanyang1 static int uvd_v5_0_soft_reset(void *handle)
604aaa36a97SAlex Deucher {
6055fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6065fc3aeebSyanyang1
607aaa36a97SAlex Deucher uvd_v5_0_stop(adev);
608aaa36a97SAlex Deucher
609aaa36a97SAlex Deucher WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
610aaa36a97SAlex Deucher ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
611aaa36a97SAlex Deucher mdelay(5);
612aaa36a97SAlex Deucher
613aaa36a97SAlex Deucher return uvd_v5_0_start(adev);
614aaa36a97SAlex Deucher }
615aaa36a97SAlex Deucher
uvd_v5_0_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)616aaa36a97SAlex Deucher static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
617aaa36a97SAlex Deucher struct amdgpu_irq_src *source,
618aaa36a97SAlex Deucher unsigned type,
619aaa36a97SAlex Deucher enum amdgpu_interrupt_state state)
620aaa36a97SAlex Deucher {
621aaa36a97SAlex Deucher // TODO
622aaa36a97SAlex Deucher return 0;
623aaa36a97SAlex Deucher }
624aaa36a97SAlex Deucher
uvd_v5_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)625aaa36a97SAlex Deucher static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
626aaa36a97SAlex Deucher struct amdgpu_irq_src *source,
627aaa36a97SAlex Deucher struct amdgpu_iv_entry *entry)
628aaa36a97SAlex Deucher {
629aaa36a97SAlex Deucher DRM_DEBUG("IH: UVD TRAP\n");
6302bb795f5SJames Zhu amdgpu_fence_process(&adev->uvd.inst->ring);
631aaa36a97SAlex Deucher return 0;
632aaa36a97SAlex Deucher }
633aaa36a97SAlex Deucher
uvd_v5_0_enable_clock_gating(struct amdgpu_device * adev,bool enable)634809a6a62SRex Zhu static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
635be3ecca7STom St Denis {
636809a6a62SRex Zhu uint32_t data1, data3, suvd_flags;
637be3ecca7STom St Denis
638be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE);
639809a6a62SRex Zhu data3 = RREG32(mmUVD_CGC_GATE);
640be3ecca7STom St Denis
641be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
642be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK |
643be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK |
644be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK |
645be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK;
646be3ecca7STom St Denis
647809a6a62SRex Zhu if (enable) {
648809a6a62SRex Zhu data3 |= (UVD_CGC_GATE__SYS_MASK |
649809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MASK |
650809a6a62SRex Zhu UVD_CGC_GATE__MPEG2_MASK |
651809a6a62SRex Zhu UVD_CGC_GATE__RBC_MASK |
652809a6a62SRex Zhu UVD_CGC_GATE__LMI_MC_MASK |
653809a6a62SRex Zhu UVD_CGC_GATE__IDCT_MASK |
654809a6a62SRex Zhu UVD_CGC_GATE__MPRD_MASK |
655809a6a62SRex Zhu UVD_CGC_GATE__MPC_MASK |
656809a6a62SRex Zhu UVD_CGC_GATE__LBSI_MASK |
657809a6a62SRex Zhu UVD_CGC_GATE__LRBBM_MASK |
658809a6a62SRex Zhu UVD_CGC_GATE__UDEC_RE_MASK |
659809a6a62SRex Zhu UVD_CGC_GATE__UDEC_CM_MASK |
660809a6a62SRex Zhu UVD_CGC_GATE__UDEC_IT_MASK |
661809a6a62SRex Zhu UVD_CGC_GATE__UDEC_DB_MASK |
662809a6a62SRex Zhu UVD_CGC_GATE__UDEC_MP_MASK |
663809a6a62SRex Zhu UVD_CGC_GATE__WCB_MASK |
664809a6a62SRex Zhu UVD_CGC_GATE__JPEG_MASK |
665809a6a62SRex Zhu UVD_CGC_GATE__SCPU_MASK);
6663c3a7e61SRex Zhu /* only in pg enabled, we can gate clock to vcpu*/
6673c3a7e61SRex Zhu if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
6683c3a7e61SRex Zhu data3 |= UVD_CGC_GATE__VCPU_MASK;
669809a6a62SRex Zhu data3 &= ~UVD_CGC_GATE__REGS_MASK;
670809a6a62SRex Zhu data1 |= suvd_flags;
671809a6a62SRex Zhu } else {
672809a6a62SRex Zhu data3 = 0;
673809a6a62SRex Zhu data1 = 0;
674809a6a62SRex Zhu }
675809a6a62SRex Zhu
676809a6a62SRex Zhu WREG32(mmUVD_SUVD_CGC_GATE, data1);
677809a6a62SRex Zhu WREG32(mmUVD_CGC_GATE, data3);
678809a6a62SRex Zhu }
679809a6a62SRex Zhu
uvd_v5_0_set_sw_clock_gating(struct amdgpu_device * adev)680809a6a62SRex Zhu static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
681809a6a62SRex Zhu {
682809a6a62SRex Zhu uint32_t data, data2;
683809a6a62SRex Zhu
684809a6a62SRex Zhu data = RREG32(mmUVD_CGC_CTRL);
685809a6a62SRex Zhu data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
686809a6a62SRex Zhu
687809a6a62SRex Zhu
688809a6a62SRex Zhu data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
689809a6a62SRex Zhu UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
690809a6a62SRex Zhu
691809a6a62SRex Zhu
692be3ecca7STom St Denis data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
693be3ecca7STom St Denis (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
694be3ecca7STom St Denis (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
695be3ecca7STom St Denis
696be3ecca7STom St Denis data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
697be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
698be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
699be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
700be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
701be3ecca7STom St Denis UVD_CGC_CTRL__SYS_MODE_MASK |
702be3ecca7STom St Denis UVD_CGC_CTRL__UDEC_MODE_MASK |
703be3ecca7STom St Denis UVD_CGC_CTRL__MPEG2_MODE_MASK |
704be3ecca7STom St Denis UVD_CGC_CTRL__REGS_MODE_MASK |
705be3ecca7STom St Denis UVD_CGC_CTRL__RBC_MODE_MASK |
706be3ecca7STom St Denis UVD_CGC_CTRL__LMI_MC_MODE_MASK |
707be3ecca7STom St Denis UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
708be3ecca7STom St Denis UVD_CGC_CTRL__IDCT_MODE_MASK |
709be3ecca7STom St Denis UVD_CGC_CTRL__MPRD_MODE_MASK |
710be3ecca7STom St Denis UVD_CGC_CTRL__MPC_MODE_MASK |
711be3ecca7STom St Denis UVD_CGC_CTRL__LBSI_MODE_MASK |
712be3ecca7STom St Denis UVD_CGC_CTRL__LRBBM_MODE_MASK |
713be3ecca7STom St Denis UVD_CGC_CTRL__WCB_MODE_MASK |
714be3ecca7STom St Denis UVD_CGC_CTRL__VCPU_MODE_MASK |
715be3ecca7STom St Denis UVD_CGC_CTRL__JPEG_MODE_MASK |
716be3ecca7STom St Denis UVD_CGC_CTRL__SCPU_MODE_MASK);
717be3ecca7STom St Denis data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
718be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
719be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
720be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
721be3ecca7STom St Denis UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
722be3ecca7STom St Denis
723be3ecca7STom St Denis WREG32(mmUVD_CGC_CTRL, data);
724be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_CTRL, data2);
725be3ecca7STom St Denis }
726be3ecca7STom St Denis
727be3ecca7STom St Denis #if 0
728be3ecca7STom St Denis static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
729be3ecca7STom St Denis {
730be3ecca7STom St Denis uint32_t data, data1, cgc_flags, suvd_flags;
731be3ecca7STom St Denis
732be3ecca7STom St Denis data = RREG32(mmUVD_CGC_GATE);
733be3ecca7STom St Denis data1 = RREG32(mmUVD_SUVD_CGC_GATE);
734be3ecca7STom St Denis
735be3ecca7STom St Denis cgc_flags = UVD_CGC_GATE__SYS_MASK |
736be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MASK |
737be3ecca7STom St Denis UVD_CGC_GATE__MPEG2_MASK |
738be3ecca7STom St Denis UVD_CGC_GATE__RBC_MASK |
739be3ecca7STom St Denis UVD_CGC_GATE__LMI_MC_MASK |
740be3ecca7STom St Denis UVD_CGC_GATE__IDCT_MASK |
741be3ecca7STom St Denis UVD_CGC_GATE__MPRD_MASK |
742be3ecca7STom St Denis UVD_CGC_GATE__MPC_MASK |
743be3ecca7STom St Denis UVD_CGC_GATE__LBSI_MASK |
744be3ecca7STom St Denis UVD_CGC_GATE__LRBBM_MASK |
745be3ecca7STom St Denis UVD_CGC_GATE__UDEC_RE_MASK |
746be3ecca7STom St Denis UVD_CGC_GATE__UDEC_CM_MASK |
747be3ecca7STom St Denis UVD_CGC_GATE__UDEC_IT_MASK |
748be3ecca7STom St Denis UVD_CGC_GATE__UDEC_DB_MASK |
749be3ecca7STom St Denis UVD_CGC_GATE__UDEC_MP_MASK |
750be3ecca7STom St Denis UVD_CGC_GATE__WCB_MASK |
751be3ecca7STom St Denis UVD_CGC_GATE__VCPU_MASK |
752be3ecca7STom St Denis UVD_CGC_GATE__SCPU_MASK;
753be3ecca7STom St Denis
754be3ecca7STom St Denis suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
755be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SIT_MASK |
756be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SMP_MASK |
757be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SCM_MASK |
758be3ecca7STom St Denis UVD_SUVD_CGC_GATE__SDB_MASK;
759be3ecca7STom St Denis
760be3ecca7STom St Denis data |= cgc_flags;
761be3ecca7STom St Denis data1 |= suvd_flags;
762be3ecca7STom St Denis
763be3ecca7STom St Denis WREG32(mmUVD_CGC_GATE, data);
764be3ecca7STom St Denis WREG32(mmUVD_SUVD_CGC_GATE, data1);
765be3ecca7STom St Denis }
766be3ecca7STom St Denis #endif
767be3ecca7STom St Denis
uvd_v5_0_enable_mgcg(struct amdgpu_device * adev,bool enable)768809a6a62SRex Zhu static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
769809a6a62SRex Zhu bool enable)
770809a6a62SRex Zhu {
771809a6a62SRex Zhu u32 orig, data;
772809a6a62SRex Zhu
773809a6a62SRex Zhu if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
774809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
775809a6a62SRex Zhu data |= 0xfff;
776809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
777809a6a62SRex Zhu
778809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL);
779809a6a62SRex Zhu data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
780809a6a62SRex Zhu if (orig != data)
781809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data);
782809a6a62SRex Zhu } else {
783809a6a62SRex Zhu data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
784809a6a62SRex Zhu data &= ~0xfff;
785809a6a62SRex Zhu WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
786809a6a62SRex Zhu
787809a6a62SRex Zhu orig = data = RREG32(mmUVD_CGC_CTRL);
788809a6a62SRex Zhu data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
789809a6a62SRex Zhu if (orig != data)
790809a6a62SRex Zhu WREG32(mmUVD_CGC_CTRL, data);
791809a6a62SRex Zhu }
792809a6a62SRex Zhu }
7934be5097cSRex Zhu
uvd_v5_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)7945fc3aeebSyanyang1 static int uvd_v5_0_set_clockgating_state(void *handle,
7955fc3aeebSyanyang1 enum amd_clockgating_state state)
796aaa36a97SAlex Deucher {
79735e5912dSAlex Deucher struct amdgpu_device *adev = (struct amdgpu_device *)handle;
798a9d4fe2fSNirmoy Das bool enable = (state == AMD_CG_STATE_GATE);
79935e5912dSAlex Deucher
800be3ecca7STom St Denis if (enable) {
801be3ecca7STom St Denis /* wait for STATUS to clear */
802be3ecca7STom St Denis if (uvd_v5_0_wait_for_idle(handle))
803be3ecca7STom St Denis return -EBUSY;
804809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, true);
805be3ecca7STom St Denis
806be3ecca7STom St Denis /* enable HW gates because UVD is idle */
807be3ecca7STom St Denis /* uvd_v5_0_set_hw_clock_gating(adev); */
808809a6a62SRex Zhu } else {
809809a6a62SRex Zhu uvd_v5_0_enable_clock_gating(adev, false);
810be3ecca7STom St Denis }
811be3ecca7STom St Denis
812809a6a62SRex Zhu uvd_v5_0_set_sw_clock_gating(adev);
813aaa36a97SAlex Deucher return 0;
814aaa36a97SAlex Deucher }
815aaa36a97SAlex Deucher
uvd_v5_0_set_powergating_state(void * handle,enum amd_powergating_state state)8165fc3aeebSyanyang1 static int uvd_v5_0_set_powergating_state(void *handle,
8175fc3aeebSyanyang1 enum amd_powergating_state state)
818aaa36a97SAlex Deucher {
819aaa36a97SAlex Deucher /* This doesn't actually powergate the UVD block.
820aaa36a97SAlex Deucher * That's done in the dpm code via the SMC. This
821aaa36a97SAlex Deucher * just re-inits the block as necessary. The actual
822aaa36a97SAlex Deucher * gating still happens in the dpm code. We should
823aaa36a97SAlex Deucher * revisit this when there is a cleaner line between
824aaa36a97SAlex Deucher * the smc and the hw blocks
825aaa36a97SAlex Deucher */
8265fc3aeebSyanyang1 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
827c8781f56SHuang Rui int ret = 0;
8285fc3aeebSyanyang1
8295fc3aeebSyanyang1 if (state == AMD_PG_STATE_GATE) {
830aaa36a97SAlex Deucher uvd_v5_0_stop(adev);
831aaa36a97SAlex Deucher } else {
832c8781f56SHuang Rui ret = uvd_v5_0_start(adev);
833c8781f56SHuang Rui if (ret)
834c8781f56SHuang Rui goto out;
835aaa36a97SAlex Deucher }
836c8781f56SHuang Rui
837c8781f56SHuang Rui out:
838c8781f56SHuang Rui return ret;
839c8781f56SHuang Rui }
840c8781f56SHuang Rui
uvd_v5_0_get_clockgating_state(void * handle,u64 * flags)84125faeddcSEvan Quan static void uvd_v5_0_get_clockgating_state(void *handle, u64 *flags)
842c8781f56SHuang Rui {
843c8781f56SHuang Rui struct amdgpu_device *adev = (struct amdgpu_device *)handle;
844c8781f56SHuang Rui int data;
845c8781f56SHuang Rui
846c8781f56SHuang Rui mutex_lock(&adev->pm.mutex);
847c8781f56SHuang Rui
848254cd2e0SRex Zhu if (RREG32_SMC(ixCURRENT_PG_STATUS) &
849254cd2e0SRex Zhu CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
850c8781f56SHuang Rui DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
851c8781f56SHuang Rui goto out;
852c8781f56SHuang Rui }
853c8781f56SHuang Rui
854c8781f56SHuang Rui /* AMD_CG_SUPPORT_UVD_MGCG */
855c8781f56SHuang Rui data = RREG32(mmUVD_CGC_CTRL);
856c8781f56SHuang Rui if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
857c8781f56SHuang Rui *flags |= AMD_CG_SUPPORT_UVD_MGCG;
858c8781f56SHuang Rui
859c8781f56SHuang Rui out:
860c8781f56SHuang Rui mutex_unlock(&adev->pm.mutex);
861aaa36a97SAlex Deucher }
862aaa36a97SAlex Deucher
863a1255107SAlex Deucher static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
86488a907d6STom St Denis .name = "uvd_v5_0",
865aaa36a97SAlex Deucher .early_init = uvd_v5_0_early_init,
866aaa36a97SAlex Deucher .late_init = NULL,
867aaa36a97SAlex Deucher .sw_init = uvd_v5_0_sw_init,
868aaa36a97SAlex Deucher .sw_fini = uvd_v5_0_sw_fini,
869aaa36a97SAlex Deucher .hw_init = uvd_v5_0_hw_init,
870aaa36a97SAlex Deucher .hw_fini = uvd_v5_0_hw_fini,
871db998890SMario Limonciello .prepare_suspend = uvd_v5_0_prepare_suspend,
872aaa36a97SAlex Deucher .suspend = uvd_v5_0_suspend,
873aaa36a97SAlex Deucher .resume = uvd_v5_0_resume,
874aaa36a97SAlex Deucher .is_idle = uvd_v5_0_is_idle,
875aaa36a97SAlex Deucher .wait_for_idle = uvd_v5_0_wait_for_idle,
876aaa36a97SAlex Deucher .soft_reset = uvd_v5_0_soft_reset,
877aaa36a97SAlex Deucher .set_clockgating_state = uvd_v5_0_set_clockgating_state,
878aaa36a97SAlex Deucher .set_powergating_state = uvd_v5_0_set_powergating_state,
879c8781f56SHuang Rui .get_clockgating_state = uvd_v5_0_get_clockgating_state,
880e21d253bSSunil Khatri .dump_ip_state = NULL,
881*40356542SSunil Khatri .print_ip_state = NULL,
882aaa36a97SAlex Deucher };
883aaa36a97SAlex Deucher
884aaa36a97SAlex Deucher static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
88521cd942eSChristian König .type = AMDGPU_RING_TYPE_UVD,
88679887142SChristian König .align_mask = 0xf,
887536fbf94SKen Wang .support_64bit_ptrs = false,
8887ee250b1SLeo Liu .no_user_fence = true,
889aaa36a97SAlex Deucher .get_rptr = uvd_v5_0_ring_get_rptr,
890aaa36a97SAlex Deucher .get_wptr = uvd_v5_0_ring_get_wptr,
891aaa36a97SAlex Deucher .set_wptr = uvd_v5_0_ring_set_wptr,
892aaa36a97SAlex Deucher .parse_cs = amdgpu_uvd_ring_parse_cs,
893e12f3d7aSChristian König .emit_frame_size =
894e12f3d7aSChristian König 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */
895e12f3d7aSChristian König .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
896aaa36a97SAlex Deucher .emit_ib = uvd_v5_0_ring_emit_ib,
897aaa36a97SAlex Deucher .emit_fence = uvd_v5_0_ring_emit_fence,
898aaa36a97SAlex Deucher .test_ring = uvd_v5_0_ring_test_ring,
8998de190c9SChristian König .test_ib = amdgpu_uvd_ring_test_ib,
9000232e306SLeo Liu .insert_nop = uvd_v5_0_ring_insert_nop,
9019e5d5309SChristian König .pad_ib = amdgpu_ring_generic_pad_ib,
902c4120d55SChristian König .begin_use = amdgpu_uvd_ring_begin_use,
903c4120d55SChristian König .end_use = amdgpu_uvd_ring_end_use,
904aaa36a97SAlex Deucher };
905aaa36a97SAlex Deucher
uvd_v5_0_set_ring_funcs(struct amdgpu_device * adev)906aaa36a97SAlex Deucher static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
907aaa36a97SAlex Deucher {
9082bb795f5SJames Zhu adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs;
909aaa36a97SAlex Deucher }
910aaa36a97SAlex Deucher
911aaa36a97SAlex Deucher static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
912aaa36a97SAlex Deucher .set = uvd_v5_0_set_interrupt_state,
913aaa36a97SAlex Deucher .process = uvd_v5_0_process_interrupt,
914aaa36a97SAlex Deucher };
915aaa36a97SAlex Deucher
uvd_v5_0_set_irq_funcs(struct amdgpu_device * adev)916aaa36a97SAlex Deucher static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
917aaa36a97SAlex Deucher {
9182bb795f5SJames Zhu adev->uvd.inst->irq.num_types = 1;
9192bb795f5SJames Zhu adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs;
920aaa36a97SAlex Deucher }
921a1255107SAlex Deucher
922a1255107SAlex Deucher const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
923a1255107SAlex Deucher {
924a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_UVD,
925a1255107SAlex Deucher .major = 5,
926a1255107SAlex Deucher .minor = 0,
927a1255107SAlex Deucher .rev = 0,
928a1255107SAlex Deucher .funcs = &uvd_v5_0_ip_funcs,
929a1255107SAlex Deucher };
930