1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König <christian.koenig@amd.com> 23 */ 24 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_uvd.h" 29 #include "cikd.h" 30 31 #include "uvd/uvd_4_2_d.h" 32 #include "uvd/uvd_4_2_sh_mask.h" 33 34 #include "oss/oss_2_0_d.h" 35 #include "oss/oss_2_0_sh_mask.h" 36 37 #include "bif/bif_4_1_d.h" 38 39 #include "smu/smu_7_0_1_d.h" 40 #include "smu/smu_7_0_1_sh_mask.h" 41 42 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev); 43 static void uvd_v4_2_init_cg(struct amdgpu_device *adev); 44 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev); 45 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev); 46 static int uvd_v4_2_start(struct amdgpu_device *adev); 47 static void uvd_v4_2_stop(struct amdgpu_device *adev); 48 49 /** 50 * uvd_v4_2_ring_get_rptr - get read pointer 51 * 52 * @ring: amdgpu_ring pointer 53 * 54 * Returns the current hardware read pointer 55 */ 56 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring) 57 { 58 struct amdgpu_device *adev = ring->adev; 59 60 return RREG32(mmUVD_RBC_RB_RPTR); 61 } 62 63 /** 64 * uvd_v4_2_ring_get_wptr - get write pointer 65 * 66 * @ring: amdgpu_ring pointer 67 * 68 * Returns the current hardware write pointer 69 */ 70 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring) 71 { 72 struct amdgpu_device *adev = ring->adev; 73 74 return RREG32(mmUVD_RBC_RB_WPTR); 75 } 76 77 /** 78 * uvd_v4_2_ring_set_wptr - set write pointer 79 * 80 * @ring: amdgpu_ring pointer 81 * 82 * Commits the write pointer to the hardware 83 */ 84 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) 85 { 86 struct amdgpu_device *adev = ring->adev; 87 88 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 89 } 90 91 static int uvd_v4_2_early_init(void *handle) 92 { 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 95 uvd_v4_2_set_ring_funcs(adev); 96 uvd_v4_2_set_irq_funcs(adev); 97 98 return 0; 99 } 100 101 static int uvd_v4_2_sw_init(void *handle) 102 { 103 struct amdgpu_ring *ring; 104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 105 int r; 106 107 /* UVD TRAP */ 108 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq); 109 if (r) 110 return r; 111 112 r = amdgpu_uvd_sw_init(adev); 113 if (r) 114 return r; 115 116 r = amdgpu_uvd_resume(adev); 117 if (r) 118 return r; 119 120 ring = &adev->uvd.ring; 121 sprintf(ring->name, "uvd"); 122 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); 123 124 return r; 125 } 126 127 static int uvd_v4_2_sw_fini(void *handle) 128 { 129 int r; 130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 131 132 r = amdgpu_uvd_suspend(adev); 133 if (r) 134 return r; 135 136 r = amdgpu_uvd_sw_fini(adev); 137 if (r) 138 return r; 139 140 return r; 141 } 142 143 /** 144 * uvd_v4_2_hw_init - start and test UVD block 145 * 146 * @adev: amdgpu_device pointer 147 * 148 * Initialize the hardware, boot up the VCPU and do some testing 149 */ 150 static int uvd_v4_2_hw_init(void *handle) 151 { 152 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 153 struct amdgpu_ring *ring = &adev->uvd.ring; 154 uint32_t tmp; 155 int r; 156 157 /* raise clocks while booting up the VCPU */ 158 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 159 160 r = uvd_v4_2_start(adev); 161 if (r) 162 goto done; 163 164 ring->ready = true; 165 r = amdgpu_ring_test_ring(ring); 166 if (r) { 167 ring->ready = false; 168 goto done; 169 } 170 171 r = amdgpu_ring_alloc(ring, 10); 172 if (r) { 173 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 174 goto done; 175 } 176 177 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 178 amdgpu_ring_write(ring, tmp); 179 amdgpu_ring_write(ring, 0xFFFFF); 180 181 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 182 amdgpu_ring_write(ring, tmp); 183 amdgpu_ring_write(ring, 0xFFFFF); 184 185 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 186 amdgpu_ring_write(ring, tmp); 187 amdgpu_ring_write(ring, 0xFFFFF); 188 189 /* Clear timeout status bits */ 190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 191 amdgpu_ring_write(ring, 0x8); 192 193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 194 amdgpu_ring_write(ring, 3); 195 196 amdgpu_ring_commit(ring); 197 198 done: 199 /* lower clocks again */ 200 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 201 202 if (!r) 203 DRM_INFO("UVD initialized successfully.\n"); 204 205 return r; 206 } 207 208 /** 209 * uvd_v4_2_hw_fini - stop the hardware block 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Stop the UVD block, mark ring as not ready any more 214 */ 215 static int uvd_v4_2_hw_fini(void *handle) 216 { 217 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 218 struct amdgpu_ring *ring = &adev->uvd.ring; 219 220 uvd_v4_2_stop(adev); 221 ring->ready = false; 222 223 return 0; 224 } 225 226 static int uvd_v4_2_suspend(void *handle) 227 { 228 int r; 229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 230 231 r = uvd_v4_2_hw_fini(adev); 232 if (r) 233 return r; 234 235 r = amdgpu_uvd_suspend(adev); 236 if (r) 237 return r; 238 239 return r; 240 } 241 242 static int uvd_v4_2_resume(void *handle) 243 { 244 int r; 245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 246 247 r = amdgpu_uvd_resume(adev); 248 if (r) 249 return r; 250 251 r = uvd_v4_2_hw_init(adev); 252 if (r) 253 return r; 254 255 return r; 256 } 257 258 /** 259 * uvd_v4_2_start - start UVD block 260 * 261 * @adev: amdgpu_device pointer 262 * 263 * Setup and start the UVD block 264 */ 265 static int uvd_v4_2_start(struct amdgpu_device *adev) 266 { 267 struct amdgpu_ring *ring = &adev->uvd.ring; 268 uint32_t rb_bufsz; 269 int i, j, r; 270 271 /* disable byte swapping */ 272 u32 lmi_swap_cntl = 0; 273 u32 mp_swap_cntl = 0; 274 275 uvd_v4_2_mc_resume(adev); 276 277 /* disable clock gating */ 278 WREG32(mmUVD_CGC_GATE, 0); 279 280 /* disable interupt */ 281 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 282 283 /* Stall UMC and register bus before resetting VCPU */ 284 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 285 mdelay(1); 286 287 /* put LMI, VCPU, RBC etc... into reset */ 288 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 289 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 290 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 291 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 292 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 293 mdelay(5); 294 295 /* take UVD block out of reset */ 296 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 297 mdelay(5); 298 299 /* initialize UVD memory controller */ 300 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 301 (1 << 21) | (1 << 9) | (1 << 20)); 302 303 #ifdef __BIG_ENDIAN 304 /* swap (8 in 32) RB and IB */ 305 lmi_swap_cntl = 0xa; 306 mp_swap_cntl = 0; 307 #endif 308 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 309 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 310 311 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 312 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 313 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 314 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 315 WREG32(mmUVD_MPC_SET_ALU, 0); 316 WREG32(mmUVD_MPC_SET_MUX, 0x88); 317 318 /* take all subblocks out of reset, except VCPU */ 319 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 320 mdelay(5); 321 322 /* enable VCPU clock */ 323 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 324 325 /* enable UMC */ 326 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 327 328 /* boot up the VCPU */ 329 WREG32(mmUVD_SOFT_RESET, 0); 330 mdelay(10); 331 332 for (i = 0; i < 10; ++i) { 333 uint32_t status; 334 for (j = 0; j < 100; ++j) { 335 status = RREG32(mmUVD_STATUS); 336 if (status & 2) 337 break; 338 mdelay(10); 339 } 340 r = 0; 341 if (status & 2) 342 break; 343 344 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 345 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 346 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 347 mdelay(10); 348 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 349 mdelay(10); 350 r = -1; 351 } 352 353 if (r) { 354 DRM_ERROR("UVD not responding, giving up!!!\n"); 355 return r; 356 } 357 358 /* enable interupt */ 359 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); 360 361 /* force RBC into idle state */ 362 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 363 364 /* Set the write pointer delay */ 365 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 366 367 /* programm the 4GB memory segment for rptr and ring buffer */ 368 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 369 (0x7 << 16) | (0x1 << 31)); 370 371 /* Initialize the ring buffer's read and write pointers */ 372 WREG32(mmUVD_RBC_RB_RPTR, 0x0); 373 374 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 375 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr); 376 377 /* set the ring address */ 378 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr); 379 380 /* Set ring buffer size */ 381 rb_bufsz = order_base_2(ring->ring_size); 382 rb_bufsz = (0x1 << 8) | rb_bufsz; 383 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); 384 385 return 0; 386 } 387 388 /** 389 * uvd_v4_2_stop - stop UVD block 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * stop the UVD block 394 */ 395 static void uvd_v4_2_stop(struct amdgpu_device *adev) 396 { 397 /* force RBC into idle state */ 398 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 399 400 /* Stall UMC and register bus before resetting VCPU */ 401 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 402 mdelay(1); 403 404 /* put VCPU into reset */ 405 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 406 mdelay(5); 407 408 /* disable VCPU clock */ 409 WREG32(mmUVD_VCPU_CNTL, 0x0); 410 411 /* Unstall UMC and register bus */ 412 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 413 } 414 415 /** 416 * uvd_v4_2_ring_emit_fence - emit an fence & trap command 417 * 418 * @ring: amdgpu_ring pointer 419 * @fence: fence to emit 420 * 421 * Write a fence and a trap command to the ring. 422 */ 423 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 424 unsigned flags) 425 { 426 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 427 428 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 429 amdgpu_ring_write(ring, seq); 430 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 431 amdgpu_ring_write(ring, addr & 0xffffffff); 432 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 433 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 434 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 435 amdgpu_ring_write(ring, 0); 436 437 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 438 amdgpu_ring_write(ring, 0); 439 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 440 amdgpu_ring_write(ring, 0); 441 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 442 amdgpu_ring_write(ring, 2); 443 } 444 445 /** 446 * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush 447 * 448 * @ring: amdgpu_ring pointer 449 * 450 * Emits an hdp flush. 451 */ 452 static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) 453 { 454 amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 455 amdgpu_ring_write(ring, 0); 456 } 457 458 /** 459 * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate 460 * 461 * @ring: amdgpu_ring pointer 462 * 463 * Emits an hdp invalidate. 464 */ 465 static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 466 { 467 amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); 468 amdgpu_ring_write(ring, 1); 469 } 470 471 /** 472 * uvd_v4_2_ring_test_ring - register write test 473 * 474 * @ring: amdgpu_ring pointer 475 * 476 * Test if we can successfully write to the context register 477 */ 478 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring) 479 { 480 struct amdgpu_device *adev = ring->adev; 481 uint32_t tmp = 0; 482 unsigned i; 483 int r; 484 485 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 486 r = amdgpu_ring_alloc(ring, 3); 487 if (r) { 488 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 489 ring->idx, r); 490 return r; 491 } 492 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 493 amdgpu_ring_write(ring, 0xDEADBEEF); 494 amdgpu_ring_commit(ring); 495 for (i = 0; i < adev->usec_timeout; i++) { 496 tmp = RREG32(mmUVD_CONTEXT_ID); 497 if (tmp == 0xDEADBEEF) 498 break; 499 DRM_UDELAY(1); 500 } 501 502 if (i < adev->usec_timeout) { 503 DRM_INFO("ring test on %d succeeded in %d usecs\n", 504 ring->idx, i); 505 } else { 506 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 507 ring->idx, tmp); 508 r = -EINVAL; 509 } 510 return r; 511 } 512 513 /** 514 * uvd_v4_2_ring_emit_ib - execute indirect buffer 515 * 516 * @ring: amdgpu_ring pointer 517 * @ib: indirect buffer to execute 518 * 519 * Write ring commands to execute the indirect buffer 520 */ 521 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, 522 struct amdgpu_ib *ib, 523 unsigned vm_id, bool ctx_switch) 524 { 525 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0)); 526 amdgpu_ring_write(ring, ib->gpu_addr); 527 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 528 amdgpu_ring_write(ring, ib->length_dw); 529 } 530 531 /** 532 * uvd_v4_2_mc_resume - memory controller programming 533 * 534 * @adev: amdgpu_device pointer 535 * 536 * Let the UVD memory controller know it's offsets 537 */ 538 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev) 539 { 540 uint64_t addr; 541 uint32_t size; 542 543 /* programm the VCPU memory controller bits 0-27 */ 544 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; 545 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3; 546 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr); 547 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 548 549 addr += size; 550 size = AMDGPU_UVD_HEAP_SIZE >> 3; 551 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr); 552 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 553 554 addr += size; 555 size = (AMDGPU_UVD_STACK_SIZE + 556 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; 557 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr); 558 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 559 560 /* bits 28-31 */ 561 addr = (adev->uvd.gpu_addr >> 28) & 0xF; 562 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); 563 564 /* bits 32-39 */ 565 addr = (adev->uvd.gpu_addr >> 32) & 0xFF; 566 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); 567 568 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 569 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 570 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 571 572 uvd_v4_2_init_cg(adev); 573 } 574 575 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, 576 bool enable) 577 { 578 u32 orig, data; 579 580 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 581 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 582 data = 0xfff; 583 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 584 585 orig = data = RREG32(mmUVD_CGC_CTRL); 586 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 587 if (orig != data) 588 WREG32(mmUVD_CGC_CTRL, data); 589 } else { 590 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 591 data &= ~0xfff; 592 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 593 594 orig = data = RREG32(mmUVD_CGC_CTRL); 595 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 596 if (orig != data) 597 WREG32(mmUVD_CGC_CTRL, data); 598 } 599 } 600 601 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev, 602 bool sw_mode) 603 { 604 u32 tmp, tmp2; 605 606 tmp = RREG32(mmUVD_CGC_CTRL); 607 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 608 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 609 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | 610 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT); 611 612 if (sw_mode) { 613 tmp &= ~0x7ffff800; 614 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK | 615 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK | 616 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT); 617 } else { 618 tmp |= 0x7ffff800; 619 tmp2 = 0; 620 } 621 622 WREG32(mmUVD_CGC_CTRL, tmp); 623 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); 624 } 625 626 static void uvd_v4_2_init_cg(struct amdgpu_device *adev) 627 { 628 bool hw_mode = true; 629 630 if (hw_mode) { 631 uvd_v4_2_set_dcm(adev, false); 632 } else { 633 u32 tmp = RREG32(mmUVD_CGC_CTRL); 634 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 635 WREG32(mmUVD_CGC_CTRL, tmp); 636 } 637 } 638 639 static bool uvd_v4_2_is_idle(void *handle) 640 { 641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 642 643 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 644 } 645 646 static int uvd_v4_2_wait_for_idle(void *handle) 647 { 648 unsigned i; 649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 650 651 for (i = 0; i < adev->usec_timeout; i++) { 652 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 653 return 0; 654 } 655 return -ETIMEDOUT; 656 } 657 658 static int uvd_v4_2_soft_reset(void *handle) 659 { 660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 661 662 uvd_v4_2_stop(adev); 663 664 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 665 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 666 mdelay(5); 667 668 return uvd_v4_2_start(adev); 669 } 670 671 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 672 struct amdgpu_irq_src *source, 673 unsigned type, 674 enum amdgpu_interrupt_state state) 675 { 676 // TODO 677 return 0; 678 } 679 680 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev, 681 struct amdgpu_irq_src *source, 682 struct amdgpu_iv_entry *entry) 683 { 684 DRM_DEBUG("IH: UVD TRAP\n"); 685 amdgpu_fence_process(&adev->uvd.ring); 686 return 0; 687 } 688 689 static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 690 { 691 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 692 693 if (enable) 694 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 695 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 696 else 697 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 698 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 699 700 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 701 } 702 703 static int uvd_v4_2_set_clockgating_state(void *handle, 704 enum amd_clockgating_state state) 705 { 706 bool gate = false; 707 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 708 709 if (state == AMD_CG_STATE_GATE) 710 gate = true; 711 712 uvd_v5_0_set_bypass_mode(adev, gate); 713 714 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 715 return 0; 716 717 uvd_v4_2_enable_mgcg(adev, gate); 718 719 return 0; 720 } 721 722 static int uvd_v4_2_set_powergating_state(void *handle, 723 enum amd_powergating_state state) 724 { 725 /* This doesn't actually powergate the UVD block. 726 * That's done in the dpm code via the SMC. This 727 * just re-inits the block as necessary. The actual 728 * gating still happens in the dpm code. We should 729 * revisit this when there is a cleaner line between 730 * the smc and the hw blocks 731 */ 732 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 733 734 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 735 return 0; 736 737 if (state == AMD_PG_STATE_GATE) { 738 uvd_v4_2_stop(adev); 739 return 0; 740 } else { 741 return uvd_v4_2_start(adev); 742 } 743 } 744 745 static const struct amd_ip_funcs uvd_v4_2_ip_funcs = { 746 .name = "uvd_v4_2", 747 .early_init = uvd_v4_2_early_init, 748 .late_init = NULL, 749 .sw_init = uvd_v4_2_sw_init, 750 .sw_fini = uvd_v4_2_sw_fini, 751 .hw_init = uvd_v4_2_hw_init, 752 .hw_fini = uvd_v4_2_hw_fini, 753 .suspend = uvd_v4_2_suspend, 754 .resume = uvd_v4_2_resume, 755 .is_idle = uvd_v4_2_is_idle, 756 .wait_for_idle = uvd_v4_2_wait_for_idle, 757 .soft_reset = uvd_v4_2_soft_reset, 758 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 759 .set_powergating_state = uvd_v4_2_set_powergating_state, 760 }; 761 762 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { 763 .type = AMDGPU_RING_TYPE_UVD, 764 .align_mask = 0xf, 765 .nop = PACKET0(mmUVD_NO_OP, 0), 766 .get_rptr = uvd_v4_2_ring_get_rptr, 767 .get_wptr = uvd_v4_2_ring_get_wptr, 768 .set_wptr = uvd_v4_2_ring_set_wptr, 769 .parse_cs = amdgpu_uvd_ring_parse_cs, 770 .emit_frame_size = 771 2 + /* uvd_v4_2_ring_emit_hdp_flush */ 772 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ 773 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ 774 .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ 775 .emit_ib = uvd_v4_2_ring_emit_ib, 776 .emit_fence = uvd_v4_2_ring_emit_fence, 777 .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, 778 .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, 779 .test_ring = uvd_v4_2_ring_test_ring, 780 .test_ib = amdgpu_uvd_ring_test_ib, 781 .insert_nop = amdgpu_ring_insert_nop, 782 .pad_ib = amdgpu_ring_generic_pad_ib, 783 .begin_use = amdgpu_uvd_ring_begin_use, 784 .end_use = amdgpu_uvd_ring_end_use, 785 }; 786 787 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) 788 { 789 adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs; 790 } 791 792 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = { 793 .set = uvd_v4_2_set_interrupt_state, 794 .process = uvd_v4_2_process_interrupt, 795 }; 796 797 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev) 798 { 799 adev->uvd.irq.num_types = 1; 800 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs; 801 } 802 803 const struct amdgpu_ip_block_version uvd_v4_2_ip_block = 804 { 805 .type = AMD_IP_BLOCK_TYPE_UVD, 806 .major = 4, 807 .minor = 2, 808 .rev = 0, 809 .funcs = &uvd_v4_2_ip_funcs, 810 }; 811