1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __UMC_V12_0_H__ 24 #define __UMC_V12_0_H__ 25 26 #include "soc15_common.h" 27 #include "amdgpu.h" 28 29 /* one piece of normalized address is mapped to 8 pieces of physical address */ 30 #define UMC_V12_0_NA_MAP_PA_NUM 8 31 /* R13 bit shift should be considered, double the number */ 32 #define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2) 33 34 /* column bits in SOC physical address */ 35 #define UMC_V12_0_PA_C2_BIT 15 36 #define UMC_V12_0_PA_C3_BIT 16 37 #define UMC_V12_0_PA_C4_BIT 21 38 /* row bits in SOC physical address */ 39 #define UMC_V12_0_PA_R0_BIT 22 40 #define UMC_V12_0_PA_R10_BIT 32 41 #define UMC_V12_0_PA_R11_BIT 33 42 #define UMC_V12_0_PA_R12_BIT 34 43 #define UMC_V12_0_PA_R13_BIT 35 44 /* channel bit in SOC physical address */ 45 #define UMC_V12_0_PA_CH4_BIT 12 46 #define UMC_V12_0_PA_CH5_BIT 13 47 /* bank bit in SOC physical address */ 48 #define UMC_V12_0_PA_B0_BIT 19 49 #define UMC_V12_0_PA_B1_BIT 20 50 /* row bits in MCA address */ 51 #define UMC_V12_0_MA_R0_BIT 10 52 53 #define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \ 54 (((_ipid_lo) >> 12) & 0xF)) 55 #define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7) 56 57 #define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03) 58 59 #define MCA_IPID_2_UMC_CH(ipid) \ 60 (MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) 61 62 #define MCA_IPID_2_UMC_INST(ipid) \ 63 (MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo))) 64 65 #define MCA_IPID_2_SOCKET_ID(ipid) \ 66 (((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \ 67 (REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03)) 68 69 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); 70 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status); 71 72 extern struct amdgpu_umc_ras umc_v12_0_ras; 73 74 #endif 75