1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 #define MAX_ECC_NUM_PER_RETIREMENT 32 32 #define DELAYED_TIME_FOR_GPU_RESET 1000 //ms 33 34 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 35 uint32_t node_inst, 36 uint32_t umc_inst, 37 uint32_t ch_inst) 38 { 39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 40 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 41 42 umc_inst = index / 4; 43 ch_inst = index % 4; 44 45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 46 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 47 } 48 49 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 50 uint32_t node_inst, uint32_t umc_inst, 51 uint32_t ch_inst, void *data) 52 { 53 uint64_t odecc_err_cnt_addr; 54 uint64_t umc_reg_offset = 55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 56 57 odecc_err_cnt_addr = 58 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 59 60 /* clear error count */ 61 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 62 UMC_V12_0_CE_CNT_INIT); 63 64 return 0; 65 } 66 67 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 68 { 69 amdgpu_umc_loop_channels(adev, 70 umc_v12_0_reset_error_count_per_channel, NULL); 71 } 72 73 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 74 { 75 dev_dbg(adev->dev, 76 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", 77 mc_umc_status, 78 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), 79 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), 80 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), 81 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), 82 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), 83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) 84 ); 85 86 return (amdgpu_ras_is_poison_mode_supported(adev) && 87 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 88 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)); 89 } 90 91 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 92 { 93 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 94 return false; 95 96 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 97 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 98 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 100 } 101 102 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 103 { 104 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 105 return false; 106 107 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 108 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 109 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 110 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 111 /* Identify data parity error in replay mode */ 112 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 113 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 114 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 115 } 116 117 static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev, 118 uint64_t umc_reg_offset, 119 unsigned long *error_count, 120 check_error_type_func error_type_func) 121 { 122 uint64_t mc_umc_status; 123 uint64_t mc_umc_status_addr; 124 125 mc_umc_status_addr = 126 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 127 128 /* Check MCUMC_STATUS */ 129 mc_umc_status = 130 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 131 132 if (error_type_func(adev, mc_umc_status)) 133 *error_count += 1; 134 } 135 136 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 137 uint32_t node_inst, uint32_t umc_inst, 138 uint32_t ch_inst, void *data) 139 { 140 struct ras_err_data *err_data = (struct ras_err_data *)data; 141 unsigned long ue_count = 0, ce_count = 0, de_count = 0; 142 143 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], 144 * which can be used as die ID directly */ 145 struct amdgpu_smuio_mcm_config_info mcm_info = { 146 .socket_id = adev->smuio.funcs->get_socket_id(adev), 147 .die_id = node_inst, 148 }; 149 150 uint64_t umc_reg_offset = 151 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 152 153 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 154 &ce_count, umc_v12_0_is_correctable_error); 155 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 156 &ue_count, umc_v12_0_is_uncorrectable_error); 157 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 158 &de_count, umc_v12_0_is_deferred_error); 159 160 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 161 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 162 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, de_count); 163 164 return 0; 165 } 166 167 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 168 void *ras_error_status) 169 { 170 amdgpu_umc_loop_channels(adev, 171 umc_v12_0_query_error_count, ras_error_status); 172 173 umc_v12_0_reset_error_count(adev); 174 } 175 176 static int umc_v12_0_convert_error_address(struct amdgpu_device *adev, 177 struct ras_err_data *err_data, 178 struct ta_ras_query_address_input *addr_in, 179 struct ta_ras_query_address_output *addr_out, 180 bool dump_addr) 181 { 182 uint32_t col, col_lower, row, row_lower, bank; 183 uint32_t channel_index = 0, umc_inst = 0; 184 uint32_t i, loop_bits[UMC_V12_0_RETIRE_LOOP_BITS]; 185 uint64_t soc_pa, column, err_addr; 186 struct ta_ras_query_address_output addr_out_tmp; 187 struct ta_ras_query_address_output *paddr_out; 188 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 189 int ret = 0; 190 191 if (!addr_out) 192 paddr_out = &addr_out_tmp; 193 else 194 paddr_out = addr_out; 195 196 err_addr = bank = 0; 197 if (addr_in) { 198 err_addr = addr_in->ma.err_addr; 199 addr_in->addr_type = TA_RAS_MCA_TO_PA; 200 ret = psp_ras_query_address(&adev->psp, addr_in, paddr_out); 201 if (ret) { 202 dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx", 203 err_addr); 204 205 goto out; 206 } 207 208 bank = paddr_out->pa.bank; 209 /* no need to care about umc inst if addr_in is NULL */ 210 umc_inst = addr_in->ma.umc_inst; 211 } 212 213 loop_bits[0] = UMC_V12_0_PA_C2_BIT; 214 loop_bits[1] = UMC_V12_0_PA_C3_BIT; 215 loop_bits[2] = UMC_V12_0_PA_C4_BIT; 216 loop_bits[3] = UMC_V12_0_PA_R13_BIT; 217 218 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 219 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 220 221 /* other nps modes are taken as nps1 */ 222 if (nps == AMDGPU_NPS4_PARTITION_MODE) { 223 loop_bits[0] = UMC_V12_0_PA_CH4_BIT; 224 loop_bits[1] = UMC_V12_0_PA_CH5_BIT; 225 loop_bits[2] = UMC_V12_0_PA_B0_BIT; 226 loop_bits[3] = UMC_V12_0_PA_R11_BIT; 227 } 228 229 soc_pa = paddr_out->pa.pa; 230 channel_index = paddr_out->pa.channel_idx; 231 /* clear loop bits in soc physical address */ 232 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 233 soc_pa &= ~BIT_ULL(loop_bits[i]); 234 235 paddr_out->pa.pa = soc_pa; 236 /* get column bit 0 and 1 in mca address */ 237 col_lower = (err_addr >> 1) & 0x3ULL; 238 /* MA_R13_BIT will be handled later */ 239 row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL; 240 241 if (!err_data && !dump_addr) 242 goto out; 243 244 /* loop for all possibilities of retired bits */ 245 for (column = 0; column < UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; column++) { 246 soc_pa = paddr_out->pa.pa; 247 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 248 soc_pa |= (((column >> i) & 0x1ULL) << loop_bits[i]); 249 250 col = ((column & 0x7) << 2) | col_lower; 251 /* add row bit 13 */ 252 row = ((column >> 3) << 13) | row_lower; 253 254 if (dump_addr) 255 dev_info(adev->dev, 256 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 257 soc_pa, row, col, bank, channel_index); 258 259 if (err_data) 260 amdgpu_umc_fill_error_record(err_data, err_addr, 261 soc_pa, channel_index, umc_inst); 262 } 263 264 out: 265 return ret; 266 } 267 268 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 269 uint32_t node_inst, uint32_t umc_inst, 270 uint32_t ch_inst, void *data) 271 { 272 struct ras_err_data *err_data = (struct ras_err_data *)data; 273 struct ta_ras_query_address_input addr_in; 274 uint64_t mc_umc_status_addr; 275 uint64_t mc_umc_status, err_addr; 276 uint64_t mc_umc_addrt0; 277 uint64_t umc_reg_offset = 278 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 279 280 mc_umc_status_addr = 281 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 282 283 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 284 285 if (mc_umc_status == 0) 286 return 0; 287 288 if (!err_data->err_addr) { 289 /* clear umc status */ 290 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 291 292 return 0; 293 } 294 295 /* calculate error address if ue error is detected */ 296 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) || 297 umc_v12_0_is_deferred_error(adev, mc_umc_status)) { 298 mc_umc_addrt0 = 299 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 300 301 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 302 303 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 304 305 if (!adev->aid_mask && 306 adev->smuio.funcs && 307 adev->smuio.funcs->get_socket_id) 308 addr_in.ma.socket_id = adev->smuio.funcs->get_socket_id(adev); 309 else 310 addr_in.ma.socket_id = 0; 311 312 addr_in.ma.err_addr = err_addr; 313 addr_in.ma.ch_inst = ch_inst; 314 addr_in.ma.umc_inst = umc_inst; 315 addr_in.ma.node_inst = node_inst; 316 317 umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL, true); 318 } 319 320 /* clear umc status */ 321 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 322 323 return 0; 324 } 325 326 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 327 void *ras_error_status) 328 { 329 amdgpu_umc_loop_channels(adev, 330 umc_v12_0_query_error_address, ras_error_status); 331 } 332 333 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 334 uint32_t node_inst, uint32_t umc_inst, 335 uint32_t ch_inst, void *data) 336 { 337 uint32_t odecc_cnt_sel; 338 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 339 uint64_t umc_reg_offset = 340 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 341 342 odecc_cnt_sel_addr = 343 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 344 odecc_err_cnt_addr = 345 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 346 347 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 348 349 /* set ce error interrupt type to APIC based interrupt */ 350 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 351 OdEccErrInt, 0x1); 352 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 353 354 /* set error count to initial value */ 355 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 356 357 return 0; 358 } 359 360 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, 361 enum amdgpu_mca_error_type type, void *ras_error_status) 362 { 363 uint64_t mc_umc_status = *(uint64_t *)ras_error_status; 364 365 switch (type) { 366 case AMDGPU_MCA_ERROR_TYPE_UE: 367 return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); 368 case AMDGPU_MCA_ERROR_TYPE_CE: 369 return umc_v12_0_is_correctable_error(adev, mc_umc_status); 370 case AMDGPU_MCA_ERROR_TYPE_DE: 371 return umc_v12_0_is_deferred_error(adev, mc_umc_status); 372 default: 373 return false; 374 } 375 376 return false; 377 } 378 379 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 380 { 381 amdgpu_umc_loop_channels(adev, 382 umc_v12_0_err_cnt_init_per_channel, NULL); 383 } 384 385 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 386 { 387 /* 388 * Force return true, because regUMCCH0_EccCtrl 389 * is not accessible from host side 390 */ 391 return true; 392 } 393 394 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 395 .query_ras_error_count = umc_v12_0_query_ras_error_count, 396 .query_ras_error_address = umc_v12_0_query_ras_error_address, 397 }; 398 399 static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 400 enum aca_smu_type type, void *data) 401 { 402 struct amdgpu_device *adev = handle->adev; 403 struct aca_bank_info info; 404 enum aca_error_type err_type; 405 u64 status, count; 406 u32 ext_error_code; 407 int ret; 408 409 status = bank->regs[ACA_REG_IDX_STATUS]; 410 if (umc_v12_0_is_deferred_error(adev, status)) 411 err_type = ACA_ERROR_TYPE_DEFERRED; 412 else if (umc_v12_0_is_uncorrectable_error(adev, status)) 413 err_type = ACA_ERROR_TYPE_UE; 414 else if (umc_v12_0_is_correctable_error(adev, status)) 415 err_type = ACA_ERROR_TYPE_CE; 416 else 417 return 0; 418 bank->aca_err_type = err_type; 419 420 ret = aca_bank_info_decode(bank, &info); 421 if (ret) 422 return ret; 423 424 amdgpu_umc_update_ecc_status(adev, 425 bank->regs[ACA_REG_IDX_STATUS], 426 bank->regs[ACA_REG_IDX_IPID], 427 bank->regs[ACA_REG_IDX_ADDR]); 428 429 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 430 count = ext_error_code == 0 ? 431 ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]) : 1ULL; 432 433 return aca_error_cache_log_bank_error(handle, &info, err_type, count); 434 } 435 436 static const struct aca_bank_ops umc_v12_0_aca_bank_ops = { 437 .aca_bank_parser = umc_v12_0_aca_bank_parser, 438 }; 439 440 const struct aca_info umc_v12_0_aca_info = { 441 .hwip = ACA_HWIP_TYPE_UMC, 442 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK, 443 .bank_ops = &umc_v12_0_aca_bank_ops, 444 }; 445 446 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 447 { 448 int ret; 449 450 ret = amdgpu_umc_ras_late_init(adev, ras_block); 451 if (ret) 452 return ret; 453 454 ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC, 455 &umc_v12_0_aca_info, NULL); 456 if (ret) 457 return ret; 458 459 return 0; 460 } 461 462 static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, 463 uint64_t status, uint64_t ipid, uint64_t addr) 464 { 465 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 466 uint16_t hwid, mcatype; 467 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 468 uint64_t err_addr, pa_addr = 0; 469 struct ras_ecc_err *ecc_err; 470 struct ta_ras_query_address_output addr_out; 471 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 472 uint32_t shift_bit = UMC_V12_0_PA_C4_BIT; 473 int count, ret, i; 474 475 hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); 476 mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); 477 478 if ((hwid != MCA_UMC_HWID_V12_0) || (mcatype != MCA_UMC_MCATYPE_V12_0)) 479 return 0; 480 481 if (!status) 482 return 0; 483 484 if (!umc_v12_0_is_deferred_error(adev, status)) 485 return 0; 486 487 err_addr = REG_GET_FIELD(addr, 488 MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 489 490 dev_dbg(adev->dev, 491 "UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n", 492 ipid, 493 MCA_IPID_2_SOCKET_ID(ipid), 494 MCA_IPID_2_DIE_ID(ipid), 495 MCA_IPID_2_UMC_INST(ipid), 496 MCA_IPID_2_UMC_CH(ipid), 497 err_addr); 498 499 ret = amdgpu_umc_mca_to_addr(adev, 500 err_addr, MCA_IPID_2_UMC_CH(ipid), 501 MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid), 502 MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true); 503 if (ret) 504 return ret; 505 506 ecc_err = kzalloc(sizeof(*ecc_err), GFP_KERNEL); 507 if (!ecc_err) 508 return -ENOMEM; 509 510 pa_addr = addr_out.pa.pa; 511 ecc_err->status = status; 512 ecc_err->ipid = ipid; 513 ecc_err->addr = addr; 514 ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT; 515 ecc_err->channel_idx = addr_out.pa.channel_idx; 516 517 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 518 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 519 if (nps == AMDGPU_NPS4_PARTITION_MODE) 520 shift_bit = UMC_V12_0_PA_B0_BIT; 521 522 /* If converted pa_pfn is 0, use pa C4 pfn. */ 523 if (!ecc_err->pa_pfn) 524 ecc_err->pa_pfn = BIT_ULL(shift_bit) >> AMDGPU_GPU_PAGE_SHIFT; 525 526 ret = amdgpu_umc_logs_ecc_err(adev, &con->umc_ecc_log.de_page_tree, ecc_err); 527 if (ret) { 528 if (ret == -EEXIST) 529 con->umc_ecc_log.de_queried_count++; 530 else 531 dev_err(adev->dev, "Fail to log ecc error! ret:%d\n", ret); 532 533 kfree(ecc_err); 534 return ret; 535 } 536 537 con->umc_ecc_log.de_queried_count++; 538 539 memset(page_pfn, 0, sizeof(page_pfn)); 540 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 541 pa_addr, 542 page_pfn, ARRAY_SIZE(page_pfn)); 543 if (count <= 0) { 544 dev_warn(adev->dev, "Fail to convert error address! count:%d\n", count); 545 return 0; 546 } 547 548 /* Reserve memory */ 549 for (i = 0; i < count; i++) 550 amdgpu_ras_reserve_page(adev, page_pfn[i]); 551 552 /* The problem case is as follows: 553 * 1. GPU A triggers a gpu ras reset, and GPU A drives 554 * GPU B to also perform a gpu ras reset. 555 * 2. After gpu B ras reset started, gpu B queried a DE 556 * data. Since the DE data was queried in the ras reset 557 * thread instead of the page retirement thread, bad 558 * page retirement work would not be triggered. Then 559 * even if all gpu resets are completed, the bad pages 560 * will be cached in RAM until GPU B's bad page retirement 561 * work is triggered again and then saved to eeprom. 562 * Trigger delayed work to save the bad pages to eeprom in time 563 * after gpu ras reset is completed. 564 */ 565 if (amdgpu_ras_in_recovery(adev)) 566 schedule_delayed_work(&con->page_retirement_dwork, 567 msecs_to_jiffies(DELAYED_TIME_FOR_GPU_RESET)); 568 569 return 0; 570 } 571 572 static int umc_v12_0_fill_error_record(struct amdgpu_device *adev, 573 struct ras_ecc_err *ecc_err, void *ras_error_status) 574 { 575 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 576 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 577 int ret, i, count; 578 579 if (!err_data || !ecc_err) 580 return -EINVAL; 581 582 memset(page_pfn, 0, sizeof(page_pfn)); 583 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 584 ecc_err->pa_pfn << AMDGPU_GPU_PAGE_SHIFT, 585 page_pfn, ARRAY_SIZE(page_pfn)); 586 587 for (i = 0; i < count; i++) { 588 ret = amdgpu_umc_fill_error_record(err_data, 589 ecc_err->addr, 590 page_pfn[i] << AMDGPU_GPU_PAGE_SHIFT, 591 ecc_err->channel_idx, 592 MCA_IPID_2_UMC_INST(ecc_err->ipid)); 593 if (ret) 594 break; 595 } 596 597 err_data->de_count++; 598 599 return ret; 600 } 601 602 static void umc_v12_0_query_ras_ecc_err_addr(struct amdgpu_device *adev, 603 void *ras_error_status) 604 { 605 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 606 struct ras_ecc_err *entries[MAX_ECC_NUM_PER_RETIREMENT]; 607 struct radix_tree_root *ecc_tree; 608 int new_detected, ret, i; 609 610 ecc_tree = &con->umc_ecc_log.de_page_tree; 611 612 mutex_lock(&con->umc_ecc_log.lock); 613 new_detected = radix_tree_gang_lookup_tag(ecc_tree, (void **)entries, 614 0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG); 615 for (i = 0; i < new_detected; i++) { 616 if (!entries[i]) 617 continue; 618 619 ret = umc_v12_0_fill_error_record(adev, entries[i], ras_error_status); 620 if (ret) { 621 dev_err(adev->dev, "Fail to fill umc error record, ret:%d\n", ret); 622 break; 623 } 624 radix_tree_tag_clear(ecc_tree, 625 entries[i]->pa_pfn, UMC_ECC_NEW_DETECTED_TAG); 626 } 627 mutex_unlock(&con->umc_ecc_log.lock); 628 } 629 630 static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev, 631 uint64_t mca_addr, uint64_t retired_page) 632 { 633 uint32_t die = 0; 634 635 /* we only calculate die id for nps1 mode right now */ 636 die += ((((retired_page >> 12) & 0x1ULL)^ 637 ((retired_page >> 20) & 0x1ULL) ^ 638 ((retired_page >> 27) & 0x1ULL) ^ 639 ((retired_page >> 34) & 0x1ULL) ^ 640 ((retired_page >> 41) & 0x1ULL)) << 0); 641 642 /* the original PA_C4 and PA_R13 may be cleared in retired_page, so 643 * get them from mca_addr. 644 */ 645 die += ((((retired_page >> 13) & 0x1ULL) ^ 646 ((mca_addr >> 5) & 0x1ULL) ^ 647 ((retired_page >> 28) & 0x1ULL) ^ 648 ((mca_addr >> 23) & 0x1ULL) ^ 649 ((retired_page >> 42) & 0x1ULL)) << 1); 650 die &= 3; 651 652 return die; 653 } 654 655 struct amdgpu_umc_ras umc_v12_0_ras = { 656 .ras_block = { 657 .hw_ops = &umc_v12_0_ras_hw_ops, 658 .ras_late_init = umc_v12_0_ras_late_init, 659 }, 660 .err_cnt_init = umc_v12_0_err_cnt_init, 661 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 662 .ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr, 663 .check_ecc_err_status = umc_v12_0_check_ecc_err_status, 664 .update_ecc_status = umc_v12_0_update_ecc_status, 665 .convert_ras_err_addr = umc_v12_0_convert_error_address, 666 .get_die_id_from_pa = umc_v12_0_get_die_id, 667 }; 668 669