1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 32 { 33 dev_dbg(adev->dev, 34 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", 35 mc_umc_status, 36 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), 37 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), 38 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), 39 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), 40 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), 41 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) 42 ); 43 44 return (amdgpu_ras_is_poison_mode_supported(adev) && 45 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 46 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) || 47 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1))); 48 } 49 50 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 51 { 52 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 53 return false; 54 55 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 56 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 57 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 58 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 59 } 60 61 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 62 { 63 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 64 return false; 65 66 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 67 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 68 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 69 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 70 /* Identify data parity error in replay mode */ 71 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 72 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 73 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 74 } 75 76 static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) 77 { 78 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 79 uint32_t vram_type = adev->gmc.vram_type; 80 struct amdgpu_umc_flip_bits *flip_bits = &(adev->umc.flip_bits); 81 82 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 83 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 84 85 if (adev->gmc.num_umc == 16) { 86 /* default setting */ 87 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; 88 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; 89 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; 90 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; 91 flip_bits->flip_row_bit = 13; 92 flip_bits->bit_num = 4; 93 flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; 94 95 if (nps == AMDGPU_NPS2_PARTITION_MODE) { 96 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; 97 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; 98 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; 99 flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; 100 } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { 101 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; 102 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; 103 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; 104 flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; 105 } 106 107 switch (vram_type) { 108 case AMDGPU_VRAM_TYPE_HBM: 109 /* other nps modes are taken as nps1 */ 110 if (nps == AMDGPU_NPS2_PARTITION_MODE) 111 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 112 else if (nps == AMDGPU_NPS4_PARTITION_MODE) 113 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 114 115 break; 116 case AMDGPU_VRAM_TYPE_HBM3E: 117 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 118 flip_bits->flip_row_bit = 12; 119 120 if (nps == AMDGPU_NPS2_PARTITION_MODE) 121 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 122 else if (nps == AMDGPU_NPS4_PARTITION_MODE) 123 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; 124 125 break; 126 default: 127 dev_warn(adev->dev, 128 "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); 129 break; 130 } 131 } else if (adev->gmc.num_umc == 8) { 132 /* default setting */ 133 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; 134 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; 135 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; 136 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 137 flip_bits->flip_row_bit = 12; 138 flip_bits->bit_num = 4; 139 flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; 140 141 if (nps == AMDGPU_NPS2_PARTITION_MODE) { 142 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; 143 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; 144 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; 145 flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; 146 } 147 148 switch (vram_type) { 149 case AMDGPU_VRAM_TYPE_HBM: 150 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 151 152 /* other nps modes are taken as nps1 */ 153 if (nps == AMDGPU_NPS2_PARTITION_MODE) 154 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 155 156 break; 157 case AMDGPU_VRAM_TYPE_HBM3E: 158 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 159 flip_bits->flip_row_bit = 12; 160 161 if (nps == AMDGPU_NPS2_PARTITION_MODE) 162 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; 163 164 break; 165 default: 166 dev_warn(adev->dev, 167 "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); 168 break; 169 } 170 } else { 171 dev_warn(adev->dev, 172 "Unsupported UMC number(%d), failed to set RAS flip bits.\n", 173 adev->gmc.num_umc); 174 175 return; 176 } 177 178 adev->umc.retire_unit = 0x1 << flip_bits->bit_num; 179 } 180 181 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, 182 enum amdgpu_mca_error_type type, void *ras_error_status) 183 { 184 uint64_t mc_umc_status = *(uint64_t *)ras_error_status; 185 186 switch (type) { 187 case AMDGPU_MCA_ERROR_TYPE_UE: 188 return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); 189 case AMDGPU_MCA_ERROR_TYPE_CE: 190 return umc_v12_0_is_correctable_error(adev, mc_umc_status); 191 case AMDGPU_MCA_ERROR_TYPE_DE: 192 return umc_v12_0_is_deferred_error(adev, mc_umc_status); 193 default: 194 return false; 195 } 196 197 return false; 198 } 199 200 struct amdgpu_umc_ras umc_v12_0_ras = { 201 .ras_block = { 202 .hw_ops = NULL, 203 }, 204 .check_ecc_err_status = umc_v12_0_check_ecc_err_status, 205 .get_retire_flip_bits = umc_v12_0_get_retire_flip_bits, 206 }; 207 208