1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 #define MAX_ECC_NUM_PER_RETIREMENT 32 32 #define DELAYED_TIME_FOR_GPU_RESET 1000 //ms 33 34 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 35 uint32_t node_inst, 36 uint32_t umc_inst, 37 uint32_t ch_inst) 38 { 39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 40 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 41 42 umc_inst = index / 4; 43 ch_inst = index % 4; 44 45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 46 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 47 } 48 49 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 50 uint32_t node_inst, uint32_t umc_inst, 51 uint32_t ch_inst, void *data) 52 { 53 uint64_t odecc_err_cnt_addr; 54 uint64_t umc_reg_offset = 55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 56 57 odecc_err_cnt_addr = 58 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 59 60 /* clear error count */ 61 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 62 UMC_V12_0_CE_CNT_INIT); 63 64 return 0; 65 } 66 67 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 68 { 69 amdgpu_umc_loop_channels(adev, 70 umc_v12_0_reset_error_count_per_channel, NULL); 71 } 72 73 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 74 { 75 dev_dbg(adev->dev, 76 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", 77 mc_umc_status, 78 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), 79 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), 80 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), 81 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), 82 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), 83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) 84 ); 85 86 return (amdgpu_ras_is_poison_mode_supported(adev) && 87 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 88 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) || 89 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1))); 90 } 91 92 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 93 { 94 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 95 return false; 96 97 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 98 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 100 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 101 } 102 103 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 104 { 105 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 106 return false; 107 108 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 109 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 110 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 111 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 112 /* Identify data parity error in replay mode */ 113 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 114 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 115 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 116 } 117 118 static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev, 119 uint64_t umc_reg_offset, 120 unsigned long *error_count, 121 check_error_type_func error_type_func) 122 { 123 uint64_t mc_umc_status; 124 uint64_t mc_umc_status_addr; 125 126 mc_umc_status_addr = 127 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 128 129 /* Check MCUMC_STATUS */ 130 mc_umc_status = 131 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 132 133 if (error_type_func(adev, mc_umc_status)) 134 *error_count += 1; 135 } 136 137 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 138 uint32_t node_inst, uint32_t umc_inst, 139 uint32_t ch_inst, void *data) 140 { 141 struct ras_err_data *err_data = (struct ras_err_data *)data; 142 unsigned long ue_count = 0, ce_count = 0, de_count = 0; 143 144 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], 145 * which can be used as die ID directly */ 146 struct amdgpu_smuio_mcm_config_info mcm_info = { 147 .socket_id = adev->smuio.funcs->get_socket_id(adev), 148 .die_id = node_inst, 149 }; 150 151 uint64_t umc_reg_offset = 152 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 153 154 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 155 &ce_count, umc_v12_0_is_correctable_error); 156 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 157 &ue_count, umc_v12_0_is_uncorrectable_error); 158 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 159 &de_count, umc_v12_0_is_deferred_error); 160 161 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 162 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 163 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, de_count); 164 165 return 0; 166 } 167 168 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 169 void *ras_error_status) 170 { 171 amdgpu_umc_loop_channels(adev, 172 umc_v12_0_query_error_count, ras_error_status); 173 174 umc_v12_0_reset_error_count(adev); 175 } 176 177 static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) 178 { 179 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 180 uint32_t vram_type = adev->gmc.vram_type; 181 struct amdgpu_umc_flip_bits *flip_bits = &(adev->umc.flip_bits); 182 183 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 184 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 185 186 if (adev->gmc.num_umc == 16) { 187 /* default setting */ 188 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; 189 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; 190 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; 191 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; 192 flip_bits->flip_row_bit = 13; 193 flip_bits->bit_num = 4; 194 flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; 195 196 if (nps == AMDGPU_NPS2_PARTITION_MODE) { 197 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; 198 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; 199 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; 200 flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; 201 } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { 202 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; 203 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; 204 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; 205 flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; 206 } 207 208 switch (vram_type) { 209 case AMDGPU_VRAM_TYPE_HBM: 210 /* other nps modes are taken as nps1 */ 211 if (nps == AMDGPU_NPS2_PARTITION_MODE) 212 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 213 else if (nps == AMDGPU_NPS4_PARTITION_MODE) 214 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 215 216 break; 217 case AMDGPU_VRAM_TYPE_HBM3E: 218 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 219 flip_bits->flip_row_bit = 12; 220 221 if (nps == AMDGPU_NPS2_PARTITION_MODE) 222 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 223 else if (nps == AMDGPU_NPS4_PARTITION_MODE) 224 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; 225 226 break; 227 default: 228 dev_warn(adev->dev, 229 "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); 230 break; 231 } 232 } else if (adev->gmc.num_umc == 8) { 233 /* default setting */ 234 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; 235 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; 236 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; 237 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 238 flip_bits->flip_row_bit = 12; 239 flip_bits->bit_num = 4; 240 flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; 241 242 if (nps == AMDGPU_NPS2_PARTITION_MODE) { 243 flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; 244 flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; 245 flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; 246 flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; 247 } 248 249 switch (vram_type) { 250 case AMDGPU_VRAM_TYPE_HBM: 251 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; 252 253 /* other nps modes are taken as nps1 */ 254 if (nps == AMDGPU_NPS2_PARTITION_MODE) 255 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 256 257 break; 258 case AMDGPU_VRAM_TYPE_HBM3E: 259 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; 260 flip_bits->flip_row_bit = 12; 261 262 if (nps == AMDGPU_NPS2_PARTITION_MODE) 263 flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; 264 265 break; 266 default: 267 dev_warn(adev->dev, 268 "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); 269 break; 270 } 271 } else { 272 dev_warn(adev->dev, 273 "Unsupported UMC number(%d), failed to set RAS flip bits.\n", 274 adev->gmc.num_umc); 275 276 return; 277 } 278 279 adev->umc.retire_unit = 0x1 << flip_bits->bit_num; 280 } 281 282 static int umc_v12_0_convert_error_address(struct amdgpu_device *adev, 283 struct ras_err_data *err_data, 284 struct ta_ras_query_address_input *addr_in, 285 struct ta_ras_query_address_output *addr_out, 286 bool dump_addr) 287 { 288 uint32_t row = 0, row_lower = 0, row_high = 0; 289 uint32_t col = 0, col_lower = 0, bank = 0; 290 uint32_t channel_index = 0, umc_inst = 0; 291 uint32_t i, bit_num, retire_unit, *flip_bits; 292 uint64_t soc_pa, column, err_addr; 293 struct ta_ras_query_address_output addr_out_tmp; 294 struct ta_ras_query_address_output *paddr_out; 295 int ret = 0; 296 297 if (!addr_out) 298 paddr_out = &addr_out_tmp; 299 else 300 paddr_out = addr_out; 301 302 err_addr = bank = 0; 303 if (addr_in) { 304 err_addr = addr_in->ma.err_addr; 305 addr_in->addr_type = TA_RAS_MCA_TO_PA; 306 ret = psp_ras_query_address(&adev->psp, addr_in, paddr_out); 307 if (ret) { 308 dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx", 309 err_addr); 310 311 goto out; 312 } 313 314 bank = paddr_out->pa.bank; 315 /* no need to care about umc inst if addr_in is NULL */ 316 umc_inst = addr_in->ma.umc_inst; 317 } 318 319 flip_bits = adev->umc.flip_bits.flip_bits_in_pa; 320 bit_num = adev->umc.flip_bits.bit_num; 321 retire_unit = adev->umc.retire_unit; 322 323 soc_pa = paddr_out->pa.pa; 324 channel_index = paddr_out->pa.channel_idx; 325 /* clear loop bits in soc physical address */ 326 for (i = 0; i < bit_num; i++) 327 soc_pa &= ~BIT_ULL(flip_bits[i]); 328 329 paddr_out->pa.pa = soc_pa; 330 /* get column bit 0 and 1 in mca address */ 331 col_lower = (err_addr >> 1) & 0x3ULL; 332 /* extra row bit will be handled later */ 333 row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL; 334 row_lower &= ~BIT_ULL(adev->umc.flip_bits.flip_row_bit); 335 336 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 5, 0)) { 337 row_high = (soc_pa >> adev->umc.flip_bits.r13_in_pa) & 0x3ULL; 338 /* it's 2.25GB in each channel, from MCA address to PA 339 * [R14 R13] is converted if the two bits value are 0x3, 340 * get them from PA instead of MCA address. 341 */ 342 row_lower |= (row_high << 13); 343 } 344 345 if (!err_data && !dump_addr) 346 goto out; 347 348 /* loop for all possibilities of retired bits */ 349 for (column = 0; column < retire_unit; column++) { 350 soc_pa = paddr_out->pa.pa; 351 for (i = 0; i < bit_num; i++) 352 soc_pa |= (((column >> i) & 0x1ULL) << flip_bits[i]); 353 354 col = ((column & 0x7) << 2) | col_lower; 355 /* handle extra row bit */ 356 if (bit_num == RETIRE_FLIP_BITS_NUM) 357 row = ((column >> 3) << adev->umc.flip_bits.flip_row_bit) | 358 row_lower; 359 360 if (dump_addr) 361 dev_info(adev->dev, 362 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 363 soc_pa, row, col, bank, channel_index); 364 365 if (err_data) 366 amdgpu_umc_fill_error_record(err_data, err_addr, 367 soc_pa, channel_index, umc_inst); 368 } 369 370 out: 371 return ret; 372 } 373 374 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 375 uint32_t node_inst, uint32_t umc_inst, 376 uint32_t ch_inst, void *data) 377 { 378 struct ras_err_data *err_data = (struct ras_err_data *)data; 379 struct ta_ras_query_address_input addr_in; 380 uint64_t mc_umc_status_addr; 381 uint64_t mc_umc_status, err_addr; 382 uint64_t mc_umc_addrt0; 383 uint64_t umc_reg_offset = 384 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 385 386 mc_umc_status_addr = 387 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 388 389 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 390 391 if (mc_umc_status == 0) 392 return 0; 393 394 if (!err_data->err_addr) { 395 /* clear umc status */ 396 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 397 398 return 0; 399 } 400 401 /* calculate error address if ue error is detected */ 402 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) || 403 umc_v12_0_is_deferred_error(adev, mc_umc_status)) { 404 mc_umc_addrt0 = 405 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 406 407 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 408 409 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 410 411 if (!adev->aid_mask && 412 adev->smuio.funcs && 413 adev->smuio.funcs->get_socket_id) 414 addr_in.ma.socket_id = adev->smuio.funcs->get_socket_id(adev); 415 else 416 addr_in.ma.socket_id = 0; 417 418 addr_in.ma.err_addr = err_addr; 419 addr_in.ma.ch_inst = ch_inst; 420 addr_in.ma.umc_inst = umc_inst; 421 addr_in.ma.node_inst = node_inst; 422 423 umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL, true); 424 } 425 426 /* clear umc status */ 427 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 428 429 return 0; 430 } 431 432 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 433 void *ras_error_status) 434 { 435 amdgpu_umc_loop_channels(adev, 436 umc_v12_0_query_error_address, ras_error_status); 437 } 438 439 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 440 uint32_t node_inst, uint32_t umc_inst, 441 uint32_t ch_inst, void *data) 442 { 443 uint32_t odecc_cnt_sel; 444 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 445 uint64_t umc_reg_offset = 446 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 447 448 odecc_cnt_sel_addr = 449 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 450 odecc_err_cnt_addr = 451 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 452 453 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 454 455 /* set ce error interrupt type to APIC based interrupt */ 456 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 457 OdEccErrInt, 0x1); 458 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 459 460 /* set error count to initial value */ 461 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 462 463 return 0; 464 } 465 466 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, 467 enum amdgpu_mca_error_type type, void *ras_error_status) 468 { 469 uint64_t mc_umc_status = *(uint64_t *)ras_error_status; 470 471 switch (type) { 472 case AMDGPU_MCA_ERROR_TYPE_UE: 473 return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); 474 case AMDGPU_MCA_ERROR_TYPE_CE: 475 return umc_v12_0_is_correctable_error(adev, mc_umc_status); 476 case AMDGPU_MCA_ERROR_TYPE_DE: 477 return umc_v12_0_is_deferred_error(adev, mc_umc_status); 478 default: 479 return false; 480 } 481 482 return false; 483 } 484 485 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 486 { 487 amdgpu_umc_loop_channels(adev, 488 umc_v12_0_err_cnt_init_per_channel, NULL); 489 } 490 491 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 492 { 493 /* 494 * Force return true, because regUMCCH0_EccCtrl 495 * is not accessible from host side 496 */ 497 return true; 498 } 499 500 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 501 .query_ras_error_count = umc_v12_0_query_ras_error_count, 502 .query_ras_error_address = umc_v12_0_query_ras_error_address, 503 }; 504 505 static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 506 enum aca_smu_type type, void *data) 507 { 508 struct amdgpu_device *adev = handle->adev; 509 struct aca_bank_info info; 510 enum aca_error_type err_type; 511 u64 status, count; 512 u32 ext_error_code; 513 int ret; 514 515 status = bank->regs[ACA_REG_IDX_STATUS]; 516 if (umc_v12_0_is_deferred_error(adev, status)) 517 err_type = ACA_ERROR_TYPE_DEFERRED; 518 else if (umc_v12_0_is_uncorrectable_error(adev, status)) 519 err_type = ACA_ERROR_TYPE_UE; 520 else if (umc_v12_0_is_correctable_error(adev, status)) 521 err_type = ACA_ERROR_TYPE_CE; 522 else 523 return 0; 524 bank->aca_err_type = err_type; 525 526 ret = aca_bank_info_decode(bank, &info); 527 if (ret) 528 return ret; 529 530 amdgpu_umc_update_ecc_status(adev, 531 bank->regs[ACA_REG_IDX_STATUS], 532 bank->regs[ACA_REG_IDX_IPID], 533 bank->regs[ACA_REG_IDX_ADDR]); 534 535 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 536 if (umc_v12_0_is_deferred_error(adev, status)) 537 count = ext_error_code == 0 ? 538 adev->umc.err_addr_cnt / adev->umc.retire_unit : 1ULL; 539 else 540 count = ext_error_code == 0 ? 541 ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]) : 1ULL; 542 543 return aca_error_cache_log_bank_error(handle, &info, err_type, count); 544 } 545 546 static const struct aca_bank_ops umc_v12_0_aca_bank_ops = { 547 .aca_bank_parser = umc_v12_0_aca_bank_parser, 548 }; 549 550 const struct aca_info umc_v12_0_aca_info = { 551 .hwip = ACA_HWIP_TYPE_UMC, 552 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK, 553 .bank_ops = &umc_v12_0_aca_bank_ops, 554 }; 555 556 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 557 { 558 int ret; 559 560 ret = amdgpu_umc_ras_late_init(adev, ras_block); 561 if (ret) 562 return ret; 563 564 ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC, 565 &umc_v12_0_aca_info, NULL); 566 if (ret) 567 return ret; 568 569 return 0; 570 } 571 572 static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, 573 uint64_t status, uint64_t ipid, uint64_t addr) 574 { 575 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 576 uint16_t hwid, mcatype; 577 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 578 uint64_t err_addr, pa_addr = 0; 579 struct ras_ecc_err *ecc_err; 580 struct ta_ras_query_address_output addr_out; 581 uint32_t shift_bit = adev->umc.flip_bits.flip_bits_in_pa[2]; 582 int count, ret, i; 583 584 hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); 585 mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); 586 587 /* The IP block decode of consumption is SMU */ 588 if (hwid != MCA_UMC_HWID_V12_0 || mcatype != MCA_UMC_MCATYPE_V12_0) { 589 con->umc_ecc_log.consumption_q_count++; 590 return 0; 591 } 592 593 if (!status) 594 return 0; 595 596 if (!umc_v12_0_is_deferred_error(adev, status)) 597 return 0; 598 599 err_addr = REG_GET_FIELD(addr, 600 MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 601 602 dev_dbg(adev->dev, 603 "UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n", 604 ipid, 605 MCA_IPID_2_SOCKET_ID(ipid), 606 MCA_IPID_2_DIE_ID(ipid), 607 MCA_IPID_2_UMC_INST(ipid), 608 MCA_IPID_2_UMC_CH(ipid), 609 err_addr); 610 611 ret = amdgpu_umc_mca_to_addr(adev, 612 err_addr, MCA_IPID_2_UMC_CH(ipid), 613 MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid), 614 MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true); 615 if (ret) 616 return ret; 617 618 ecc_err = kzalloc_obj(*ecc_err); 619 if (!ecc_err) 620 return -ENOMEM; 621 622 pa_addr = addr_out.pa.pa; 623 ecc_err->status = status; 624 ecc_err->ipid = ipid; 625 ecc_err->addr = addr; 626 ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT; 627 ecc_err->channel_idx = addr_out.pa.channel_idx; 628 629 /* If converted pa_pfn is 0, use pa C4 pfn. */ 630 if (!ecc_err->pa_pfn) 631 ecc_err->pa_pfn = BIT_ULL(shift_bit) >> AMDGPU_GPU_PAGE_SHIFT; 632 633 ret = amdgpu_umc_logs_ecc_err(adev, &con->umc_ecc_log.de_page_tree, ecc_err); 634 if (ret) { 635 if (ret == -EEXIST) 636 con->umc_ecc_log.de_queried_count++; 637 else 638 dev_err(adev->dev, "Fail to log ecc error! ret:%d\n", ret); 639 640 kfree(ecc_err); 641 return ret; 642 } 643 644 con->umc_ecc_log.de_queried_count++; 645 646 memset(page_pfn, 0, sizeof(page_pfn)); 647 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 648 pa_addr, 649 page_pfn, ARRAY_SIZE(page_pfn)); 650 if (count <= 0) { 651 dev_warn(adev->dev, "Fail to convert error address! count:%d\n", count); 652 return 0; 653 } 654 655 /* Reserve memory */ 656 for (i = 0; i < count; i++) 657 amdgpu_ras_reserve_page(adev, page_pfn[i]); 658 659 /* The problem case is as follows: 660 * 1. GPU A triggers a gpu ras reset, and GPU A drives 661 * GPU B to also perform a gpu ras reset. 662 * 2. After gpu B ras reset started, gpu B queried a DE 663 * data. Since the DE data was queried in the ras reset 664 * thread instead of the page retirement thread, bad 665 * page retirement work would not be triggered. Then 666 * even if all gpu resets are completed, the bad pages 667 * will be cached in RAM until GPU B's bad page retirement 668 * work is triggered again and then saved to eeprom. 669 * Trigger delayed work to save the bad pages to eeprom in time 670 * after gpu ras reset is completed. 671 */ 672 if (amdgpu_ras_in_recovery(adev)) 673 schedule_delayed_work(&con->page_retirement_dwork, 674 msecs_to_jiffies(DELAYED_TIME_FOR_GPU_RESET)); 675 676 return 0; 677 } 678 679 static int umc_v12_0_fill_error_record(struct amdgpu_device *adev, 680 struct ras_ecc_err *ecc_err, void *ras_error_status) 681 { 682 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 683 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 684 int ret, i, count; 685 686 if (!err_data || !ecc_err) 687 return -EINVAL; 688 689 memset(page_pfn, 0, sizeof(page_pfn)); 690 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 691 ecc_err->pa_pfn << AMDGPU_GPU_PAGE_SHIFT, 692 page_pfn, ARRAY_SIZE(page_pfn)); 693 694 for (i = 0; i < count; i++) { 695 ret = amdgpu_umc_fill_error_record(err_data, 696 ecc_err->addr, 697 page_pfn[i] << AMDGPU_GPU_PAGE_SHIFT, 698 ecc_err->channel_idx, 699 MCA_IPID_2_UMC_INST(ecc_err->ipid)); 700 if (ret) 701 break; 702 } 703 704 err_data->de_count++; 705 706 return ret; 707 } 708 709 static void umc_v12_0_query_ras_ecc_err_addr(struct amdgpu_device *adev, 710 void *ras_error_status) 711 { 712 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 713 struct ras_ecc_err *entries[MAX_ECC_NUM_PER_RETIREMENT]; 714 struct radix_tree_root *ecc_tree; 715 int new_detected, ret, i; 716 717 ecc_tree = &con->umc_ecc_log.de_page_tree; 718 719 mutex_lock(&con->umc_ecc_log.lock); 720 new_detected = radix_tree_gang_lookup_tag(ecc_tree, (void **)entries, 721 0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG); 722 for (i = 0; i < new_detected; i++) { 723 if (!entries[i]) 724 continue; 725 726 ret = umc_v12_0_fill_error_record(adev, entries[i], ras_error_status); 727 if (ret) { 728 dev_err(adev->dev, "Fail to fill umc error record, ret:%d\n", ret); 729 break; 730 } 731 radix_tree_tag_clear(ecc_tree, 732 entries[i]->pa_pfn, UMC_ECC_NEW_DETECTED_TAG); 733 } 734 mutex_unlock(&con->umc_ecc_log.lock); 735 } 736 737 static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev, 738 uint64_t mca_addr, uint64_t retired_page) 739 { 740 uint32_t die = 0; 741 742 /* we only calculate die id for nps1 mode right now */ 743 die += ((((retired_page >> 12) & 0x1ULL)^ 744 ((retired_page >> 20) & 0x1ULL) ^ 745 ((retired_page >> 27) & 0x1ULL) ^ 746 ((retired_page >> 34) & 0x1ULL) ^ 747 ((retired_page >> 41) & 0x1ULL)) << 0); 748 749 /* the original PA_C4 and PA_R13 may be cleared in retired_page, so 750 * get them from mca_addr. 751 */ 752 die += ((((retired_page >> 13) & 0x1ULL) ^ 753 ((mca_addr >> 5) & 0x1ULL) ^ 754 ((retired_page >> 28) & 0x1ULL) ^ 755 ((mca_addr >> 23) & 0x1ULL) ^ 756 ((retired_page >> 42) & 0x1ULL)) << 1); 757 die &= 3; 758 759 return die; 760 } 761 762 static void umc_v12_0_mca_ipid_parse(struct amdgpu_device *adev, uint64_t ipid, 763 uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid) 764 { 765 if (did) 766 *did = MCA_IPID_2_DIE_ID(ipid); 767 if (ch) 768 *ch = MCA_IPID_2_UMC_CH(ipid); 769 if (umc_inst) 770 *umc_inst = MCA_IPID_2_UMC_INST(ipid); 771 if (sid) 772 *sid = MCA_IPID_2_SOCKET_ID(ipid); 773 } 774 775 struct amdgpu_umc_ras umc_v12_0_ras = { 776 .ras_block = { 777 .hw_ops = &umc_v12_0_ras_hw_ops, 778 .ras_late_init = umc_v12_0_ras_late_init, 779 }, 780 .err_cnt_init = umc_v12_0_err_cnt_init, 781 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 782 .ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr, 783 .check_ecc_err_status = umc_v12_0_check_ecc_err_status, 784 .update_ecc_status = umc_v12_0_update_ecc_status, 785 .convert_ras_err_addr = umc_v12_0_convert_error_address, 786 .get_die_id_from_pa = umc_v12_0_get_die_id, 787 .get_retire_flip_bits = umc_v12_0_get_retire_flip_bits, 788 .mca_ipid_parse = umc_v12_0_mca_ipid_parse, 789 }; 790 791