1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 #define MAX_ECC_NUM_PER_RETIREMENT 32 32 #define DELAYED_TIME_FOR_GPU_RESET 1000 //ms 33 34 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 35 uint32_t node_inst, 36 uint32_t umc_inst, 37 uint32_t ch_inst) 38 { 39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 40 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 41 42 umc_inst = index / 4; 43 ch_inst = index % 4; 44 45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 46 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 47 } 48 49 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 50 uint32_t node_inst, uint32_t umc_inst, 51 uint32_t ch_inst, void *data) 52 { 53 uint64_t odecc_err_cnt_addr; 54 uint64_t umc_reg_offset = 55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 56 57 odecc_err_cnt_addr = 58 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 59 60 /* clear error count */ 61 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 62 UMC_V12_0_CE_CNT_INIT); 63 64 return 0; 65 } 66 67 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 68 { 69 amdgpu_umc_loop_channels(adev, 70 umc_v12_0_reset_error_count_per_channel, NULL); 71 } 72 73 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 74 { 75 dev_dbg(adev->dev, 76 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", 77 mc_umc_status, 78 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), 79 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), 80 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), 81 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), 82 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), 83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) 84 ); 85 86 return (amdgpu_ras_is_poison_mode_supported(adev) && 87 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 88 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) || 89 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1))); 90 } 91 92 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 93 { 94 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 95 return false; 96 97 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 98 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 100 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 101 } 102 103 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 104 { 105 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 106 return false; 107 108 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 109 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 110 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 111 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 112 /* Identify data parity error in replay mode */ 113 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 114 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 115 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 116 } 117 118 static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev, 119 uint64_t umc_reg_offset, 120 unsigned long *error_count, 121 check_error_type_func error_type_func) 122 { 123 uint64_t mc_umc_status; 124 uint64_t mc_umc_status_addr; 125 126 mc_umc_status_addr = 127 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 128 129 /* Check MCUMC_STATUS */ 130 mc_umc_status = 131 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 132 133 if (error_type_func(adev, mc_umc_status)) 134 *error_count += 1; 135 } 136 137 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 138 uint32_t node_inst, uint32_t umc_inst, 139 uint32_t ch_inst, void *data) 140 { 141 struct ras_err_data *err_data = (struct ras_err_data *)data; 142 unsigned long ue_count = 0, ce_count = 0, de_count = 0; 143 144 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], 145 * which can be used as die ID directly */ 146 struct amdgpu_smuio_mcm_config_info mcm_info = { 147 .socket_id = adev->smuio.funcs->get_socket_id(adev), 148 .die_id = node_inst, 149 }; 150 151 uint64_t umc_reg_offset = 152 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 153 154 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 155 &ce_count, umc_v12_0_is_correctable_error); 156 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 157 &ue_count, umc_v12_0_is_uncorrectable_error); 158 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 159 &de_count, umc_v12_0_is_deferred_error); 160 161 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 162 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 163 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, de_count); 164 165 return 0; 166 } 167 168 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 169 void *ras_error_status) 170 { 171 amdgpu_umc_loop_channels(adev, 172 umc_v12_0_query_error_count, ras_error_status); 173 174 umc_v12_0_reset_error_count(adev); 175 } 176 177 static int umc_v12_0_convert_error_address(struct amdgpu_device *adev, 178 struct ras_err_data *err_data, 179 struct ta_ras_query_address_input *addr_in, 180 struct ta_ras_query_address_output *addr_out, 181 bool dump_addr) 182 { 183 uint32_t col, col_lower, row, row_lower, bank; 184 uint32_t channel_index = 0, umc_inst = 0; 185 uint32_t i, loop_bits[UMC_V12_0_RETIRE_LOOP_BITS]; 186 uint64_t soc_pa, column, err_addr; 187 struct ta_ras_query_address_output addr_out_tmp; 188 struct ta_ras_query_address_output *paddr_out; 189 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 190 int ret = 0; 191 192 if (!addr_out) 193 paddr_out = &addr_out_tmp; 194 else 195 paddr_out = addr_out; 196 197 err_addr = bank = 0; 198 if (addr_in) { 199 err_addr = addr_in->ma.err_addr; 200 addr_in->addr_type = TA_RAS_MCA_TO_PA; 201 ret = psp_ras_query_address(&adev->psp, addr_in, paddr_out); 202 if (ret) { 203 dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx", 204 err_addr); 205 206 goto out; 207 } 208 209 bank = paddr_out->pa.bank; 210 /* no need to care about umc inst if addr_in is NULL */ 211 umc_inst = addr_in->ma.umc_inst; 212 } 213 214 loop_bits[0] = UMC_V12_0_PA_C2_BIT; 215 loop_bits[1] = UMC_V12_0_PA_C3_BIT; 216 loop_bits[2] = UMC_V12_0_PA_C4_BIT; 217 loop_bits[3] = UMC_V12_0_PA_R13_BIT; 218 219 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 220 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 221 222 /* other nps modes are taken as nps1 */ 223 if (nps == AMDGPU_NPS2_PARTITION_MODE) { 224 loop_bits[0] = UMC_V12_0_PA_CH5_BIT; 225 loop_bits[1] = UMC_V12_0_PA_C2_BIT; 226 loop_bits[2] = UMC_V12_0_PA_B1_BIT; 227 loop_bits[3] = UMC_V12_0_PA_R12_BIT; 228 } 229 230 if (nps == AMDGPU_NPS4_PARTITION_MODE) { 231 loop_bits[0] = UMC_V12_0_PA_CH4_BIT; 232 loop_bits[1] = UMC_V12_0_PA_CH5_BIT; 233 loop_bits[2] = UMC_V12_0_PA_B0_BIT; 234 loop_bits[3] = UMC_V12_0_PA_R11_BIT; 235 } 236 237 soc_pa = paddr_out->pa.pa; 238 channel_index = paddr_out->pa.channel_idx; 239 /* clear loop bits in soc physical address */ 240 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 241 soc_pa &= ~BIT_ULL(loop_bits[i]); 242 243 paddr_out->pa.pa = soc_pa; 244 /* get column bit 0 and 1 in mca address */ 245 col_lower = (err_addr >> 1) & 0x3ULL; 246 /* MA_R13_BIT will be handled later */ 247 row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL; 248 249 if (!err_data && !dump_addr) 250 goto out; 251 252 /* loop for all possibilities of retired bits */ 253 for (column = 0; column < UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; column++) { 254 soc_pa = paddr_out->pa.pa; 255 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 256 soc_pa |= (((column >> i) & 0x1ULL) << loop_bits[i]); 257 258 col = ((column & 0x7) << 2) | col_lower; 259 /* add row bit 13 */ 260 row = ((column >> 3) << 13) | row_lower; 261 262 if (dump_addr) 263 dev_info(adev->dev, 264 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 265 soc_pa, row, col, bank, channel_index); 266 267 if (err_data) 268 amdgpu_umc_fill_error_record(err_data, err_addr, 269 soc_pa, channel_index, umc_inst); 270 } 271 272 out: 273 return ret; 274 } 275 276 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 277 uint32_t node_inst, uint32_t umc_inst, 278 uint32_t ch_inst, void *data) 279 { 280 struct ras_err_data *err_data = (struct ras_err_data *)data; 281 struct ta_ras_query_address_input addr_in; 282 uint64_t mc_umc_status_addr; 283 uint64_t mc_umc_status, err_addr; 284 uint64_t mc_umc_addrt0; 285 uint64_t umc_reg_offset = 286 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 287 288 mc_umc_status_addr = 289 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 290 291 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 292 293 if (mc_umc_status == 0) 294 return 0; 295 296 if (!err_data->err_addr) { 297 /* clear umc status */ 298 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 299 300 return 0; 301 } 302 303 /* calculate error address if ue error is detected */ 304 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) || 305 umc_v12_0_is_deferred_error(adev, mc_umc_status)) { 306 mc_umc_addrt0 = 307 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 308 309 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 310 311 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 312 313 if (!adev->aid_mask && 314 adev->smuio.funcs && 315 adev->smuio.funcs->get_socket_id) 316 addr_in.ma.socket_id = adev->smuio.funcs->get_socket_id(adev); 317 else 318 addr_in.ma.socket_id = 0; 319 320 addr_in.ma.err_addr = err_addr; 321 addr_in.ma.ch_inst = ch_inst; 322 addr_in.ma.umc_inst = umc_inst; 323 addr_in.ma.node_inst = node_inst; 324 325 umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL, true); 326 } 327 328 /* clear umc status */ 329 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 330 331 return 0; 332 } 333 334 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 335 void *ras_error_status) 336 { 337 amdgpu_umc_loop_channels(adev, 338 umc_v12_0_query_error_address, ras_error_status); 339 } 340 341 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 342 uint32_t node_inst, uint32_t umc_inst, 343 uint32_t ch_inst, void *data) 344 { 345 uint32_t odecc_cnt_sel; 346 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 347 uint64_t umc_reg_offset = 348 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 349 350 odecc_cnt_sel_addr = 351 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 352 odecc_err_cnt_addr = 353 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 354 355 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 356 357 /* set ce error interrupt type to APIC based interrupt */ 358 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 359 OdEccErrInt, 0x1); 360 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 361 362 /* set error count to initial value */ 363 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 364 365 return 0; 366 } 367 368 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, 369 enum amdgpu_mca_error_type type, void *ras_error_status) 370 { 371 uint64_t mc_umc_status = *(uint64_t *)ras_error_status; 372 373 switch (type) { 374 case AMDGPU_MCA_ERROR_TYPE_UE: 375 return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); 376 case AMDGPU_MCA_ERROR_TYPE_CE: 377 return umc_v12_0_is_correctable_error(adev, mc_umc_status); 378 case AMDGPU_MCA_ERROR_TYPE_DE: 379 return umc_v12_0_is_deferred_error(adev, mc_umc_status); 380 default: 381 return false; 382 } 383 384 return false; 385 } 386 387 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 388 { 389 amdgpu_umc_loop_channels(adev, 390 umc_v12_0_err_cnt_init_per_channel, NULL); 391 } 392 393 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 394 { 395 /* 396 * Force return true, because regUMCCH0_EccCtrl 397 * is not accessible from host side 398 */ 399 return true; 400 } 401 402 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 403 .query_ras_error_count = umc_v12_0_query_ras_error_count, 404 .query_ras_error_address = umc_v12_0_query_ras_error_address, 405 }; 406 407 static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 408 enum aca_smu_type type, void *data) 409 { 410 struct amdgpu_device *adev = handle->adev; 411 struct aca_bank_info info; 412 enum aca_error_type err_type; 413 u64 status, count; 414 u32 ext_error_code; 415 int ret; 416 417 status = bank->regs[ACA_REG_IDX_STATUS]; 418 if (umc_v12_0_is_deferred_error(adev, status)) 419 err_type = ACA_ERROR_TYPE_DEFERRED; 420 else if (umc_v12_0_is_uncorrectable_error(adev, status)) 421 err_type = ACA_ERROR_TYPE_UE; 422 else if (umc_v12_0_is_correctable_error(adev, status)) 423 err_type = ACA_ERROR_TYPE_CE; 424 else 425 return 0; 426 bank->aca_err_type = err_type; 427 428 ret = aca_bank_info_decode(bank, &info); 429 if (ret) 430 return ret; 431 432 amdgpu_umc_update_ecc_status(adev, 433 bank->regs[ACA_REG_IDX_STATUS], 434 bank->regs[ACA_REG_IDX_IPID], 435 bank->regs[ACA_REG_IDX_ADDR]); 436 437 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 438 count = ext_error_code == 0 ? 439 ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]) : 1ULL; 440 441 return aca_error_cache_log_bank_error(handle, &info, err_type, count); 442 } 443 444 static const struct aca_bank_ops umc_v12_0_aca_bank_ops = { 445 .aca_bank_parser = umc_v12_0_aca_bank_parser, 446 }; 447 448 const struct aca_info umc_v12_0_aca_info = { 449 .hwip = ACA_HWIP_TYPE_UMC, 450 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK, 451 .bank_ops = &umc_v12_0_aca_bank_ops, 452 }; 453 454 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 455 { 456 int ret; 457 458 ret = amdgpu_umc_ras_late_init(adev, ras_block); 459 if (ret) 460 return ret; 461 462 ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC, 463 &umc_v12_0_aca_info, NULL); 464 if (ret) 465 return ret; 466 467 return 0; 468 } 469 470 static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, 471 uint64_t status, uint64_t ipid, uint64_t addr) 472 { 473 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 474 uint16_t hwid, mcatype; 475 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 476 uint64_t err_addr, pa_addr = 0; 477 struct ras_ecc_err *ecc_err; 478 struct ta_ras_query_address_output addr_out; 479 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 480 uint32_t shift_bit = UMC_V12_0_PA_C4_BIT; 481 int count, ret, i; 482 483 hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); 484 mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); 485 486 if ((hwid != MCA_UMC_HWID_V12_0) || (mcatype != MCA_UMC_MCATYPE_V12_0)) 487 return 0; 488 489 if (!status) 490 return 0; 491 492 if (!umc_v12_0_is_deferred_error(adev, status)) 493 return 0; 494 495 err_addr = REG_GET_FIELD(addr, 496 MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 497 498 dev_dbg(adev->dev, 499 "UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n", 500 ipid, 501 MCA_IPID_2_SOCKET_ID(ipid), 502 MCA_IPID_2_DIE_ID(ipid), 503 MCA_IPID_2_UMC_INST(ipid), 504 MCA_IPID_2_UMC_CH(ipid), 505 err_addr); 506 507 ret = amdgpu_umc_mca_to_addr(adev, 508 err_addr, MCA_IPID_2_UMC_CH(ipid), 509 MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid), 510 MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true); 511 if (ret) 512 return ret; 513 514 ecc_err = kzalloc(sizeof(*ecc_err), GFP_KERNEL); 515 if (!ecc_err) 516 return -ENOMEM; 517 518 pa_addr = addr_out.pa.pa; 519 ecc_err->status = status; 520 ecc_err->ipid = ipid; 521 ecc_err->addr = addr; 522 ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT; 523 ecc_err->channel_idx = addr_out.pa.channel_idx; 524 525 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 526 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 527 528 if (nps == AMDGPU_NPS2_PARTITION_MODE) 529 shift_bit = UMC_V12_0_PA_B1_BIT; 530 if (nps == AMDGPU_NPS4_PARTITION_MODE) 531 shift_bit = UMC_V12_0_PA_B0_BIT; 532 533 /* If converted pa_pfn is 0, use pa C4 pfn. */ 534 if (!ecc_err->pa_pfn) 535 ecc_err->pa_pfn = BIT_ULL(shift_bit) >> AMDGPU_GPU_PAGE_SHIFT; 536 537 ret = amdgpu_umc_logs_ecc_err(adev, &con->umc_ecc_log.de_page_tree, ecc_err); 538 if (ret) { 539 if (ret == -EEXIST) 540 con->umc_ecc_log.de_queried_count++; 541 else 542 dev_err(adev->dev, "Fail to log ecc error! ret:%d\n", ret); 543 544 kfree(ecc_err); 545 return ret; 546 } 547 548 con->umc_ecc_log.de_queried_count++; 549 550 memset(page_pfn, 0, sizeof(page_pfn)); 551 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 552 pa_addr, 553 page_pfn, ARRAY_SIZE(page_pfn)); 554 if (count <= 0) { 555 dev_warn(adev->dev, "Fail to convert error address! count:%d\n", count); 556 return 0; 557 } 558 559 /* Reserve memory */ 560 for (i = 0; i < count; i++) 561 amdgpu_ras_reserve_page(adev, page_pfn[i]); 562 563 /* The problem case is as follows: 564 * 1. GPU A triggers a gpu ras reset, and GPU A drives 565 * GPU B to also perform a gpu ras reset. 566 * 2. After gpu B ras reset started, gpu B queried a DE 567 * data. Since the DE data was queried in the ras reset 568 * thread instead of the page retirement thread, bad 569 * page retirement work would not be triggered. Then 570 * even if all gpu resets are completed, the bad pages 571 * will be cached in RAM until GPU B's bad page retirement 572 * work is triggered again and then saved to eeprom. 573 * Trigger delayed work to save the bad pages to eeprom in time 574 * after gpu ras reset is completed. 575 */ 576 if (amdgpu_ras_in_recovery(adev)) 577 schedule_delayed_work(&con->page_retirement_dwork, 578 msecs_to_jiffies(DELAYED_TIME_FOR_GPU_RESET)); 579 580 return 0; 581 } 582 583 static int umc_v12_0_fill_error_record(struct amdgpu_device *adev, 584 struct ras_ecc_err *ecc_err, void *ras_error_status) 585 { 586 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 587 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 588 int ret, i, count; 589 590 if (!err_data || !ecc_err) 591 return -EINVAL; 592 593 memset(page_pfn, 0, sizeof(page_pfn)); 594 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 595 ecc_err->pa_pfn << AMDGPU_GPU_PAGE_SHIFT, 596 page_pfn, ARRAY_SIZE(page_pfn)); 597 598 for (i = 0; i < count; i++) { 599 ret = amdgpu_umc_fill_error_record(err_data, 600 ecc_err->addr, 601 page_pfn[i] << AMDGPU_GPU_PAGE_SHIFT, 602 ecc_err->channel_idx, 603 MCA_IPID_2_UMC_INST(ecc_err->ipid)); 604 if (ret) 605 break; 606 } 607 608 err_data->de_count++; 609 610 return ret; 611 } 612 613 static void umc_v12_0_query_ras_ecc_err_addr(struct amdgpu_device *adev, 614 void *ras_error_status) 615 { 616 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 617 struct ras_ecc_err *entries[MAX_ECC_NUM_PER_RETIREMENT]; 618 struct radix_tree_root *ecc_tree; 619 int new_detected, ret, i; 620 621 ecc_tree = &con->umc_ecc_log.de_page_tree; 622 623 mutex_lock(&con->umc_ecc_log.lock); 624 new_detected = radix_tree_gang_lookup_tag(ecc_tree, (void **)entries, 625 0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG); 626 for (i = 0; i < new_detected; i++) { 627 if (!entries[i]) 628 continue; 629 630 ret = umc_v12_0_fill_error_record(adev, entries[i], ras_error_status); 631 if (ret) { 632 dev_err(adev->dev, "Fail to fill umc error record, ret:%d\n", ret); 633 break; 634 } 635 radix_tree_tag_clear(ecc_tree, 636 entries[i]->pa_pfn, UMC_ECC_NEW_DETECTED_TAG); 637 } 638 mutex_unlock(&con->umc_ecc_log.lock); 639 } 640 641 static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev, 642 uint64_t mca_addr, uint64_t retired_page) 643 { 644 uint32_t die = 0; 645 646 /* we only calculate die id for nps1 mode right now */ 647 die += ((((retired_page >> 12) & 0x1ULL)^ 648 ((retired_page >> 20) & 0x1ULL) ^ 649 ((retired_page >> 27) & 0x1ULL) ^ 650 ((retired_page >> 34) & 0x1ULL) ^ 651 ((retired_page >> 41) & 0x1ULL)) << 0); 652 653 /* the original PA_C4 and PA_R13 may be cleared in retired_page, so 654 * get them from mca_addr. 655 */ 656 die += ((((retired_page >> 13) & 0x1ULL) ^ 657 ((mca_addr >> 5) & 0x1ULL) ^ 658 ((retired_page >> 28) & 0x1ULL) ^ 659 ((mca_addr >> 23) & 0x1ULL) ^ 660 ((retired_page >> 42) & 0x1ULL)) << 1); 661 die &= 3; 662 663 return die; 664 } 665 666 struct amdgpu_umc_ras umc_v12_0_ras = { 667 .ras_block = { 668 .hw_ops = &umc_v12_0_ras_hw_ops, 669 .ras_late_init = umc_v12_0_ras_late_init, 670 }, 671 .err_cnt_init = umc_v12_0_err_cnt_init, 672 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 673 .ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr, 674 .check_ecc_err_status = umc_v12_0_check_ecc_err_status, 675 .update_ecc_status = umc_v12_0_update_ecc_status, 676 .convert_ras_err_addr = umc_v12_0_convert_error_address, 677 .get_die_id_from_pa = umc_v12_0_get_die_id, 678 }; 679 680