1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 30 const uint32_t 31 umc_v12_0_channel_idx_tbl[] 32 [UMC_V12_0_UMC_INSTANCE_NUM] 33 [UMC_V12_0_CHANNEL_INSTANCE_NUM] = { 34 {{3, 7, 11, 15, 2, 6, 10, 14}, {1, 5, 9, 13, 0, 4, 8, 12}, 35 {19, 23, 27, 31, 18, 22, 26, 30}, {17, 21, 25, 29, 16, 20, 24, 28}}, 36 {{47, 43, 39, 35, 46, 42, 38, 34}, {45, 41, 37, 33, 44, 40, 36, 32}, 37 {63, 59, 55, 51, 62, 58, 54, 50}, {61, 57, 53, 49, 60, 56, 52, 48}}, 38 {{79, 75, 71, 67, 78, 74, 70, 66}, {77, 73, 69, 65, 76, 72, 68, 64}, 39 {95, 91, 87, 83, 94, 90, 86, 82}, {93, 89, 85, 81, 92, 88, 84, 80}}, 40 {{99, 103, 107, 111, 98, 102, 106, 110}, {97, 101, 105, 109, 96, 100, 104, 108}, 41 {115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}} 42 }; 43 44 /* mapping of MCA error address to normalized address */ 45 static const uint32_t umc_v12_0_ma2na_mapping[] = { 46 0, 5, 6, 8, 9, 14, 12, 13, 47 10, 11, 15, 16, 17, 18, 19, 20, 48 21, 22, 23, 24, 25, 26, 27, 28, 49 24, 7, 29, 30, 50 }; 51 52 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 53 uint32_t node_inst, 54 uint32_t umc_inst, 55 uint32_t ch_inst) 56 { 57 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 58 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 59 60 umc_inst = index / 4; 61 ch_inst = index % 4; 62 63 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 64 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 65 } 66 67 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 68 uint32_t node_inst, uint32_t umc_inst, 69 uint32_t ch_inst, void *data) 70 { 71 uint64_t odecc_err_cnt_addr; 72 uint64_t umc_reg_offset = 73 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 74 75 odecc_err_cnt_addr = 76 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 77 78 /* clear error count */ 79 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 80 UMC_V12_0_CE_CNT_INIT); 81 82 return 0; 83 } 84 85 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 86 { 87 amdgpu_umc_loop_channels(adev, 88 umc_v12_0_reset_error_count_per_channel, NULL); 89 } 90 91 static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev, 92 uint64_t umc_reg_offset, 93 unsigned long *error_count) 94 { 95 uint64_t mc_umc_status; 96 uint64_t mc_umc_status_addr; 97 98 mc_umc_status_addr = 99 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 100 101 /* Rely on MCUMC_STATUS for correctable error counter 102 * MCUMC_STATUS is a 64 bit register 103 */ 104 mc_umc_status = 105 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 106 107 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 108 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) 109 *error_count += 1; 110 } 111 112 static void umc_v12_0_query_uncorrectable_error_count(struct amdgpu_device *adev, 113 uint64_t umc_reg_offset, 114 unsigned long *error_count) 115 { 116 uint64_t mc_umc_status; 117 uint64_t mc_umc_status_addr; 118 119 mc_umc_status_addr = 120 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 121 122 /* Check the MCUMC_STATUS. */ 123 mc_umc_status = 124 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 125 126 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 127 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || 128 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || 129 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 130 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 131 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) 132 *error_count += 1; 133 } 134 135 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 136 uint32_t node_inst, uint32_t umc_inst, 137 uint32_t ch_inst, void *data) 138 { 139 struct ras_err_data *err_data = (struct ras_err_data *)data; 140 uint64_t umc_reg_offset = 141 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 142 143 umc_v12_0_query_correctable_error_count(adev, 144 umc_reg_offset, 145 &(err_data->ce_count)); 146 umc_v12_0_query_uncorrectable_error_count(adev, 147 umc_reg_offset, 148 &(err_data->ue_count)); 149 150 return 0; 151 } 152 153 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 154 void *ras_error_status) 155 { 156 amdgpu_umc_loop_channels(adev, 157 umc_v12_0_query_error_count, ras_error_status); 158 159 umc_v12_0_reset_error_count(adev); 160 } 161 162 static bool umc_v12_0_bit_wise_xor(uint32_t val) 163 { 164 bool result = 0; 165 int i; 166 167 for (i = 0; i < 32; i++) 168 result = result ^ ((val >> i) & 0x1); 169 170 return result; 171 } 172 173 static void umc_v12_0_convert_error_address(struct amdgpu_device *adev, 174 struct ras_err_data *err_data, uint64_t err_addr, 175 uint32_t ch_inst, uint32_t umc_inst, 176 uint32_t node_inst) 177 { 178 uint32_t channel_index, i; 179 uint64_t soc_pa, na, retired_page, column; 180 uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row, row_xor; 181 uint32_t bank0, bank1, bank2, bank3, bank; 182 183 bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL; 184 bank_hash1 = (err_addr >> UMC_V12_0_MCA_B1_BIT) & 0x1ULL; 185 bank_hash2 = (err_addr >> UMC_V12_0_MCA_B2_BIT) & 0x1ULL; 186 bank_hash3 = (err_addr >> UMC_V12_0_MCA_B3_BIT) & 0x1ULL; 187 col = (err_addr >> 1) & 0x1fULL; 188 row = (err_addr >> 10) & 0x3fffULL; 189 190 /* apply bank hash algorithm */ 191 bank0 = 192 bank_hash0 ^ (UMC_V12_0_XOR_EN0 & 193 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR0) ^ 194 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR0)))); 195 bank1 = 196 bank_hash1 ^ (UMC_V12_0_XOR_EN1 & 197 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR1) ^ 198 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR1)))); 199 bank2 = 200 bank_hash2 ^ (UMC_V12_0_XOR_EN2 & 201 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR2) ^ 202 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR2)))); 203 bank3 = 204 bank_hash3 ^ (UMC_V12_0_XOR_EN3 & 205 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR3) ^ 206 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR3)))); 207 208 bank = bank0 | (bank1 << 1) | (bank2 << 2) | (bank3 << 3); 209 err_addr &= ~0x3c0ULL; 210 err_addr |= (bank << UMC_V12_0_MCA_B0_BIT); 211 212 na = 0x0; 213 /* convert mca error address to normalized address */ 214 for (i = 1; i < ARRAY_SIZE(umc_v12_0_ma2na_mapping); i++) 215 na |= ((err_addr >> i) & 0x1ULL) << umc_v12_0_ma2na_mapping[i]; 216 217 channel_index = 218 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * 219 adev->umc.channel_inst_num + 220 umc_inst * adev->umc.channel_inst_num + 221 ch_inst]; 222 /* translate umc channel address to soc pa, 3 parts are included */ 223 soc_pa = ADDR_OF_32KB_BLOCK(na) | 224 ADDR_OF_256B_BLOCK(channel_index) | 225 OFFSET_IN_256B_BLOCK(na); 226 227 /* the umc channel bits are not original values, they are hashed */ 228 UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa); 229 230 /* clear [C3 C2] in soc physical address */ 231 soc_pa &= ~(0x3ULL << UMC_V12_0_PA_C2_BIT); 232 /* clear [C4] in soc physical address */ 233 soc_pa &= ~(0x1ULL << UMC_V12_0_PA_C4_BIT); 234 235 row_xor = row ^ (0x1ULL << 13); 236 /* loop for all possibilities of [C4 C3 C2] */ 237 for (column = 0; column < UMC_V12_0_NA_MAP_PA_NUM; column++) { 238 retired_page = soc_pa | ((column & 0x3) << UMC_V12_0_PA_C2_BIT); 239 retired_page |= (((column & 0x4) >> 2) << UMC_V12_0_PA_C4_BIT); 240 /* include column bit 0 and 1 */ 241 col &= 0x3; 242 col |= (column << 2); 243 dev_info(adev->dev, 244 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 245 retired_page, row, col, bank, channel_index); 246 amdgpu_umc_fill_error_record(err_data, err_addr, 247 retired_page, channel_index, umc_inst); 248 249 /* shift R13 bit */ 250 retired_page ^= (0x1ULL << UMC_V12_0_PA_R13_BIT); 251 dev_info(adev->dev, 252 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 253 retired_page, row_xor, col, bank, channel_index); 254 amdgpu_umc_fill_error_record(err_data, err_addr, 255 retired_page, channel_index, umc_inst); 256 } 257 } 258 259 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 260 uint32_t node_inst, uint32_t umc_inst, 261 uint32_t ch_inst, void *data) 262 { 263 uint64_t mc_umc_status_addr; 264 uint64_t mc_umc_status, err_addr; 265 uint64_t mc_umc_addrt0; 266 struct ras_err_data *err_data = (struct ras_err_data *)data; 267 uint64_t umc_reg_offset = 268 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 269 270 mc_umc_status_addr = 271 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 272 273 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 274 275 if (mc_umc_status == 0) 276 return 0; 277 278 if (!err_data->err_addr) { 279 /* clear umc status */ 280 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 281 282 return 0; 283 } 284 285 /* calculate error address if ue error is detected */ 286 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 287 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && 288 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { 289 290 mc_umc_addrt0 = 291 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 292 293 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 294 295 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 296 297 umc_v12_0_convert_error_address(adev, err_data, err_addr, 298 ch_inst, umc_inst, node_inst); 299 } 300 301 /* clear umc status */ 302 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 303 304 return 0; 305 } 306 307 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 308 void *ras_error_status) 309 { 310 amdgpu_umc_loop_channels(adev, 311 umc_v12_0_query_error_address, ras_error_status); 312 } 313 314 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 315 uint32_t node_inst, uint32_t umc_inst, 316 uint32_t ch_inst, void *data) 317 { 318 uint32_t odecc_cnt_sel; 319 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 320 uint64_t umc_reg_offset = 321 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 322 323 odecc_cnt_sel_addr = 324 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 325 odecc_err_cnt_addr = 326 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 327 328 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 329 330 /* set ce error interrupt type to APIC based interrupt */ 331 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 332 OdEccErrInt, 0x1); 333 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 334 335 /* set error count to initial value */ 336 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 337 338 return 0; 339 } 340 341 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 342 { 343 amdgpu_umc_loop_channels(adev, 344 umc_v12_0_err_cnt_init_per_channel, NULL); 345 } 346 347 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 348 { 349 /* 350 * Force return true, because regUMCCH0_EccCtrl 351 * is not accessible from host side 352 */ 353 return true; 354 } 355 356 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 357 .query_ras_error_count = umc_v12_0_query_ras_error_count, 358 .query_ras_error_address = umc_v12_0_query_ras_error_address, 359 }; 360 361 struct amdgpu_umc_ras umc_v12_0_ras = { 362 .ras_block = { 363 .hw_ops = &umc_v12_0_ras_hw_ops, 364 }, 365 .err_cnt_init = umc_v12_0_err_cnt_init, 366 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 367 }; 368