1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 #define MAX_ECC_NUM_PER_RETIREMENT 32 32 #define DELAYED_TIME_FOR_GPU_RESET 1000 //ms 33 34 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 35 uint32_t node_inst, 36 uint32_t umc_inst, 37 uint32_t ch_inst) 38 { 39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 40 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 41 42 umc_inst = index / 4; 43 ch_inst = index % 4; 44 45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 46 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 47 } 48 49 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 50 uint32_t node_inst, uint32_t umc_inst, 51 uint32_t ch_inst, void *data) 52 { 53 uint64_t odecc_err_cnt_addr; 54 uint64_t umc_reg_offset = 55 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 56 57 odecc_err_cnt_addr = 58 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 59 60 /* clear error count */ 61 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 62 UMC_V12_0_CE_CNT_INIT); 63 64 return 0; 65 } 66 67 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 68 { 69 amdgpu_umc_loop_channels(adev, 70 umc_v12_0_reset_error_count_per_channel, NULL); 71 } 72 73 bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 74 { 75 dev_dbg(adev->dev, 76 "MCA_UMC_STATUS(0x%llx): Val:%llu, Poison:%llu, Deferred:%llu, PCC:%llu, UC:%llu, TCC:%llu\n", 77 mc_umc_status, 78 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val), 79 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison), 80 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred), 81 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC), 82 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC), 83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) 84 ); 85 86 return (amdgpu_ras_is_poison_mode_supported(adev) && 87 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 88 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) || 89 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Poison) == 1))); 90 } 91 92 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 93 { 94 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 95 return false; 96 97 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 98 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 99 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 100 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 101 } 102 103 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 104 { 105 if (umc_v12_0_is_deferred_error(adev, mc_umc_status)) 106 return false; 107 108 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 109 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 110 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 111 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 112 /* Identify data parity error in replay mode */ 113 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 114 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 115 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 116 } 117 118 static void umc_v12_0_query_error_count_per_type(struct amdgpu_device *adev, 119 uint64_t umc_reg_offset, 120 unsigned long *error_count, 121 check_error_type_func error_type_func) 122 { 123 uint64_t mc_umc_status; 124 uint64_t mc_umc_status_addr; 125 126 mc_umc_status_addr = 127 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 128 129 /* Check MCUMC_STATUS */ 130 mc_umc_status = 131 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 132 133 if (error_type_func(adev, mc_umc_status)) 134 *error_count += 1; 135 } 136 137 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 138 uint32_t node_inst, uint32_t umc_inst, 139 uint32_t ch_inst, void *data) 140 { 141 struct ras_err_data *err_data = (struct ras_err_data *)data; 142 unsigned long ue_count = 0, ce_count = 0, de_count = 0; 143 144 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], 145 * which can be used as die ID directly */ 146 struct amdgpu_smuio_mcm_config_info mcm_info = { 147 .socket_id = adev->smuio.funcs->get_socket_id(adev), 148 .die_id = node_inst, 149 }; 150 151 uint64_t umc_reg_offset = 152 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 153 154 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 155 &ce_count, umc_v12_0_is_correctable_error); 156 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 157 &ue_count, umc_v12_0_is_uncorrectable_error); 158 umc_v12_0_query_error_count_per_type(adev, umc_reg_offset, 159 &de_count, umc_v12_0_is_deferred_error); 160 161 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 162 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 163 amdgpu_ras_error_statistic_de_count(err_data, &mcm_info, de_count); 164 165 return 0; 166 } 167 168 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 169 void *ras_error_status) 170 { 171 amdgpu_umc_loop_channels(adev, 172 umc_v12_0_query_error_count, ras_error_status); 173 174 umc_v12_0_reset_error_count(adev); 175 } 176 177 static int umc_v12_0_convert_error_address(struct amdgpu_device *adev, 178 struct ras_err_data *err_data, 179 struct ta_ras_query_address_input *addr_in, 180 struct ta_ras_query_address_output *addr_out, 181 bool dump_addr) 182 { 183 uint32_t col, col_lower, row, row_lower, bank; 184 uint32_t channel_index = 0, umc_inst = 0; 185 uint32_t i, loop_bits[UMC_V12_0_RETIRE_LOOP_BITS]; 186 uint64_t soc_pa, column, err_addr; 187 struct ta_ras_query_address_output addr_out_tmp; 188 struct ta_ras_query_address_output *paddr_out; 189 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 190 int ret = 0; 191 192 if (!addr_out) 193 paddr_out = &addr_out_tmp; 194 else 195 paddr_out = addr_out; 196 197 err_addr = bank = 0; 198 if (addr_in) { 199 err_addr = addr_in->ma.err_addr; 200 addr_in->addr_type = TA_RAS_MCA_TO_PA; 201 ret = psp_ras_query_address(&adev->psp, addr_in, paddr_out); 202 if (ret) { 203 dev_warn(adev->dev, "Failed to query RAS physical address for 0x%llx", 204 err_addr); 205 206 goto out; 207 } 208 209 bank = paddr_out->pa.bank; 210 /* no need to care about umc inst if addr_in is NULL */ 211 umc_inst = addr_in->ma.umc_inst; 212 } 213 214 loop_bits[0] = UMC_V12_0_PA_C2_BIT; 215 loop_bits[1] = UMC_V12_0_PA_C3_BIT; 216 loop_bits[2] = UMC_V12_0_PA_C4_BIT; 217 loop_bits[3] = UMC_V12_0_PA_R13_BIT; 218 219 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 220 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 221 222 /* other nps modes are taken as nps1 */ 223 if (nps == AMDGPU_NPS4_PARTITION_MODE) { 224 loop_bits[0] = UMC_V12_0_PA_CH4_BIT; 225 loop_bits[1] = UMC_V12_0_PA_CH5_BIT; 226 loop_bits[2] = UMC_V12_0_PA_B0_BIT; 227 loop_bits[3] = UMC_V12_0_PA_R11_BIT; 228 } 229 230 soc_pa = paddr_out->pa.pa; 231 channel_index = paddr_out->pa.channel_idx; 232 /* clear loop bits in soc physical address */ 233 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 234 soc_pa &= ~BIT_ULL(loop_bits[i]); 235 236 paddr_out->pa.pa = soc_pa; 237 /* get column bit 0 and 1 in mca address */ 238 col_lower = (err_addr >> 1) & 0x3ULL; 239 /* MA_R13_BIT will be handled later */ 240 row_lower = (err_addr >> UMC_V12_0_MA_R0_BIT) & 0x1fffULL; 241 242 if (!err_data && !dump_addr) 243 goto out; 244 245 /* loop for all possibilities of retired bits */ 246 for (column = 0; column < UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL; column++) { 247 soc_pa = paddr_out->pa.pa; 248 for (i = 0; i < UMC_V12_0_RETIRE_LOOP_BITS; i++) 249 soc_pa |= (((column >> i) & 0x1ULL) << loop_bits[i]); 250 251 col = ((column & 0x7) << 2) | col_lower; 252 /* add row bit 13 */ 253 row = ((column >> 3) << 13) | row_lower; 254 255 if (dump_addr) 256 dev_info(adev->dev, 257 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 258 soc_pa, row, col, bank, channel_index); 259 260 if (err_data) 261 amdgpu_umc_fill_error_record(err_data, err_addr, 262 soc_pa, channel_index, umc_inst); 263 } 264 265 out: 266 return ret; 267 } 268 269 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 270 uint32_t node_inst, uint32_t umc_inst, 271 uint32_t ch_inst, void *data) 272 { 273 struct ras_err_data *err_data = (struct ras_err_data *)data; 274 struct ta_ras_query_address_input addr_in; 275 uint64_t mc_umc_status_addr; 276 uint64_t mc_umc_status, err_addr; 277 uint64_t mc_umc_addrt0; 278 uint64_t umc_reg_offset = 279 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 280 281 mc_umc_status_addr = 282 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 283 284 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 285 286 if (mc_umc_status == 0) 287 return 0; 288 289 if (!err_data->err_addr) { 290 /* clear umc status */ 291 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 292 293 return 0; 294 } 295 296 /* calculate error address if ue error is detected */ 297 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status) || 298 umc_v12_0_is_deferred_error(adev, mc_umc_status)) { 299 mc_umc_addrt0 = 300 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 301 302 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 303 304 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 305 306 if (!adev->aid_mask && 307 adev->smuio.funcs && 308 adev->smuio.funcs->get_socket_id) 309 addr_in.ma.socket_id = adev->smuio.funcs->get_socket_id(adev); 310 else 311 addr_in.ma.socket_id = 0; 312 313 addr_in.ma.err_addr = err_addr; 314 addr_in.ma.ch_inst = ch_inst; 315 addr_in.ma.umc_inst = umc_inst; 316 addr_in.ma.node_inst = node_inst; 317 318 umc_v12_0_convert_error_address(adev, err_data, &addr_in, NULL, true); 319 } 320 321 /* clear umc status */ 322 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 323 324 return 0; 325 } 326 327 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 328 void *ras_error_status) 329 { 330 amdgpu_umc_loop_channels(adev, 331 umc_v12_0_query_error_address, ras_error_status); 332 } 333 334 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 335 uint32_t node_inst, uint32_t umc_inst, 336 uint32_t ch_inst, void *data) 337 { 338 uint32_t odecc_cnt_sel; 339 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 340 uint64_t umc_reg_offset = 341 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 342 343 odecc_cnt_sel_addr = 344 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 345 odecc_err_cnt_addr = 346 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 347 348 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 349 350 /* set ce error interrupt type to APIC based interrupt */ 351 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 352 OdEccErrInt, 0x1); 353 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 354 355 /* set error count to initial value */ 356 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 357 358 return 0; 359 } 360 361 static bool umc_v12_0_check_ecc_err_status(struct amdgpu_device *adev, 362 enum amdgpu_mca_error_type type, void *ras_error_status) 363 { 364 uint64_t mc_umc_status = *(uint64_t *)ras_error_status; 365 366 switch (type) { 367 case AMDGPU_MCA_ERROR_TYPE_UE: 368 return umc_v12_0_is_uncorrectable_error(adev, mc_umc_status); 369 case AMDGPU_MCA_ERROR_TYPE_CE: 370 return umc_v12_0_is_correctable_error(adev, mc_umc_status); 371 case AMDGPU_MCA_ERROR_TYPE_DE: 372 return umc_v12_0_is_deferred_error(adev, mc_umc_status); 373 default: 374 return false; 375 } 376 377 return false; 378 } 379 380 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 381 { 382 amdgpu_umc_loop_channels(adev, 383 umc_v12_0_err_cnt_init_per_channel, NULL); 384 } 385 386 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 387 { 388 /* 389 * Force return true, because regUMCCH0_EccCtrl 390 * is not accessible from host side 391 */ 392 return true; 393 } 394 395 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 396 .query_ras_error_count = umc_v12_0_query_ras_error_count, 397 .query_ras_error_address = umc_v12_0_query_ras_error_address, 398 }; 399 400 static int umc_v12_0_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, 401 enum aca_smu_type type, void *data) 402 { 403 struct amdgpu_device *adev = handle->adev; 404 struct aca_bank_info info; 405 enum aca_error_type err_type; 406 u64 status, count; 407 u32 ext_error_code; 408 int ret; 409 410 status = bank->regs[ACA_REG_IDX_STATUS]; 411 if (umc_v12_0_is_deferred_error(adev, status)) 412 err_type = ACA_ERROR_TYPE_DEFERRED; 413 else if (umc_v12_0_is_uncorrectable_error(adev, status)) 414 err_type = ACA_ERROR_TYPE_UE; 415 else if (umc_v12_0_is_correctable_error(adev, status)) 416 err_type = ACA_ERROR_TYPE_CE; 417 else 418 return 0; 419 bank->aca_err_type = err_type; 420 421 ret = aca_bank_info_decode(bank, &info); 422 if (ret) 423 return ret; 424 425 amdgpu_umc_update_ecc_status(adev, 426 bank->regs[ACA_REG_IDX_STATUS], 427 bank->regs[ACA_REG_IDX_IPID], 428 bank->regs[ACA_REG_IDX_ADDR]); 429 430 ext_error_code = ACA_REG__STATUS__ERRORCODEEXT(status); 431 count = ext_error_code == 0 ? 432 ACA_REG__MISC0__ERRCNT(bank->regs[ACA_REG_IDX_MISC0]) : 1ULL; 433 434 return aca_error_cache_log_bank_error(handle, &info, err_type, count); 435 } 436 437 static const struct aca_bank_ops umc_v12_0_aca_bank_ops = { 438 .aca_bank_parser = umc_v12_0_aca_bank_parser, 439 }; 440 441 const struct aca_info umc_v12_0_aca_info = { 442 .hwip = ACA_HWIP_TYPE_UMC, 443 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK | ACA_ERROR_DEFERRED_MASK, 444 .bank_ops = &umc_v12_0_aca_bank_ops, 445 }; 446 447 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 448 { 449 int ret; 450 451 ret = amdgpu_umc_ras_late_init(adev, ras_block); 452 if (ret) 453 return ret; 454 455 ret = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__UMC, 456 &umc_v12_0_aca_info, NULL); 457 if (ret) 458 return ret; 459 460 return 0; 461 } 462 463 static int umc_v12_0_update_ecc_status(struct amdgpu_device *adev, 464 uint64_t status, uint64_t ipid, uint64_t addr) 465 { 466 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 467 uint16_t hwid, mcatype; 468 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 469 uint64_t err_addr, pa_addr = 0; 470 struct ras_ecc_err *ecc_err; 471 struct ta_ras_query_address_output addr_out; 472 enum amdgpu_memory_partition nps = AMDGPU_NPS1_PARTITION_MODE; 473 uint32_t shift_bit = UMC_V12_0_PA_C4_BIT; 474 int count, ret, i; 475 476 hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID); 477 mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType); 478 479 if ((hwid != MCA_UMC_HWID_V12_0) || (mcatype != MCA_UMC_MCATYPE_V12_0)) 480 return 0; 481 482 if (!status) 483 return 0; 484 485 if (!umc_v12_0_is_deferred_error(adev, status)) 486 return 0; 487 488 err_addr = REG_GET_FIELD(addr, 489 MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 490 491 dev_dbg(adev->dev, 492 "UMC:IPID:0x%llx, socket:%llu, aid:%llu, inst:%llu, ch:%llu, err_addr:0x%llx\n", 493 ipid, 494 MCA_IPID_2_SOCKET_ID(ipid), 495 MCA_IPID_2_DIE_ID(ipid), 496 MCA_IPID_2_UMC_INST(ipid), 497 MCA_IPID_2_UMC_CH(ipid), 498 err_addr); 499 500 ret = amdgpu_umc_mca_to_addr(adev, 501 err_addr, MCA_IPID_2_UMC_CH(ipid), 502 MCA_IPID_2_UMC_INST(ipid), MCA_IPID_2_DIE_ID(ipid), 503 MCA_IPID_2_SOCKET_ID(ipid), &addr_out, true); 504 if (ret) 505 return ret; 506 507 ecc_err = kzalloc(sizeof(*ecc_err), GFP_KERNEL); 508 if (!ecc_err) 509 return -ENOMEM; 510 511 pa_addr = addr_out.pa.pa; 512 ecc_err->status = status; 513 ecc_err->ipid = ipid; 514 ecc_err->addr = addr; 515 ecc_err->pa_pfn = pa_addr >> AMDGPU_GPU_PAGE_SHIFT; 516 ecc_err->channel_idx = addr_out.pa.channel_idx; 517 518 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 519 nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 520 if (nps == AMDGPU_NPS4_PARTITION_MODE) 521 shift_bit = UMC_V12_0_PA_B0_BIT; 522 523 /* If converted pa_pfn is 0, use pa C4 pfn. */ 524 if (!ecc_err->pa_pfn) 525 ecc_err->pa_pfn = BIT_ULL(shift_bit) >> AMDGPU_GPU_PAGE_SHIFT; 526 527 ret = amdgpu_umc_logs_ecc_err(adev, &con->umc_ecc_log.de_page_tree, ecc_err); 528 if (ret) { 529 if (ret == -EEXIST) 530 con->umc_ecc_log.de_queried_count++; 531 else 532 dev_err(adev->dev, "Fail to log ecc error! ret:%d\n", ret); 533 534 kfree(ecc_err); 535 return ret; 536 } 537 538 con->umc_ecc_log.de_queried_count++; 539 540 memset(page_pfn, 0, sizeof(page_pfn)); 541 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 542 pa_addr, 543 page_pfn, ARRAY_SIZE(page_pfn)); 544 if (count <= 0) { 545 dev_warn(adev->dev, "Fail to convert error address! count:%d\n", count); 546 return 0; 547 } 548 549 /* Reserve memory */ 550 for (i = 0; i < count; i++) 551 amdgpu_ras_reserve_page(adev, page_pfn[i]); 552 553 /* The problem case is as follows: 554 * 1. GPU A triggers a gpu ras reset, and GPU A drives 555 * GPU B to also perform a gpu ras reset. 556 * 2. After gpu B ras reset started, gpu B queried a DE 557 * data. Since the DE data was queried in the ras reset 558 * thread instead of the page retirement thread, bad 559 * page retirement work would not be triggered. Then 560 * even if all gpu resets are completed, the bad pages 561 * will be cached in RAM until GPU B's bad page retirement 562 * work is triggered again and then saved to eeprom. 563 * Trigger delayed work to save the bad pages to eeprom in time 564 * after gpu ras reset is completed. 565 */ 566 if (amdgpu_ras_in_recovery(adev)) 567 schedule_delayed_work(&con->page_retirement_dwork, 568 msecs_to_jiffies(DELAYED_TIME_FOR_GPU_RESET)); 569 570 return 0; 571 } 572 573 static int umc_v12_0_fill_error_record(struct amdgpu_device *adev, 574 struct ras_ecc_err *ecc_err, void *ras_error_status) 575 { 576 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 577 uint64_t page_pfn[UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL]; 578 int ret, i, count; 579 580 if (!err_data || !ecc_err) 581 return -EINVAL; 582 583 memset(page_pfn, 0, sizeof(page_pfn)); 584 count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, 585 ecc_err->pa_pfn << AMDGPU_GPU_PAGE_SHIFT, 586 page_pfn, ARRAY_SIZE(page_pfn)); 587 588 for (i = 0; i < count; i++) { 589 ret = amdgpu_umc_fill_error_record(err_data, 590 ecc_err->addr, 591 page_pfn[i] << AMDGPU_GPU_PAGE_SHIFT, 592 ecc_err->channel_idx, 593 MCA_IPID_2_UMC_INST(ecc_err->ipid)); 594 if (ret) 595 break; 596 } 597 598 err_data->de_count++; 599 600 return ret; 601 } 602 603 static void umc_v12_0_query_ras_ecc_err_addr(struct amdgpu_device *adev, 604 void *ras_error_status) 605 { 606 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 607 struct ras_ecc_err *entries[MAX_ECC_NUM_PER_RETIREMENT]; 608 struct radix_tree_root *ecc_tree; 609 int new_detected, ret, i; 610 611 ecc_tree = &con->umc_ecc_log.de_page_tree; 612 613 mutex_lock(&con->umc_ecc_log.lock); 614 new_detected = radix_tree_gang_lookup_tag(ecc_tree, (void **)entries, 615 0, ARRAY_SIZE(entries), UMC_ECC_NEW_DETECTED_TAG); 616 for (i = 0; i < new_detected; i++) { 617 if (!entries[i]) 618 continue; 619 620 ret = umc_v12_0_fill_error_record(adev, entries[i], ras_error_status); 621 if (ret) { 622 dev_err(adev->dev, "Fail to fill umc error record, ret:%d\n", ret); 623 break; 624 } 625 radix_tree_tag_clear(ecc_tree, 626 entries[i]->pa_pfn, UMC_ECC_NEW_DETECTED_TAG); 627 } 628 mutex_unlock(&con->umc_ecc_log.lock); 629 } 630 631 static uint32_t umc_v12_0_get_die_id(struct amdgpu_device *adev, 632 uint64_t mca_addr, uint64_t retired_page) 633 { 634 uint32_t die = 0; 635 636 /* we only calculate die id for nps1 mode right now */ 637 die += ((((retired_page >> 12) & 0x1ULL)^ 638 ((retired_page >> 20) & 0x1ULL) ^ 639 ((retired_page >> 27) & 0x1ULL) ^ 640 ((retired_page >> 34) & 0x1ULL) ^ 641 ((retired_page >> 41) & 0x1ULL)) << 0); 642 643 /* the original PA_C4 and PA_R13 may be cleared in retired_page, so 644 * get them from mca_addr. 645 */ 646 die += ((((retired_page >> 13) & 0x1ULL) ^ 647 ((mca_addr >> 5) & 0x1ULL) ^ 648 ((retired_page >> 28) & 0x1ULL) ^ 649 ((mca_addr >> 23) & 0x1ULL) ^ 650 ((retired_page >> 42) & 0x1ULL)) << 1); 651 die &= 3; 652 653 return die; 654 } 655 656 struct amdgpu_umc_ras umc_v12_0_ras = { 657 .ras_block = { 658 .hw_ops = &umc_v12_0_ras_hw_ops, 659 .ras_late_init = umc_v12_0_ras_late_init, 660 }, 661 .err_cnt_init = umc_v12_0_err_cnt_init, 662 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 663 .ecc_info_query_ras_error_address = umc_v12_0_query_ras_ecc_err_addr, 664 .check_ecc_err_status = umc_v12_0_check_ecc_err_status, 665 .update_ecc_status = umc_v12_0_update_ecc_status, 666 .convert_ras_err_addr = umc_v12_0_convert_error_address, 667 .get_die_id_from_pa = umc_v12_0_get_die_id, 668 }; 669 670