1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "umc_v12_0.h" 24 #include "amdgpu_ras.h" 25 #include "amdgpu_umc.h" 26 #include "amdgpu.h" 27 #include "umc/umc_12_0_0_offset.h" 28 #include "umc/umc_12_0_0_sh_mask.h" 29 #include "mp/mp_13_0_6_sh_mask.h" 30 31 const uint32_t 32 umc_v12_0_channel_idx_tbl[] 33 [UMC_V12_0_UMC_INSTANCE_NUM] 34 [UMC_V12_0_CHANNEL_INSTANCE_NUM] = { 35 {{3, 7, 11, 15, 2, 6, 10, 14}, {1, 5, 9, 13, 0, 4, 8, 12}, 36 {19, 23, 27, 31, 18, 22, 26, 30}, {17, 21, 25, 29, 16, 20, 24, 28}}, 37 {{47, 43, 39, 35, 46, 42, 38, 34}, {45, 41, 37, 33, 44, 40, 36, 32}, 38 {63, 59, 55, 51, 62, 58, 54, 50}, {61, 57, 53, 49, 60, 56, 52, 48}}, 39 {{79, 75, 71, 67, 78, 74, 70, 66}, {77, 73, 69, 65, 76, 72, 68, 64}, 40 {95, 91, 87, 83, 94, 90, 86, 82}, {93, 89, 85, 81, 92, 88, 84, 80}}, 41 {{99, 103, 107, 111, 98, 102, 106, 110}, {97, 101, 105, 109, 96, 100, 104, 108}, 42 {115, 119, 123, 127, 114, 118, 122, 126}, {113, 117, 121, 125, 112, 116, 120, 124}} 43 }; 44 45 /* mapping of MCA error address to normalized address */ 46 static const uint32_t umc_v12_0_ma2na_mapping[] = { 47 0, 5, 6, 8, 9, 14, 12, 13, 48 10, 11, 15, 16, 17, 18, 19, 20, 49 21, 22, 23, 24, 25, 26, 27, 28, 50 24, 7, 29, 30, 51 }; 52 53 static inline uint64_t get_umc_v12_0_reg_offset(struct amdgpu_device *adev, 54 uint32_t node_inst, 55 uint32_t umc_inst, 56 uint32_t ch_inst) 57 { 58 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; 59 uint64_t cross_node_offset = (node_inst == 0) ? 0 : UMC_V12_0_CROSS_NODE_OFFSET; 60 61 umc_inst = index / 4; 62 ch_inst = index % 4; 63 64 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + 65 UMC_V12_0_NODE_DIST * node_inst + cross_node_offset; 66 } 67 68 static int umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, 69 uint32_t node_inst, uint32_t umc_inst, 70 uint32_t ch_inst, void *data) 71 { 72 uint64_t odecc_err_cnt_addr; 73 uint64_t umc_reg_offset = 74 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 75 76 odecc_err_cnt_addr = 77 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 78 79 /* clear error count */ 80 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, 81 UMC_V12_0_CE_CNT_INIT); 82 83 return 0; 84 } 85 86 static void umc_v12_0_reset_error_count(struct amdgpu_device *adev) 87 { 88 amdgpu_umc_loop_channels(adev, 89 umc_v12_0_reset_error_count_per_channel, NULL); 90 } 91 92 bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 93 { 94 if (amdgpu_ras_is_poison_mode_supported(adev) && 95 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 96 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)) 97 return true; 98 99 return ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 100 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || 101 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || 102 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)); 103 } 104 105 bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status) 106 { 107 if (amdgpu_ras_is_poison_mode_supported(adev) && 108 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && 109 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1)) 110 return false; 111 112 return (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 113 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1 || 114 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 && 115 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 0) || 116 /* Identify data parity error in replay mode */ 117 ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0x5 || 118 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 0xb) && 119 !(umc_v12_0_is_uncorrectable_error(adev, mc_umc_status))))); 120 } 121 122 static void umc_v12_0_query_correctable_error_count(struct amdgpu_device *adev, 123 uint64_t umc_reg_offset, 124 unsigned long *error_count) 125 { 126 uint64_t mc_umc_status; 127 uint64_t mc_umc_status_addr; 128 129 mc_umc_status_addr = 130 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 131 132 /* Rely on MCUMC_STATUS for correctable error counter 133 * MCUMC_STATUS is a 64 bit register 134 */ 135 mc_umc_status = 136 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 137 138 if (umc_v12_0_is_correctable_error(adev, mc_umc_status)) 139 *error_count += 1; 140 } 141 142 static void umc_v12_0_query_uncorrectable_error_count(struct amdgpu_device *adev, 143 uint64_t umc_reg_offset, 144 unsigned long *error_count) 145 { 146 uint64_t mc_umc_status; 147 uint64_t mc_umc_status_addr; 148 149 mc_umc_status_addr = 150 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 151 152 /* Check the MCUMC_STATUS. */ 153 mc_umc_status = 154 RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 155 156 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) 157 *error_count += 1; 158 } 159 160 static int umc_v12_0_query_error_count(struct amdgpu_device *adev, 161 uint32_t node_inst, uint32_t umc_inst, 162 uint32_t ch_inst, void *data) 163 { 164 struct ras_err_data *err_data = (struct ras_err_data *)data; 165 unsigned long ue_count = 0, ce_count = 0; 166 167 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], 168 * which can be used as die ID directly */ 169 struct amdgpu_smuio_mcm_config_info mcm_info = { 170 .socket_id = adev->smuio.funcs->get_socket_id(adev), 171 .die_id = node_inst, 172 }; 173 174 uint64_t umc_reg_offset = 175 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 176 177 umc_v12_0_query_correctable_error_count(adev, umc_reg_offset, &ce_count); 178 umc_v12_0_query_uncorrectable_error_count(adev, umc_reg_offset, &ue_count); 179 180 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 181 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); 182 183 return 0; 184 } 185 186 static void umc_v12_0_query_ras_error_count(struct amdgpu_device *adev, 187 void *ras_error_status) 188 { 189 amdgpu_umc_loop_channels(adev, 190 umc_v12_0_query_error_count, ras_error_status); 191 192 umc_v12_0_reset_error_count(adev); 193 } 194 195 static bool umc_v12_0_bit_wise_xor(uint32_t val) 196 { 197 bool result = 0; 198 int i; 199 200 for (i = 0; i < 32; i++) 201 result = result ^ ((val >> i) & 0x1); 202 203 return result; 204 } 205 206 static void umc_v12_0_convert_error_address(struct amdgpu_device *adev, 207 struct ras_err_data *err_data, uint64_t err_addr, 208 uint32_t ch_inst, uint32_t umc_inst, 209 uint32_t node_inst) 210 { 211 uint32_t channel_index, i; 212 uint64_t soc_pa, na, retired_page, column; 213 uint32_t bank_hash0, bank_hash1, bank_hash2, bank_hash3, col, row, row_xor; 214 uint32_t bank0, bank1, bank2, bank3, bank; 215 216 bank_hash0 = (err_addr >> UMC_V12_0_MCA_B0_BIT) & 0x1ULL; 217 bank_hash1 = (err_addr >> UMC_V12_0_MCA_B1_BIT) & 0x1ULL; 218 bank_hash2 = (err_addr >> UMC_V12_0_MCA_B2_BIT) & 0x1ULL; 219 bank_hash3 = (err_addr >> UMC_V12_0_MCA_B3_BIT) & 0x1ULL; 220 col = (err_addr >> 1) & 0x1fULL; 221 row = (err_addr >> 10) & 0x3fffULL; 222 223 /* apply bank hash algorithm */ 224 bank0 = 225 bank_hash0 ^ (UMC_V12_0_XOR_EN0 & 226 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR0) ^ 227 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR0)))); 228 bank1 = 229 bank_hash1 ^ (UMC_V12_0_XOR_EN1 & 230 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR1) ^ 231 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR1)))); 232 bank2 = 233 bank_hash2 ^ (UMC_V12_0_XOR_EN2 & 234 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR2) ^ 235 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR2)))); 236 bank3 = 237 bank_hash3 ^ (UMC_V12_0_XOR_EN3 & 238 (umc_v12_0_bit_wise_xor(col & UMC_V12_0_COL_XOR3) ^ 239 (umc_v12_0_bit_wise_xor(row & UMC_V12_0_ROW_XOR3)))); 240 241 bank = bank0 | (bank1 << 1) | (bank2 << 2) | (bank3 << 3); 242 err_addr &= ~0x3c0ULL; 243 err_addr |= (bank << UMC_V12_0_MCA_B0_BIT); 244 245 na = 0x0; 246 /* convert mca error address to normalized address */ 247 for (i = 1; i < ARRAY_SIZE(umc_v12_0_ma2na_mapping); i++) 248 na |= ((err_addr >> i) & 0x1ULL) << umc_v12_0_ma2na_mapping[i]; 249 250 channel_index = 251 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * 252 adev->umc.channel_inst_num + 253 umc_inst * adev->umc.channel_inst_num + 254 ch_inst]; 255 /* translate umc channel address to soc pa, 3 parts are included */ 256 soc_pa = ADDR_OF_32KB_BLOCK(na) | 257 ADDR_OF_256B_BLOCK(channel_index) | 258 OFFSET_IN_256B_BLOCK(na); 259 260 /* the umc channel bits are not original values, they are hashed */ 261 UMC_V12_0_SET_CHANNEL_HASH(channel_index, soc_pa); 262 263 /* clear [C3 C2] in soc physical address */ 264 soc_pa &= ~(0x3ULL << UMC_V12_0_PA_C2_BIT); 265 /* clear [C4] in soc physical address */ 266 soc_pa &= ~(0x1ULL << UMC_V12_0_PA_C4_BIT); 267 268 row_xor = row ^ (0x1ULL << 13); 269 /* loop for all possibilities of [C4 C3 C2] */ 270 for (column = 0; column < UMC_V12_0_NA_MAP_PA_NUM; column++) { 271 retired_page = soc_pa | ((column & 0x3) << UMC_V12_0_PA_C2_BIT); 272 retired_page |= (((column & 0x4) >> 2) << UMC_V12_0_PA_C4_BIT); 273 /* include column bit 0 and 1 */ 274 col &= 0x3; 275 col |= (column << 2); 276 dev_info(adev->dev, 277 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 278 retired_page, row, col, bank, channel_index); 279 amdgpu_umc_fill_error_record(err_data, err_addr, 280 retired_page, channel_index, umc_inst); 281 282 /* shift R13 bit */ 283 retired_page ^= (0x1ULL << UMC_V12_0_PA_R13_BIT); 284 dev_info(adev->dev, 285 "Error Address(PA):0x%-10llx Row:0x%-4x Col:0x%-2x Bank:0x%x Channel:0x%x\n", 286 retired_page, row_xor, col, bank, channel_index); 287 amdgpu_umc_fill_error_record(err_data, err_addr, 288 retired_page, channel_index, umc_inst); 289 } 290 } 291 292 static int umc_v12_0_query_error_address(struct amdgpu_device *adev, 293 uint32_t node_inst, uint32_t umc_inst, 294 uint32_t ch_inst, void *data) 295 { 296 uint64_t mc_umc_status_addr; 297 uint64_t mc_umc_status, err_addr; 298 uint64_t mc_umc_addrt0; 299 struct ras_err_data *err_data = (struct ras_err_data *)data; 300 uint64_t umc_reg_offset = 301 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 302 303 mc_umc_status_addr = 304 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); 305 306 mc_umc_status = RREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4); 307 308 if (mc_umc_status == 0) 309 return 0; 310 311 if (!err_data->err_addr) { 312 /* clear umc status */ 313 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 314 315 return 0; 316 } 317 318 /* calculate error address if ue error is detected */ 319 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && 320 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && 321 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1) { 322 323 mc_umc_addrt0 = 324 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); 325 326 err_addr = RREG64_PCIE_EXT((mc_umc_addrt0 + umc_reg_offset) * 4); 327 328 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 329 330 umc_v12_0_convert_error_address(adev, err_data, err_addr, 331 ch_inst, umc_inst, node_inst); 332 } 333 334 /* clear umc status */ 335 WREG64_PCIE_EXT((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); 336 337 return 0; 338 } 339 340 static void umc_v12_0_query_ras_error_address(struct amdgpu_device *adev, 341 void *ras_error_status) 342 { 343 amdgpu_umc_loop_channels(adev, 344 umc_v12_0_query_error_address, ras_error_status); 345 } 346 347 static int umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, 348 uint32_t node_inst, uint32_t umc_inst, 349 uint32_t ch_inst, void *data) 350 { 351 uint32_t odecc_cnt_sel; 352 uint64_t odecc_cnt_sel_addr, odecc_err_cnt_addr; 353 uint64_t umc_reg_offset = 354 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst); 355 356 odecc_cnt_sel_addr = 357 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccCntSel); 358 odecc_err_cnt_addr = 359 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_OdEccErrCnt); 360 361 odecc_cnt_sel = RREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4); 362 363 /* set ce error interrupt type to APIC based interrupt */ 364 odecc_cnt_sel = REG_SET_FIELD(odecc_cnt_sel, UMCCH0_OdEccCntSel, 365 OdEccErrInt, 0x1); 366 WREG32_PCIE_EXT((odecc_cnt_sel_addr + umc_reg_offset) * 4, odecc_cnt_sel); 367 368 /* set error count to initial value */ 369 WREG32_PCIE_EXT((odecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V12_0_CE_CNT_INIT); 370 371 return 0; 372 } 373 374 static void umc_v12_0_ecc_info_query_ras_error_count(struct amdgpu_device *adev, 375 void *ras_error_status) 376 { 377 amdgpu_mca_smu_log_ras_error(adev, 378 AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_CE, ras_error_status); 379 amdgpu_mca_smu_log_ras_error(adev, 380 AMDGPU_RAS_BLOCK__UMC, AMDGPU_MCA_ERROR_TYPE_UE, ras_error_status); 381 } 382 383 static void umc_v12_0_ecc_info_query_ras_error_address(struct amdgpu_device *adev, 384 void *ras_error_status) 385 { 386 struct ras_err_node *err_node; 387 uint64_t mc_umc_status; 388 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 389 390 for_each_ras_error(err_node, err_data) { 391 mc_umc_status = err_node->err_info.err_addr.err_status; 392 if (!mc_umc_status) 393 continue; 394 395 if (umc_v12_0_is_uncorrectable_error(adev, mc_umc_status)) { 396 uint64_t mca_addr, err_addr, mca_ipid; 397 uint32_t InstanceIdLo; 398 struct amdgpu_smuio_mcm_config_info *mcm_info; 399 400 mcm_info = &err_node->err_info.mcm_info; 401 mca_addr = err_node->err_info.err_addr.err_addr; 402 mca_ipid = err_node->err_info.err_addr.err_ipid; 403 404 err_addr = REG_GET_FIELD(mca_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); 405 InstanceIdLo = REG_GET_FIELD(mca_ipid, MCMP1_IPIDT0, InstanceIdLo); 406 407 dev_info(adev->dev, "UMC:IPID:0x%llx, aid:%d, inst:%d, ch:%d, err_addr:0x%llx\n", 408 mca_ipid, 409 mcm_info->die_id, 410 MCA_IPID_LO_2_UMC_INST(InstanceIdLo), 411 MCA_IPID_LO_2_UMC_CH(InstanceIdLo), 412 err_addr); 413 414 umc_v12_0_convert_error_address(adev, 415 err_data, err_addr, 416 MCA_IPID_LO_2_UMC_CH(InstanceIdLo), 417 MCA_IPID_LO_2_UMC_INST(InstanceIdLo), 418 mcm_info->die_id); 419 420 /* Clear umc error address content */ 421 memset(&err_node->err_info.err_addr, 422 0, sizeof(err_node->err_info.err_addr)); 423 } 424 } 425 } 426 427 static void umc_v12_0_err_cnt_init(struct amdgpu_device *adev) 428 { 429 amdgpu_umc_loop_channels(adev, 430 umc_v12_0_err_cnt_init_per_channel, NULL); 431 } 432 433 static bool umc_v12_0_query_ras_poison_mode(struct amdgpu_device *adev) 434 { 435 /* 436 * Force return true, because regUMCCH0_EccCtrl 437 * is not accessible from host side 438 */ 439 return true; 440 } 441 442 const struct amdgpu_ras_block_hw_ops umc_v12_0_ras_hw_ops = { 443 .query_ras_error_count = umc_v12_0_query_ras_error_count, 444 .query_ras_error_address = umc_v12_0_query_ras_error_address, 445 }; 446 447 struct amdgpu_umc_ras umc_v12_0_ras = { 448 .ras_block = { 449 .hw_ops = &umc_v12_0_ras_hw_ops, 450 }, 451 .err_cnt_init = umc_v12_0_err_cnt_init, 452 .query_ras_poison_mode = umc_v12_0_query_ras_poison_mode, 453 .ecc_info_query_ras_error_count = umc_v12_0_ecc_info_query_ras_error_count, 454 .ecc_info_query_ras_error_address = umc_v12_0_ecc_info_query_ras_error_address, 455 }; 456