1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_ih.h" 28 #include "vid.h" 29 30 #include "oss/oss_3_0_d.h" 31 #include "oss/oss_3_0_sh_mask.h" 32 33 #include "bif/bif_5_1_d.h" 34 #include "bif/bif_5_1_sh_mask.h" 35 36 /* 37 * Interrupts 38 * Starting with r6xx, interrupts are handled via a ring buffer. 39 * Ring buffers are areas of GPU accessible memory that the GPU 40 * writes interrupt vectors into and the host reads vectors out of. 41 * There is a rptr (read pointer) that determines where the 42 * host is currently reading, and a wptr (write pointer) 43 * which determines where the GPU has written. When the 44 * pointers are equal, the ring is idle. When the GPU 45 * writes vectors to the ring buffer, it increments the 46 * wptr. When there is an interrupt, the host then starts 47 * fetching commands and processing them until the pointers are 48 * equal again at which point it updates the rptr. 49 */ 50 51 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev); 52 53 /** 54 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer 55 * 56 * @adev: amdgpu_device pointer 57 * 58 * Enable the interrupt ring buffer (VI). 59 */ 60 static void tonga_ih_enable_interrupts(struct amdgpu_device *adev) 61 { 62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 63 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 65 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 67 adev->irq.ih.enabled = true; 68 } 69 70 /** 71 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer 72 * 73 * @adev: amdgpu_device pointer 74 * 75 * Disable the interrupt ring buffer (VI). 76 */ 77 static void tonga_ih_disable_interrupts(struct amdgpu_device *adev) 78 { 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 80 81 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); 83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 84 /* set rptr, wptr to 0 */ 85 WREG32(mmIH_RB_RPTR, 0); 86 WREG32(mmIH_RB_WPTR, 0); 87 adev->irq.ih.enabled = false; 88 adev->irq.ih.rptr = 0; 89 } 90 91 /** 92 * tonga_ih_irq_init - init and enable the interrupt ring 93 * 94 * @adev: amdgpu_device pointer 95 * 96 * Allocate a ring buffer for the interrupt controller, 97 * enable the RLC, disable interrupts, enable the IH 98 * ring buffer and enable it (VI). 99 * Called at device load and reume. 100 * Returns 0 for success, errors for failure. 101 */ 102 static int tonga_ih_irq_init(struct amdgpu_device *adev) 103 { 104 u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr; 105 struct amdgpu_ih_ring *ih = &adev->irq.ih; 106 int rb_bufsz; 107 108 /* disable irqs */ 109 tonga_ih_disable_interrupts(adev); 110 111 /* setup interrupt control */ 112 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 113 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 114 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 115 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 116 */ 117 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 118 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 120 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 121 122 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 123 WREG32(mmIH_RB_BASE, ih->gpu_addr >> 8); 124 125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 126 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 128 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); 131 132 if (adev->irq.msi_enabled) 133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); 134 135 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 136 137 /* set the writeback address whether it's enabled or not */ 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); 139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); 140 141 /* set rptr, wptr to 0 */ 142 WREG32(mmIH_RB_RPTR, 0); 143 WREG32(mmIH_RB_WPTR, 0); 144 145 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR); 146 if (adev->irq.ih.use_doorbell) { 147 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 148 OFFSET, adev->irq.ih.doorbell_index); 149 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 150 ENABLE, 1); 151 } else { 152 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr, IH_DOORBELL_RPTR, 153 ENABLE, 0); 154 } 155 WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr); 156 157 pci_set_master(adev->pdev); 158 159 /* enable interrupts */ 160 tonga_ih_enable_interrupts(adev); 161 162 if (adev->irq.ih_soft.ring_size) 163 adev->irq.ih_soft.enabled = true; 164 165 return 0; 166 } 167 168 /** 169 * tonga_ih_irq_disable - disable interrupts 170 * 171 * @adev: amdgpu_device pointer 172 * 173 * Disable interrupts on the hw (VI). 174 */ 175 static void tonga_ih_irq_disable(struct amdgpu_device *adev) 176 { 177 tonga_ih_disable_interrupts(adev); 178 179 /* Wait and acknowledge irq */ 180 mdelay(1); 181 } 182 183 /** 184 * tonga_ih_get_wptr - get the IH ring buffer wptr 185 * 186 * @adev: amdgpu_device pointer 187 * @ih: IH ring buffer to fetch wptr 188 * 189 * Get the IH ring buffer wptr from either the register 190 * or the writeback memory buffer (VI). Also check for 191 * ring buffer overflow and deal with it. 192 * Used by cz_irq_process(VI). 193 * Returns the value of the wptr. 194 */ 195 static u32 tonga_ih_get_wptr(struct amdgpu_device *adev, 196 struct amdgpu_ih_ring *ih) 197 { 198 u32 wptr, tmp; 199 200 wptr = le32_to_cpu(*ih->wptr_cpu); 201 202 if (ih == &adev->irq.ih_soft) 203 goto out; 204 205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 206 goto out; 207 208 /* Double check that the overflow wasn't already cleared. */ 209 wptr = RREG32(mmIH_RB_WPTR); 210 211 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) 212 goto out; 213 214 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 215 216 /* When a ring buffer overflow happen start parsing interrupt 217 * from the last not overwritten vector (wptr + 16). Hopefully 218 * this should allow us to catchup. 219 */ 220 221 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 222 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); 223 ih->rptr = (wptr + 16) & ih->ptr_mask; 224 tmp = RREG32(mmIH_RB_CNTL); 225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 226 WREG32(mmIH_RB_CNTL, tmp); 227 228 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 229 * can be detected. 230 */ 231 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 232 WREG32(mmIH_RB_CNTL, tmp); 233 234 out: 235 return (wptr & ih->ptr_mask); 236 } 237 238 /** 239 * tonga_ih_decode_iv - decode an interrupt vector 240 * 241 * @adev: amdgpu_device pointer 242 * @ih: IH ring buffer to decode 243 * @entry: IV entry to place decoded information into 244 * 245 * Decodes the interrupt vector at the current rptr 246 * position and also advance the position. 247 */ 248 static void tonga_ih_decode_iv(struct amdgpu_device *adev, 249 struct amdgpu_ih_ring *ih, 250 struct amdgpu_iv_entry *entry) 251 { 252 /* wptr/rptr are in bytes! */ 253 u32 ring_index = ih->rptr >> 2; 254 uint32_t dw[4]; 255 256 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); 257 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); 258 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); 259 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); 260 261 entry->client_id = AMDGPU_IRQ_CLIENTID_LEGACY; 262 entry->src_id = dw[0] & 0xff; 263 entry->src_data[0] = dw[1] & 0xfffffff; 264 entry->ring_id = dw[2] & 0xff; 265 entry->vmid = (dw[2] >> 8) & 0xff; 266 entry->pasid = (dw[2] >> 16) & 0xffff; 267 268 /* wptr/rptr are in bytes! */ 269 ih->rptr += 16; 270 } 271 272 /** 273 * tonga_ih_set_rptr - set the IH ring buffer rptr 274 * 275 * @adev: amdgpu_device pointer 276 * @ih: IH ring buffer to set rptr 277 * 278 * Set the IH ring buffer rptr. 279 */ 280 static void tonga_ih_set_rptr(struct amdgpu_device *adev, 281 struct amdgpu_ih_ring *ih) 282 { 283 if (ih->use_doorbell) { 284 /* XXX check if swapping is necessary on BE */ 285 *ih->rptr_cpu = ih->rptr; 286 WDOORBELL32(ih->doorbell_index, ih->rptr); 287 } else { 288 WREG32(mmIH_RB_RPTR, ih->rptr); 289 } 290 } 291 292 static int tonga_ih_early_init(struct amdgpu_ip_block *ip_block) 293 { 294 struct amdgpu_device *adev = ip_block->adev; 295 int ret; 296 297 ret = amdgpu_irq_add_domain(adev); 298 if (ret) 299 return ret; 300 301 tonga_ih_set_interrupt_funcs(adev); 302 303 return 0; 304 } 305 306 static int tonga_ih_sw_init(struct amdgpu_ip_block *ip_block) 307 { 308 int r; 309 struct amdgpu_device *adev = ip_block->adev; 310 311 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true); 312 if (r) 313 return r; 314 315 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); 316 if (r) 317 return r; 318 319 adev->irq.ih.use_doorbell = true; 320 adev->irq.ih.doorbell_index = adev->doorbell_index.ih; 321 322 r = amdgpu_irq_init(adev); 323 324 return r; 325 } 326 327 static int tonga_ih_sw_fini(struct amdgpu_ip_block *ip_block) 328 { 329 struct amdgpu_device *adev = ip_block->adev; 330 331 amdgpu_irq_fini_sw(adev); 332 amdgpu_irq_remove_domain(adev); 333 334 return 0; 335 } 336 337 static int tonga_ih_hw_init(struct amdgpu_ip_block *ip_block) 338 { 339 int r; 340 struct amdgpu_device *adev = ip_block->adev; 341 342 r = tonga_ih_irq_init(adev); 343 if (r) 344 return r; 345 346 return 0; 347 } 348 349 static int tonga_ih_hw_fini(struct amdgpu_ip_block *ip_block) 350 { 351 tonga_ih_irq_disable(ip_block->adev); 352 353 return 0; 354 } 355 356 static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block) 357 { 358 return tonga_ih_hw_fini(ip_block); 359 } 360 361 static int tonga_ih_resume(struct amdgpu_ip_block *ip_block) 362 { 363 return tonga_ih_hw_init(ip_block); 364 } 365 366 static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block) 367 { 368 struct amdgpu_device *adev = ip_block->adev; 369 u32 tmp = RREG32(mmSRBM_STATUS); 370 371 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 372 return false; 373 374 return true; 375 } 376 377 static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) 378 { 379 unsigned i; 380 u32 tmp; 381 struct amdgpu_device *adev = ip_block->adev; 382 383 for (i = 0; i < adev->usec_timeout; i++) { 384 /* read MC_STATUS */ 385 tmp = RREG32(mmSRBM_STATUS); 386 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 387 return 0; 388 udelay(1); 389 } 390 return -ETIMEDOUT; 391 } 392 393 static bool tonga_ih_check_soft_reset(struct amdgpu_ip_block *ip_block) 394 { 395 struct amdgpu_device *adev = ip_block->adev; 396 u32 srbm_soft_reset = 0; 397 u32 tmp = RREG32(mmSRBM_STATUS); 398 399 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 400 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 401 SOFT_RESET_IH, 1); 402 403 if (srbm_soft_reset) { 404 adev->irq.srbm_soft_reset = srbm_soft_reset; 405 return true; 406 } else { 407 adev->irq.srbm_soft_reset = 0; 408 return false; 409 } 410 } 411 412 static int tonga_ih_pre_soft_reset(struct amdgpu_ip_block *ip_block) 413 { 414 if (!ip_block->adev->irq.srbm_soft_reset) 415 return 0; 416 417 return tonga_ih_hw_fini(ip_block); 418 } 419 420 static int tonga_ih_post_soft_reset(struct amdgpu_ip_block *ip_block) 421 { 422 struct amdgpu_device *adev = ip_block->adev; 423 424 if (!adev->irq.srbm_soft_reset) 425 return 0; 426 427 return tonga_ih_hw_init(ip_block); 428 } 429 430 static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block) 431 { 432 struct amdgpu_device *adev = ip_block->adev; 433 u32 srbm_soft_reset; 434 435 if (!adev->irq.srbm_soft_reset) 436 return 0; 437 srbm_soft_reset = adev->irq.srbm_soft_reset; 438 439 if (srbm_soft_reset) { 440 u32 tmp; 441 442 tmp = RREG32(mmSRBM_SOFT_RESET); 443 tmp |= srbm_soft_reset; 444 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 445 WREG32(mmSRBM_SOFT_RESET, tmp); 446 tmp = RREG32(mmSRBM_SOFT_RESET); 447 448 udelay(50); 449 450 tmp &= ~srbm_soft_reset; 451 WREG32(mmSRBM_SOFT_RESET, tmp); 452 tmp = RREG32(mmSRBM_SOFT_RESET); 453 454 /* Wait a little for things to settle down */ 455 udelay(50); 456 } 457 458 return 0; 459 } 460 461 static int tonga_ih_set_clockgating_state(struct amdgpu_ip_block *ip_block, 462 enum amd_clockgating_state state) 463 { 464 return 0; 465 } 466 467 static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block, 468 enum amd_powergating_state state) 469 { 470 return 0; 471 } 472 473 static const struct amd_ip_funcs tonga_ih_ip_funcs = { 474 .name = "tonga_ih", 475 .early_init = tonga_ih_early_init, 476 .sw_init = tonga_ih_sw_init, 477 .sw_fini = tonga_ih_sw_fini, 478 .hw_init = tonga_ih_hw_init, 479 .hw_fini = tonga_ih_hw_fini, 480 .suspend = tonga_ih_suspend, 481 .resume = tonga_ih_resume, 482 .is_idle = tonga_ih_is_idle, 483 .wait_for_idle = tonga_ih_wait_for_idle, 484 .check_soft_reset = tonga_ih_check_soft_reset, 485 .pre_soft_reset = tonga_ih_pre_soft_reset, 486 .soft_reset = tonga_ih_soft_reset, 487 .post_soft_reset = tonga_ih_post_soft_reset, 488 .set_clockgating_state = tonga_ih_set_clockgating_state, 489 .set_powergating_state = tonga_ih_set_powergating_state, 490 }; 491 492 static const struct amdgpu_ih_funcs tonga_ih_funcs = { 493 .get_wptr = tonga_ih_get_wptr, 494 .decode_iv = tonga_ih_decode_iv, 495 .set_rptr = tonga_ih_set_rptr 496 }; 497 498 static void tonga_ih_set_interrupt_funcs(struct amdgpu_device *adev) 499 { 500 adev->irq.ih_funcs = &tonga_ih_funcs; 501 } 502 503 const struct amdgpu_ip_block_version tonga_ih_ip_block = { 504 .type = AMD_IP_BLOCK_TYPE_IH, 505 .major = 3, 506 .minor = 0, 507 .rev = 0, 508 .funcs = &tonga_ih_ip_funcs, 509 }; 510