1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 38 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 39 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 40 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 41 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 42 (offset & 0xFFFF) 43 44 #define MID1_REG_RANGE_0_LOW 0x40000 45 #define MID1_REG_RANGE_0_HIGH 0x80000 46 #define NORMALIZE_MID_REG_OFFSET(offset) \ 47 (offset & 0x3FFFF) 48 49 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { 50 .codec_count = 0, 51 .codec_array = NULL, 52 }; 53 54 static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 56 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 57 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), 64 .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, 65 }; 66 67 static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, 68 const struct amdgpu_video_codecs **codecs) 69 { 70 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 71 case IP_VERSION(5, 0, 2): 72 if (encode) 73 *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; 74 else 75 *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; 76 return 0; 77 default: 78 return -EINVAL; 79 } 80 } 81 82 /* Initialized doorbells for amdgpu including multimedia 83 * KFD can use all the rest in 2M doorbell bar */ 84 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 85 { 86 int i; 87 88 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 89 90 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 91 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 92 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 93 94 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 95 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 96 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 97 98 adev->doorbell_index.sdma_doorbell_range = 14; 99 for (i = 0; i < adev->sdma.num_instances; i++) 100 adev->doorbell_index.sdma_engine[i] = 101 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 102 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 103 104 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 105 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 106 107 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 108 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 109 110 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 111 } 112 113 /* Fixed pattern for upper 32bits smn addressing. 114 * bit[47:40]: Socket ID 115 * bit[39:34]: Die ID 116 * bit[32]: local or remote die in same socket 117 * The ext_id is comprised of socket_id and die_id. 118 * ext_id = (socket_id << 6) | (die_id) 119 */ 120 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 121 { 122 u64 ext_offset; 123 int socket_id, die_id; 124 125 /* local die routing for MID0 on local socket */ 126 if (ext_id == 0) 127 return 0; 128 129 die_id = ext_id & 0x3; 130 socket_id = (ext_id >> 6) & 0xff; 131 132 /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 133 if (socket_id == 0) 134 ext_offset = ((u64)die_id << 34) | (1ULL << 32); 135 else if (socket_id != 0 && die_id != 0) 136 ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 137 (3ULL << 32); 138 else 139 ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 140 141 return ext_offset; 142 } 143 144 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 145 { 146 return adev->nbio.funcs->get_memsize(adev); 147 } 148 149 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 150 { 151 return adev->clock.spll.reference_freq; 152 } 153 154 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 155 u32 me, u32 pipe, 156 u32 queue, u32 vmid, 157 int xcc_id) 158 { 159 u32 grbm_gfx_cntl = 0; 160 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 161 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 162 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 163 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 164 165 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 166 } 167 168 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 169 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 170 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 171 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 172 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 173 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 174 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 175 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 176 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 177 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 178 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 179 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 180 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 181 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 182 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 183 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 184 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 185 }; 186 187 static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, 188 u32 se_num, 189 u32 sh_num, 190 u32 reg_offset) 191 { 192 uint32_t val; 193 194 mutex_lock(&adev->grbm_idx_mutex); 195 if (se_num != 0xffffffff || sh_num != 0xffffffff) 196 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 197 198 val = RREG32(reg_offset); 199 200 if (se_num != 0xffffffff || sh_num != 0xffffffff) 201 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 202 mutex_unlock(&adev->grbm_idx_mutex); 203 return val; 204 } 205 206 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 207 bool indexed, u32 se_num, 208 u32 sh_num, u32 reg_offset) 209 { 210 if (indexed) { 211 return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); 212 } else { 213 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 214 adev->gfx.config.gb_addr_config) 215 return adev->gfx.config.gb_addr_config; 216 return RREG32(reg_offset); 217 } 218 } 219 220 static int soc_v1_0_read_register(struct amdgpu_device *adev, 221 u32 se_num, u32 sh_num, 222 u32 reg_offset, u32 *value) 223 { 224 uint32_t i; 225 struct soc15_allowed_register_entry *en; 226 227 *value = 0; 228 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 229 en = &soc_v1_0_allowed_read_registers[i]; 230 if (!adev->reg_offset[en->hwip][en->inst]) 231 continue; 232 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 233 + en->reg_offset)) 234 continue; 235 236 *value = soc_v1_0_get_register_value(adev, 237 soc_v1_0_allowed_read_registers[i].grbm_indexed, 238 se_num, sh_num, reg_offset); 239 return 0; 240 } 241 return -EINVAL; 242 } 243 244 static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) 245 { 246 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 247 case IP_VERSION(12, 1, 0): 248 default: 249 return true; 250 } 251 } 252 253 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 254 { 255 256 return false; 257 } 258 259 static enum amd_reset_method 260 soc_v1_0_asic_reset_method(struct amdgpu_device *adev) 261 { 262 if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || 263 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { 264 if (amdgpu_reset_method != -1) 265 dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); 266 267 return AMD_RESET_METHOD_MODE2; 268 } 269 270 return amdgpu_reset_method; 271 } 272 273 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 274 { 275 switch (soc_v1_0_asic_reset_method(adev)) { 276 case AMD_RESET_METHOD_MODE2: 277 dev_info(adev->dev, "MODE2 reset\n"); 278 return amdgpu_dpm_mode2_reset(adev); 279 default: 280 dev_info(adev->dev, "Invalid reset method Not supported\n"); 281 return -EOPNOTSUPP; 282 } 283 284 return 0; 285 } 286 287 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 288 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 289 .read_register = &soc_v1_0_read_register, 290 .get_config_memsize = &soc_v1_0_get_config_memsize, 291 .get_xclk = &soc_v1_0_get_xclk, 292 .need_full_reset = &soc_v1_0_need_full_reset, 293 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 294 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 295 .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 296 .reset = soc_v1_0_asic_reset, 297 .reset_method = &soc_v1_0_asic_reset_method, 298 .query_video_codecs = &soc_v1_0_query_video_codecs, 299 }; 300 301 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 302 { 303 struct amdgpu_device *adev = ip_block->adev; 304 305 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 306 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 307 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 308 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 309 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 310 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 311 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 312 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 313 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 314 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 315 316 adev->asic_funcs = &soc_v1_0_asic_funcs; 317 318 adev->rev_id = amdgpu_device_get_rev_id(adev); 319 adev->external_rev_id = 0xff; 320 321 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 322 case IP_VERSION(12, 1, 0): 323 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 324 AMD_CG_SUPPORT_GFX_CGLS; 325 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 326 adev->external_rev_id = adev->rev_id + 0x50; 327 break; 328 default: 329 /* FIXME: not supported yet */ 330 return -EINVAL; 331 } 332 333 adev->nbio.funcs->init_registers(adev); 334 335 return 0; 336 } 337 338 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 339 { 340 struct amdgpu_device *adev = ip_block->adev; 341 342 /* Enable selfring doorbell aperture late because doorbell BAR 343 * aperture will change if resize BAR successfully in gmc sw_init. 344 */ 345 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 346 347 return 0; 348 } 349 350 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 351 { 352 return 0; 353 } 354 355 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 356 { 357 struct amdgpu_device *adev = ip_block->adev; 358 359 /* enable the doorbell aperture */ 360 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 361 362 return 0; 363 } 364 365 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 366 { 367 struct amdgpu_device *adev = ip_block->adev; 368 369 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 370 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 371 372 return 0; 373 } 374 375 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 376 { 377 return soc_v1_0_common_hw_fini(ip_block); 378 } 379 380 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 381 { 382 return soc_v1_0_common_hw_init(ip_block); 383 } 384 385 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 386 { 387 return true; 388 } 389 390 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 391 enum amd_clockgating_state state) 392 { 393 return 0; 394 } 395 396 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 397 enum amd_powergating_state state) 398 { 399 return 0; 400 } 401 402 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 403 u64 *flags) 404 { 405 return; 406 } 407 408 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 409 .name = "soc_v1_0_common", 410 .early_init = soc_v1_0_common_early_init, 411 .late_init = soc_v1_0_common_late_init, 412 .sw_init = soc_v1_0_common_sw_init, 413 .hw_init = soc_v1_0_common_hw_init, 414 .hw_fini = soc_v1_0_common_hw_fini, 415 .suspend = soc_v1_0_common_suspend, 416 .resume = soc_v1_0_common_resume, 417 .is_idle = soc_v1_0_common_is_idle, 418 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 419 .set_powergating_state = soc_v1_0_common_set_powergating_state, 420 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 421 }; 422 423 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 424 .type = AMD_IP_BLOCK_TYPE_COMMON, 425 .major = 1, 426 .minor = 0, 427 .rev = 0, 428 .funcs = &soc_v1_0_common_ip_funcs, 429 }; 430 431 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 432 { 433 struct amdgpu_device *adev = xcp_mgr->adev; 434 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 435 436 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 437 if (adev->gfx.funcs && 438 adev->gfx.funcs->get_xccs_per_xcp) 439 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 440 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 441 mode = num_xcc / num_xcc_per_xcp; 442 443 if (num_xcc_per_xcp == 1) 444 return AMDGPU_CPX_PARTITION_MODE; 445 446 switch (mode) { 447 case 1: 448 return AMDGPU_SPX_PARTITION_MODE; 449 case 2: 450 return AMDGPU_DPX_PARTITION_MODE; 451 case 3: 452 return AMDGPU_TPX_PARTITION_MODE; 453 case 4: 454 return AMDGPU_QPX_PARTITION_MODE; 455 default: 456 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 457 } 458 459 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 460 } 461 462 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 463 { 464 enum amdgpu_gfx_partition derv_mode, mode; 465 struct amdgpu_device *adev = xcp_mgr->adev; 466 467 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 468 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 469 470 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 471 return derv_mode; 472 473 if (adev->nbio.funcs && 474 adev->nbio.funcs->get_compute_partition_mode) { 475 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 476 if (mode != derv_mode) 477 dev_warn(adev->dev, 478 "Mismatch in compute partition mode - reported : %d derived : %d", 479 mode, derv_mode); 480 } 481 482 return mode; 483 } 484 485 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 486 { 487 int num_xcc, num_xcc_per_xcp = 0; 488 489 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 490 491 switch (mode) { 492 case AMDGPU_SPX_PARTITION_MODE: 493 num_xcc_per_xcp = num_xcc; 494 break; 495 case AMDGPU_DPX_PARTITION_MODE: 496 num_xcc_per_xcp = num_xcc / 2; 497 break; 498 case AMDGPU_TPX_PARTITION_MODE: 499 num_xcc_per_xcp = num_xcc / 3; 500 break; 501 case AMDGPU_QPX_PARTITION_MODE: 502 num_xcc_per_xcp = num_xcc / 4; 503 break; 504 case AMDGPU_CPX_PARTITION_MODE: 505 num_xcc_per_xcp = 1; 506 break; 507 } 508 509 return num_xcc_per_xcp; 510 } 511 512 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 513 enum AMDGPU_XCP_IP_BLOCK ip_id, 514 struct amdgpu_xcp_ip *ip) 515 { 516 struct amdgpu_device *adev = xcp_mgr->adev; 517 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 518 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 519 520 num_sdma = adev->sdma.num_instances; 521 num_vcn = adev->vcn.num_vcn_inst; 522 num_shared_vcn = 1; 523 524 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 525 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 526 527 switch (xcp_mgr->mode) { 528 case AMDGPU_SPX_PARTITION_MODE: 529 case AMDGPU_DPX_PARTITION_MODE: 530 case AMDGPU_TPX_PARTITION_MODE: 531 case AMDGPU_QPX_PARTITION_MODE: 532 case AMDGPU_CPX_PARTITION_MODE: 533 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 534 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 535 break; 536 default: 537 return -EINVAL; 538 } 539 540 if (num_vcn && num_xcp > num_vcn) 541 num_shared_vcn = num_xcp / num_vcn; 542 543 switch (ip_id) { 544 case AMDGPU_XCP_GFXHUB: 545 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 546 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 547 break; 548 case AMDGPU_XCP_GFX: 549 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 550 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 551 break; 552 case AMDGPU_XCP_SDMA: 553 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 554 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 555 break; 556 case AMDGPU_XCP_VCN: 557 ip->inst_mask = 558 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 559 /* TODO : Assign IP funcs */ 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 ip->ip_id = ip_id; 566 567 return 0; 568 } 569 570 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 571 int mode, 572 struct amdgpu_xcp_cfg *xcp_cfg) 573 { 574 struct amdgpu_device *adev = xcp_mgr->adev; 575 int max_res[AMDGPU_XCP_RES_MAX] = {}; 576 bool res_lt_xcp; 577 int num_xcp, i; 578 u16 nps_modes; 579 580 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 581 return -EINVAL; 582 583 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 584 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 585 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 586 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 587 588 switch (mode) { 589 case AMDGPU_SPX_PARTITION_MODE: 590 num_xcp = 1; 591 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 592 break; 593 case AMDGPU_DPX_PARTITION_MODE: 594 num_xcp = 2; 595 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 596 break; 597 case AMDGPU_TPX_PARTITION_MODE: 598 num_xcp = 3; 599 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 600 BIT(AMDGPU_NPS4_PARTITION_MODE); 601 break; 602 case AMDGPU_QPX_PARTITION_MODE: 603 num_xcp = 4; 604 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 605 BIT(AMDGPU_NPS4_PARTITION_MODE); 606 break; 607 case AMDGPU_CPX_PARTITION_MODE: 608 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 609 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 610 BIT(AMDGPU_NPS4_PARTITION_MODE); 611 break; 612 default: 613 return -EINVAL; 614 } 615 616 xcp_cfg->compatible_nps_modes = 617 (adev->gmc.supported_nps_modes & nps_modes); 618 xcp_cfg->num_res = ARRAY_SIZE(max_res); 619 620 for (i = 0; i < xcp_cfg->num_res; i++) { 621 res_lt_xcp = max_res[i] < num_xcp; 622 xcp_cfg->xcp_res[i].id = i; 623 xcp_cfg->xcp_res[i].num_inst = 624 res_lt_xcp ? 1 : max_res[i] / num_xcp; 625 xcp_cfg->xcp_res[i].num_inst = 626 i == AMDGPU_XCP_RES_JPEG ? 627 xcp_cfg->xcp_res[i].num_inst * 628 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 629 xcp_cfg->xcp_res[i].num_shared = 630 res_lt_xcp ? num_xcp / max_res[i] : 1; 631 } 632 633 return 0; 634 } 635 636 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 637 { 638 struct amdgpu_device *adev = xcp_mgr->adev; 639 int num_xcc; 640 641 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 642 643 if (adev->gmc.num_mem_partitions == 1) 644 return AMDGPU_SPX_PARTITION_MODE; 645 646 if (adev->gmc.num_mem_partitions == num_xcc) 647 return AMDGPU_CPX_PARTITION_MODE; 648 649 if (adev->gmc.num_mem_partitions == 2) 650 return AMDGPU_DPX_PARTITION_MODE; 651 652 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 653 } 654 655 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 656 enum amdgpu_gfx_partition mode) 657 { 658 struct amdgpu_device *adev = xcp_mgr->adev; 659 int num_xcc, num_xccs_per_xcp; 660 661 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 662 switch (mode) { 663 case AMDGPU_SPX_PARTITION_MODE: 664 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 665 case AMDGPU_DPX_PARTITION_MODE: 666 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 667 case AMDGPU_TPX_PARTITION_MODE: 668 return (adev->gmc.num_mem_partitions == 1 || 669 adev->gmc.num_mem_partitions == 3) && 670 ((num_xcc % 3) == 0); 671 case AMDGPU_QPX_PARTITION_MODE: 672 num_xccs_per_xcp = num_xcc / 4; 673 return (adev->gmc.num_mem_partitions == 1 || 674 adev->gmc.num_mem_partitions == 4) && 675 (num_xccs_per_xcp >= 2); 676 case AMDGPU_CPX_PARTITION_MODE: 677 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 678 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 679 * num_compute_partitions can't be less than num_mem_partitions 680 */ 681 return ((num_xcc > 1) && 682 (num_xcc % adev->gmc.num_mem_partitions) == 0); 683 default: 684 return false; 685 } 686 687 return false; 688 } 689 690 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 691 { 692 int mode; 693 694 xcp_mgr->avail_xcp_modes = 0; 695 696 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 697 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 698 xcp_mgr->avail_xcp_modes |= BIT(mode); 699 } 700 } 701 702 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 703 int mode, int *num_xcps) 704 { 705 int num_xcc_per_xcp, num_xcc, ret; 706 struct amdgpu_device *adev; 707 u32 flags = 0; 708 709 adev = xcp_mgr->adev; 710 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 711 712 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 713 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 714 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 715 dev_err(adev->dev, 716 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 717 adev->gmc.num_mem_partitions); 718 return -EINVAL; 719 } 720 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 721 dev_err(adev->dev, 722 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 723 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 724 return -EINVAL; 725 } 726 727 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 728 flags |= AMDGPU_XCP_OPS_KFD; 729 730 if (flags & AMDGPU_XCP_OPS_KFD) { 731 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 732 if (ret) 733 goto out; 734 } 735 736 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 737 if (ret) 738 goto unlock; 739 740 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 741 if (adev->gfx.imu.funcs && 742 adev->gfx.imu.funcs->switch_compute_partition) 743 adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 744 745 /* Init info about new xcps */ 746 *num_xcps = num_xcc / num_xcc_per_xcp; 747 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 748 749 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 750 if (!ret) 751 __soc_v1_0_update_available_partition_mode(xcp_mgr); 752 unlock: 753 if (flags & AMDGPU_XCP_OPS_KFD) 754 amdgpu_amdkfd_unlock_kfd(adev); 755 out: 756 return ret; 757 } 758 759 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 760 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 761 int xcc_id, uint8_t *mem_id) 762 { 763 /* memory/spatial modes validation check is already done */ 764 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 765 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 766 767 return 0; 768 } 769 770 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 771 struct amdgpu_xcp *xcp, uint8_t *mem_id) 772 { 773 struct amdgpu_numa_info numa_info; 774 struct amdgpu_device *adev; 775 uint32_t xcc_mask; 776 int r, i, xcc_id; 777 778 adev = xcp_mgr->adev; 779 /* TODO: BIOS is not returning the right info now 780 * Check on this later 781 */ 782 /* 783 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 784 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 785 */ 786 if (adev->gmc.num_mem_partitions == 1) { 787 /* Only one range */ 788 *mem_id = 0; 789 return 0; 790 } 791 792 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 793 if (r || !xcc_mask) 794 return -EINVAL; 795 796 xcc_id = ffs(xcc_mask) - 1; 797 if (!adev->gmc.is_app_apu) 798 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 799 800 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 801 802 if (r) 803 return r; 804 805 r = -EINVAL; 806 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 807 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 808 *mem_id = i; 809 r = 0; 810 break; 811 } 812 } 813 814 return r; 815 } 816 #endif 817 818 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 819 enum AMDGPU_XCP_IP_BLOCK ip_id, 820 struct amdgpu_xcp_ip *ip) 821 { 822 if (!ip) 823 return -EINVAL; 824 825 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 826 } 827 828 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 829 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 830 .query_partition_mode = &soc_v1_0_query_partition_mode, 831 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 832 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 833 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 834 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 835 #endif 836 }; 837 838 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 839 { 840 int ret; 841 842 if (amdgpu_sriov_vf(adev)) 843 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 844 845 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 846 1, &soc_v1_0_xcp_funcs); 847 if (ret) 848 return ret; 849 850 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 851 /* TODO: Default memory node affinity init */ 852 853 return ret; 854 } 855 856 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 857 { 858 int ret, i; 859 int xcc_inst_per_aid = 4; 860 uint16_t xcc_mask, sdma_mask = 0; 861 862 xcc_mask = adev->gfx.xcc_mask; 863 adev->aid_mask = 0; 864 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 865 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 866 adev->aid_mask |= (1 << i); 867 } 868 869 adev->sdma.num_inst_per_xcc = 2; 870 for_each_inst(i, adev->gfx.xcc_mask) 871 sdma_mask |= 872 GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << 873 (i * adev->sdma.num_inst_per_xcc); 874 adev->sdma.sdma_mask = sdma_mask; 875 adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); 876 877 ret = soc_v1_0_xcp_mgr_init(adev); 878 if (ret) 879 return ret; 880 881 amdgpu_ip_map_init(adev); 882 883 return 0; 884 } 885 886 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 887 { 888 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 889 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 890 return true; 891 else 892 return false; 893 } 894 895 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 896 { 897 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 898 899 /* If it is an XCC reg, normalize the reg to keep 900 * lower 16 bits in local xcc */ 901 902 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 903 return normalized_reg; 904 else 905 return reg; 906 } 907 908 bool soc_v1_0_mid1_reg_range(uint32_t reg) 909 { 910 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 911 912 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 913 return false; 914 915 if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) 916 return true; 917 else 918 return false; 919 } 920 921 uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) 922 { 923 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 924 925 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 926 return soc_v1_0_normalize_xcc_reg_offset(reg); 927 928 /* check if the reg offset is inside MID1. */ 929 if (soc_v1_0_mid1_reg_range(reg)) 930 return NORMALIZE_MID_REG_OFFSET(reg); 931 932 return reg; 933 } 934 935