1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 38 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 39 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 40 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 41 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 42 (offset & 0xFFFF) 43 44 /* Initialized doorbells for amdgpu including multimedia 45 * KFD can use all the rest in 2M doorbell bar */ 46 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 47 { 48 int i; 49 50 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 51 52 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 53 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 54 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 55 56 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 57 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 58 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 59 60 adev->doorbell_index.sdma_doorbell_range = 14; 61 for (i = 0; i < adev->sdma.num_instances; i++) 62 adev->doorbell_index.sdma_engine[i] = 63 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 64 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 65 66 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 67 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 68 69 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 70 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 71 72 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 73 } 74 75 /* Fixed pattern for upper 32bits smn addressing. 76 * bit[47:40]: Socket ID 77 * bit[39:34]: Die ID 78 * bit[32]: local or remote die in same socket 79 * The ext_id is comprised of socket_id and die_id. 80 * ext_id = (socket_id << 6) | (die_id) 81 */ 82 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 83 { 84 u64 ext_offset; 85 int socket_id, die_id; 86 87 /* local die routing for MID0 on local socket */ 88 if (ext_id == 0) 89 return 0; 90 91 die_id = ext_id & 0x3; 92 socket_id = (ext_id >> 6) & 0xff; 93 94 /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 95 if (socket_id == 0) 96 ext_offset = ((u64)die_id << 34) | (1ULL << 32); 97 else if (socket_id != 0 && die_id != 0) 98 ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 99 (3ULL << 32); 100 else 101 ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 102 103 return ext_offset; 104 } 105 106 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 107 { 108 return adev->nbio.funcs->get_memsize(adev); 109 } 110 111 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 112 { 113 return adev->clock.spll.reference_freq; 114 } 115 116 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 117 u32 me, u32 pipe, 118 u32 queue, u32 vmid, 119 int xcc_id) 120 { 121 u32 grbm_gfx_cntl = 0; 122 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 123 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 124 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 125 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 126 127 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 128 } 129 130 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 131 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 132 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 133 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 134 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 135 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 136 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 137 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 138 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 139 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 140 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 141 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 142 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 143 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 144 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 145 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 146 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 147 }; 148 149 static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, 150 u32 se_num, 151 u32 sh_num, 152 u32 reg_offset) 153 { 154 uint32_t val; 155 156 mutex_lock(&adev->grbm_idx_mutex); 157 if (se_num != 0xffffffff || sh_num != 0xffffffff) 158 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 159 160 val = RREG32(reg_offset); 161 162 if (se_num != 0xffffffff || sh_num != 0xffffffff) 163 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 164 mutex_unlock(&adev->grbm_idx_mutex); 165 return val; 166 } 167 168 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 169 bool indexed, u32 se_num, 170 u32 sh_num, u32 reg_offset) 171 { 172 if (indexed) { 173 return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); 174 } else { 175 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 176 adev->gfx.config.gb_addr_config) 177 return adev->gfx.config.gb_addr_config; 178 return RREG32(reg_offset); 179 } 180 } 181 182 static int soc_v1_0_read_register(struct amdgpu_device *adev, 183 u32 se_num, u32 sh_num, 184 u32 reg_offset, u32 *value) 185 { 186 uint32_t i; 187 struct soc15_allowed_register_entry *en; 188 189 *value = 0; 190 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 191 en = &soc_v1_0_allowed_read_registers[i]; 192 if (!adev->reg_offset[en->hwip][en->inst]) 193 continue; 194 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 195 + en->reg_offset)) 196 continue; 197 198 *value = soc_v1_0_get_register_value(adev, 199 soc_v1_0_allowed_read_registers[i].grbm_indexed, 200 se_num, sh_num, reg_offset); 201 return 0; 202 } 203 return -EINVAL; 204 } 205 206 static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) 207 { 208 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 209 case IP_VERSION(12, 1, 0): 210 default: 211 return true; 212 } 213 } 214 215 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 216 { 217 218 return false; 219 } 220 221 static enum amd_reset_method 222 soc_v1_0_asic_reset_method(struct amdgpu_device *adev) 223 { 224 if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || 225 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { 226 if (amdgpu_reset_method != -1) 227 dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); 228 229 return AMD_RESET_METHOD_MODE2; 230 } 231 232 return amdgpu_reset_method; 233 } 234 235 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 236 { 237 switch (soc_v1_0_asic_reset_method(adev)) { 238 case AMD_RESET_METHOD_MODE2: 239 dev_info(adev->dev, "MODE2 reset\n"); 240 return amdgpu_dpm_mode2_reset(adev); 241 default: 242 dev_info(adev->dev, "Invalid reset method Not supported\n"); 243 return -EOPNOTSUPP; 244 } 245 246 return 0; 247 } 248 249 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 250 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 251 .read_register = &soc_v1_0_read_register, 252 .get_config_memsize = &soc_v1_0_get_config_memsize, 253 .get_xclk = &soc_v1_0_get_xclk, 254 .need_full_reset = &soc_v1_0_need_full_reset, 255 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 256 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 257 .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 258 .reset = soc_v1_0_asic_reset, 259 .reset_method = &soc_v1_0_asic_reset_method, 260 }; 261 262 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 263 { 264 struct amdgpu_device *adev = ip_block->adev; 265 266 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 267 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 268 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 269 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 270 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 271 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 272 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 273 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 274 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 275 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 276 277 adev->asic_funcs = &soc_v1_0_asic_funcs; 278 279 adev->rev_id = amdgpu_device_get_rev_id(adev); 280 adev->external_rev_id = 0xff; 281 282 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 283 case IP_VERSION(12, 1, 0): 284 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 285 AMD_CG_SUPPORT_GFX_CGLS; 286 adev->pg_flags = 0; 287 adev->external_rev_id = adev->rev_id + 0x50; 288 break; 289 default: 290 /* FIXME: not supported yet */ 291 return -EINVAL; 292 } 293 294 return 0; 295 } 296 297 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 298 { 299 struct amdgpu_device *adev = ip_block->adev; 300 301 /* Enable selfring doorbell aperture late because doorbell BAR 302 * aperture will change if resize BAR successfully in gmc sw_init. 303 */ 304 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 305 306 return 0; 307 } 308 309 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 310 { 311 return 0; 312 } 313 314 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 315 { 316 struct amdgpu_device *adev = ip_block->adev; 317 318 /* enable the doorbell aperture */ 319 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 320 321 return 0; 322 } 323 324 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 325 { 326 struct amdgpu_device *adev = ip_block->adev; 327 328 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 329 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 330 331 return 0; 332 } 333 334 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 335 { 336 return soc_v1_0_common_hw_fini(ip_block); 337 } 338 339 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 340 { 341 return soc_v1_0_common_hw_init(ip_block); 342 } 343 344 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 345 { 346 return true; 347 } 348 349 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 350 enum amd_clockgating_state state) 351 { 352 return 0; 353 } 354 355 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 356 enum amd_powergating_state state) 357 { 358 return 0; 359 } 360 361 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 362 u64 *flags) 363 { 364 return; 365 } 366 367 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 368 .name = "soc_v1_0_common", 369 .early_init = soc_v1_0_common_early_init, 370 .late_init = soc_v1_0_common_late_init, 371 .sw_init = soc_v1_0_common_sw_init, 372 .hw_init = soc_v1_0_common_hw_init, 373 .hw_fini = soc_v1_0_common_hw_fini, 374 .suspend = soc_v1_0_common_suspend, 375 .resume = soc_v1_0_common_resume, 376 .is_idle = soc_v1_0_common_is_idle, 377 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 378 .set_powergating_state = soc_v1_0_common_set_powergating_state, 379 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 380 }; 381 382 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 383 .type = AMD_IP_BLOCK_TYPE_COMMON, 384 .major = 1, 385 .minor = 0, 386 .rev = 0, 387 .funcs = &soc_v1_0_common_ip_funcs, 388 }; 389 390 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 391 { 392 struct amdgpu_device *adev = xcp_mgr->adev; 393 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 394 395 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 396 if (adev->gfx.funcs && 397 adev->gfx.funcs->get_xccs_per_xcp) 398 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 399 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 400 mode = num_xcc / num_xcc_per_xcp; 401 402 if (num_xcc_per_xcp == 1) 403 return AMDGPU_CPX_PARTITION_MODE; 404 405 switch (mode) { 406 case 1: 407 return AMDGPU_SPX_PARTITION_MODE; 408 case 2: 409 return AMDGPU_DPX_PARTITION_MODE; 410 case 3: 411 return AMDGPU_TPX_PARTITION_MODE; 412 case 4: 413 return AMDGPU_QPX_PARTITION_MODE; 414 default: 415 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 416 } 417 418 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 419 } 420 421 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 422 { 423 enum amdgpu_gfx_partition derv_mode, mode; 424 struct amdgpu_device *adev = xcp_mgr->adev; 425 426 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 427 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 428 429 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 430 return derv_mode; 431 432 if (adev->nbio.funcs && 433 adev->nbio.funcs->get_compute_partition_mode) { 434 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 435 if (mode != derv_mode) 436 dev_warn(adev->dev, 437 "Mismatch in compute partition mode - reported : %d derived : %d", 438 mode, derv_mode); 439 } 440 441 return mode; 442 } 443 444 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 445 { 446 int num_xcc, num_xcc_per_xcp = 0; 447 448 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 449 450 switch (mode) { 451 case AMDGPU_SPX_PARTITION_MODE: 452 num_xcc_per_xcp = num_xcc; 453 break; 454 case AMDGPU_DPX_PARTITION_MODE: 455 num_xcc_per_xcp = num_xcc / 2; 456 break; 457 case AMDGPU_TPX_PARTITION_MODE: 458 num_xcc_per_xcp = num_xcc / 3; 459 break; 460 case AMDGPU_QPX_PARTITION_MODE: 461 num_xcc_per_xcp = num_xcc / 4; 462 break; 463 case AMDGPU_CPX_PARTITION_MODE: 464 num_xcc_per_xcp = 1; 465 break; 466 } 467 468 return num_xcc_per_xcp; 469 } 470 471 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 472 enum AMDGPU_XCP_IP_BLOCK ip_id, 473 struct amdgpu_xcp_ip *ip) 474 { 475 struct amdgpu_device *adev = xcp_mgr->adev; 476 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 477 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 478 479 num_sdma = adev->sdma.num_instances; 480 num_vcn = adev->vcn.num_vcn_inst; 481 num_shared_vcn = 1; 482 483 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 484 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 485 486 switch (xcp_mgr->mode) { 487 case AMDGPU_SPX_PARTITION_MODE: 488 case AMDGPU_DPX_PARTITION_MODE: 489 case AMDGPU_TPX_PARTITION_MODE: 490 case AMDGPU_QPX_PARTITION_MODE: 491 case AMDGPU_CPX_PARTITION_MODE: 492 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 493 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 494 break; 495 default: 496 return -EINVAL; 497 } 498 499 if (num_vcn && num_xcp > num_vcn) 500 num_shared_vcn = num_xcp / num_vcn; 501 502 switch (ip_id) { 503 case AMDGPU_XCP_GFXHUB: 504 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 505 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 506 break; 507 case AMDGPU_XCP_GFX: 508 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 509 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 510 break; 511 case AMDGPU_XCP_SDMA: 512 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 513 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 514 break; 515 case AMDGPU_XCP_VCN: 516 ip->inst_mask = 517 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 518 /* TODO : Assign IP funcs */ 519 break; 520 default: 521 return -EINVAL; 522 } 523 524 ip->ip_id = ip_id; 525 526 return 0; 527 } 528 529 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 530 int mode, 531 struct amdgpu_xcp_cfg *xcp_cfg) 532 { 533 struct amdgpu_device *adev = xcp_mgr->adev; 534 int max_res[AMDGPU_XCP_RES_MAX] = {}; 535 bool res_lt_xcp; 536 int num_xcp, i; 537 u16 nps_modes; 538 539 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 540 return -EINVAL; 541 542 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 543 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 544 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 545 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 546 547 switch (mode) { 548 case AMDGPU_SPX_PARTITION_MODE: 549 num_xcp = 1; 550 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 551 break; 552 case AMDGPU_DPX_PARTITION_MODE: 553 num_xcp = 2; 554 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 555 break; 556 case AMDGPU_TPX_PARTITION_MODE: 557 num_xcp = 3; 558 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 559 BIT(AMDGPU_NPS4_PARTITION_MODE); 560 break; 561 case AMDGPU_QPX_PARTITION_MODE: 562 num_xcp = 4; 563 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 564 BIT(AMDGPU_NPS4_PARTITION_MODE); 565 break; 566 case AMDGPU_CPX_PARTITION_MODE: 567 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 568 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 569 BIT(AMDGPU_NPS4_PARTITION_MODE); 570 break; 571 default: 572 return -EINVAL; 573 } 574 575 xcp_cfg->compatible_nps_modes = 576 (adev->gmc.supported_nps_modes & nps_modes); 577 xcp_cfg->num_res = ARRAY_SIZE(max_res); 578 579 for (i = 0; i < xcp_cfg->num_res; i++) { 580 res_lt_xcp = max_res[i] < num_xcp; 581 xcp_cfg->xcp_res[i].id = i; 582 xcp_cfg->xcp_res[i].num_inst = 583 res_lt_xcp ? 1 : max_res[i] / num_xcp; 584 xcp_cfg->xcp_res[i].num_inst = 585 i == AMDGPU_XCP_RES_JPEG ? 586 xcp_cfg->xcp_res[i].num_inst * 587 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 588 xcp_cfg->xcp_res[i].num_shared = 589 res_lt_xcp ? num_xcp / max_res[i] : 1; 590 } 591 592 return 0; 593 } 594 595 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 596 { 597 struct amdgpu_device *adev = xcp_mgr->adev; 598 int num_xcc; 599 600 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 601 602 if (adev->gmc.num_mem_partitions == 1) 603 return AMDGPU_SPX_PARTITION_MODE; 604 605 if (adev->gmc.num_mem_partitions == num_xcc) 606 return AMDGPU_CPX_PARTITION_MODE; 607 608 if (adev->gmc.num_mem_partitions == 2) 609 return AMDGPU_DPX_PARTITION_MODE; 610 611 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 612 } 613 614 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 615 enum amdgpu_gfx_partition mode) 616 { 617 struct amdgpu_device *adev = xcp_mgr->adev; 618 int num_xcc, num_xccs_per_xcp; 619 620 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 621 switch (mode) { 622 case AMDGPU_SPX_PARTITION_MODE: 623 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 624 case AMDGPU_DPX_PARTITION_MODE: 625 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 626 case AMDGPU_TPX_PARTITION_MODE: 627 return (adev->gmc.num_mem_partitions == 1 || 628 adev->gmc.num_mem_partitions == 3) && 629 ((num_xcc % 3) == 0); 630 case AMDGPU_QPX_PARTITION_MODE: 631 num_xccs_per_xcp = num_xcc / 4; 632 return (adev->gmc.num_mem_partitions == 1 || 633 adev->gmc.num_mem_partitions == 4) && 634 (num_xccs_per_xcp >= 2); 635 case AMDGPU_CPX_PARTITION_MODE: 636 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 637 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 638 * num_compute_partitions can't be less than num_mem_partitions 639 */ 640 return ((num_xcc > 1) && 641 (num_xcc % adev->gmc.num_mem_partitions) == 0); 642 default: 643 return false; 644 } 645 646 return false; 647 } 648 649 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 650 { 651 int mode; 652 653 xcp_mgr->avail_xcp_modes = 0; 654 655 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 656 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 657 xcp_mgr->avail_xcp_modes |= BIT(mode); 658 } 659 } 660 661 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 662 int mode, int *num_xcps) 663 { 664 int num_xcc_per_xcp, num_xcc, ret; 665 struct amdgpu_device *adev; 666 u32 flags = 0; 667 668 adev = xcp_mgr->adev; 669 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 670 671 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 672 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 673 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 674 dev_err(adev->dev, 675 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 676 adev->gmc.num_mem_partitions); 677 return -EINVAL; 678 } 679 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 680 dev_err(adev->dev, 681 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 682 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 683 return -EINVAL; 684 } 685 686 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 687 flags |= AMDGPU_XCP_OPS_KFD; 688 689 if (flags & AMDGPU_XCP_OPS_KFD) { 690 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 691 if (ret) 692 goto out; 693 } 694 695 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 696 if (ret) 697 goto unlock; 698 699 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 700 if (adev->gfx.imu.funcs && 701 adev->gfx.imu.funcs->switch_compute_partition) { 702 ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 703 if (ret) 704 goto out; 705 } 706 if (adev->gfx.imu.funcs && 707 adev->gfx.imu.funcs->init_mcm_addr_lut && 708 amdgpu_emu_mode) 709 adev->gfx.imu.funcs->init_mcm_addr_lut(adev); 710 711 /* Init info about new xcps */ 712 *num_xcps = num_xcc / num_xcc_per_xcp; 713 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 714 715 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 716 if (!ret) 717 __soc_v1_0_update_available_partition_mode(xcp_mgr); 718 unlock: 719 if (flags & AMDGPU_XCP_OPS_KFD) 720 amdgpu_amdkfd_unlock_kfd(adev); 721 out: 722 return ret; 723 } 724 725 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 726 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 727 int xcc_id, uint8_t *mem_id) 728 { 729 /* memory/spatial modes validation check is already done */ 730 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 731 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 732 733 return 0; 734 } 735 736 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 737 struct amdgpu_xcp *xcp, uint8_t *mem_id) 738 { 739 struct amdgpu_numa_info numa_info; 740 struct amdgpu_device *adev; 741 uint32_t xcc_mask; 742 int r, i, xcc_id; 743 744 adev = xcp_mgr->adev; 745 /* TODO: BIOS is not returning the right info now 746 * Check on this later 747 */ 748 /* 749 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 750 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 751 */ 752 if (adev->gmc.num_mem_partitions == 1) { 753 /* Only one range */ 754 *mem_id = 0; 755 return 0; 756 } 757 758 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 759 if (r || !xcc_mask) 760 return -EINVAL; 761 762 xcc_id = ffs(xcc_mask) - 1; 763 if (!adev->gmc.is_app_apu) 764 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 765 766 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 767 768 if (r) 769 return r; 770 771 r = -EINVAL; 772 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 773 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 774 *mem_id = i; 775 r = 0; 776 break; 777 } 778 } 779 780 return r; 781 } 782 #endif 783 784 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 785 enum AMDGPU_XCP_IP_BLOCK ip_id, 786 struct amdgpu_xcp_ip *ip) 787 { 788 if (!ip) 789 return -EINVAL; 790 791 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 792 } 793 794 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 795 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 796 .query_partition_mode = &soc_v1_0_query_partition_mode, 797 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 798 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 799 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 800 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 801 #endif 802 }; 803 804 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 805 { 806 int ret; 807 808 if (amdgpu_sriov_vf(adev)) 809 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 810 811 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 812 1, &soc_v1_0_xcp_funcs); 813 if (ret) 814 return ret; 815 816 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 817 /* TODO: Default memory node affinity init */ 818 819 return ret; 820 } 821 822 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 823 { 824 int ret, i; 825 int xcc_inst_per_aid = 4; 826 uint16_t xcc_mask, sdma_mask = 0; 827 828 xcc_mask = adev->gfx.xcc_mask; 829 adev->aid_mask = 0; 830 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 831 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 832 adev->aid_mask |= (1 << i); 833 } 834 835 adev->sdma.num_inst_per_xcc = 2; 836 for_each_inst(i, adev->gfx.xcc_mask) 837 sdma_mask |= 838 GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << 839 (i * adev->sdma.num_inst_per_xcc); 840 adev->sdma.sdma_mask = sdma_mask; 841 adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); 842 843 ret = soc_v1_0_xcp_mgr_init(adev); 844 if (ret) 845 return ret; 846 847 amdgpu_ip_map_init(adev); 848 849 return 0; 850 } 851 852 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 853 { 854 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 855 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 856 return true; 857 else 858 return false; 859 } 860 861 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 862 { 863 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 864 865 /* If it is an XCC reg, normalize the reg to keep 866 * lower 16 bits in local xcc */ 867 868 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 869 return normalized_reg; 870 else 871 return reg; 872 } 873