1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 38 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 39 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 40 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 41 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 42 (offset & 0xFFFF) 43 44 #define MID1_REG_RANGE_0_LOW 0x40000 45 #define MID1_REG_RANGE_0_HIGH 0x80000 46 #define NORMALIZE_MID_REG_OFFSET(offset) \ 47 (offset & 0x3FFFF) 48 49 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { 50 .codec_count = 0, 51 .codec_array = NULL, 52 }; 53 54 static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 56 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 57 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), 64 .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, 65 }; 66 67 static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, 68 const struct amdgpu_video_codecs **codecs) 69 { 70 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 71 case IP_VERSION(5, 0, 2): 72 if (encode) 73 *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; 74 else 75 *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; 76 return 0; 77 default: 78 return -EINVAL; 79 } 80 } 81 82 /* Initialized doorbells for amdgpu including multimedia 83 * KFD can use all the rest in 2M doorbell bar */ 84 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 85 { 86 int i; 87 88 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 89 90 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 91 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 92 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 93 94 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 95 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 96 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 97 98 adev->doorbell_index.sdma_doorbell_range = 14; 99 for (i = 0; i < adev->sdma.num_instances; i++) 100 adev->doorbell_index.sdma_engine[i] = 101 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 102 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 103 104 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 105 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 106 107 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 108 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 109 110 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 111 } 112 113 /* Fixed pattern for upper 32bits smn addressing. 114 * bit[47:40]: Socket ID 115 * bit[39:34]: Die ID 116 * bit[32]: local or remote die in same socket 117 * The ext_id is comprised of socket_id and die_id. 118 * ext_id = (socket_id << 6) | (die_id) 119 */ 120 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 121 { 122 u64 ext_offset; 123 int socket_id, die_id; 124 125 /* local die routing for MID0 on local socket */ 126 if (ext_id == 0) 127 return 0; 128 129 die_id = ext_id & 0x3; 130 socket_id = (ext_id >> 6) & 0xff; 131 132 /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 133 if (socket_id == 0) 134 ext_offset = ((u64)die_id << 34) | (1ULL << 32); 135 else if (socket_id != 0 && die_id != 0) 136 ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 137 (3ULL << 32); 138 else 139 ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 140 141 return ext_offset; 142 } 143 144 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 145 { 146 return adev->nbio.funcs->get_memsize(adev); 147 } 148 149 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 150 { 151 return adev->clock.spll.reference_freq; 152 } 153 154 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 155 u32 me, u32 pipe, 156 u32 queue, u32 vmid, 157 int xcc_id) 158 { 159 u32 grbm_gfx_cntl = 0; 160 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 161 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 162 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 163 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 164 165 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 166 } 167 168 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 169 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 170 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 171 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 172 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 173 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 174 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 175 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 176 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 177 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 178 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 179 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 180 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 181 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 182 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 183 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 184 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 185 }; 186 187 188 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 189 bool indexed, u32 se_num, 190 u32 sh_num, u32 reg_offset) 191 { 192 if (indexed) { 193 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 194 } else { 195 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 196 adev->gfx.config.gb_addr_config) 197 return adev->gfx.config.gb_addr_config; 198 return RREG32(reg_offset); 199 } 200 } 201 202 static int soc_v1_0_read_register(struct amdgpu_device *adev, 203 u32 se_num, u32 sh_num, 204 u32 reg_offset, u32 *value) 205 { 206 uint32_t i; 207 struct soc15_allowed_register_entry *en; 208 209 *value = 0; 210 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 211 en = &soc_v1_0_allowed_read_registers[i]; 212 if (!adev->reg_offset[en->hwip][en->inst]) 213 continue; 214 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 215 + en->reg_offset)) 216 continue; 217 218 *value = soc_v1_0_get_register_value(adev, 219 soc_v1_0_allowed_read_registers[i].grbm_indexed, 220 se_num, sh_num, reg_offset); 221 return 0; 222 } 223 return -EINVAL; 224 } 225 226 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 227 { 228 229 return false; 230 } 231 232 static enum amd_reset_method 233 soc_v1_0_asic_reset_method(struct amdgpu_device *adev) 234 { 235 if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || 236 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { 237 if (amdgpu_reset_method != -1) 238 dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); 239 240 return AMD_RESET_METHOD_MODE2; 241 } 242 243 return amdgpu_reset_method; 244 } 245 246 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 247 { 248 switch (soc_v1_0_asic_reset_method(adev)) { 249 case AMD_RESET_METHOD_MODE2: 250 dev_info(adev->dev, "MODE2 reset\n"); 251 return amdgpu_dpm_mode2_reset(adev); 252 default: 253 dev_info(adev->dev, "Invalid reset method Not supported\n"); 254 return -EOPNOTSUPP; 255 } 256 257 return 0; 258 } 259 260 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 261 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 262 .read_register = &soc_v1_0_read_register, 263 .get_config_memsize = &soc_v1_0_get_config_memsize, 264 .get_xclk = &soc_v1_0_get_xclk, 265 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 266 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 267 .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 268 .reset = soc_v1_0_asic_reset, 269 .reset_method = &soc_v1_0_asic_reset_method, 270 .query_video_codecs = &soc_v1_0_query_video_codecs, 271 }; 272 273 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 274 { 275 struct amdgpu_device *adev = ip_block->adev; 276 277 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 278 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 279 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 280 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 281 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 282 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 283 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 284 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 285 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 286 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 287 288 adev->asic_funcs = &soc_v1_0_asic_funcs; 289 290 adev->rev_id = amdgpu_device_get_rev_id(adev); 291 adev->external_rev_id = 0xff; 292 293 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 294 case IP_VERSION(12, 1, 0): 295 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 296 AMD_CG_SUPPORT_GFX_CGLS; 297 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 298 adev->external_rev_id = adev->rev_id + 0x50; 299 break; 300 default: 301 /* FIXME: not supported yet */ 302 return -EINVAL; 303 } 304 305 adev->nbio.funcs->init_registers(adev); 306 307 return 0; 308 } 309 310 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 311 { 312 struct amdgpu_device *adev = ip_block->adev; 313 314 /* Enable selfring doorbell aperture late because doorbell BAR 315 * aperture will change if resize BAR successfully in gmc sw_init. 316 */ 317 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 318 319 return 0; 320 } 321 322 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 323 { 324 return 0; 325 } 326 327 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 328 { 329 struct amdgpu_device *adev = ip_block->adev; 330 331 /* enable the doorbell aperture */ 332 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 333 334 return 0; 335 } 336 337 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 338 { 339 struct amdgpu_device *adev = ip_block->adev; 340 341 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 342 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 343 344 return 0; 345 } 346 347 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 348 { 349 return soc_v1_0_common_hw_fini(ip_block); 350 } 351 352 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 353 { 354 return soc_v1_0_common_hw_init(ip_block); 355 } 356 357 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 358 { 359 return true; 360 } 361 362 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 363 enum amd_clockgating_state state) 364 { 365 return 0; 366 } 367 368 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 369 enum amd_powergating_state state) 370 { 371 return 0; 372 } 373 374 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 375 u64 *flags) 376 { 377 return; 378 } 379 380 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 381 .name = "soc_v1_0_common", 382 .early_init = soc_v1_0_common_early_init, 383 .late_init = soc_v1_0_common_late_init, 384 .sw_init = soc_v1_0_common_sw_init, 385 .hw_init = soc_v1_0_common_hw_init, 386 .hw_fini = soc_v1_0_common_hw_fini, 387 .suspend = soc_v1_0_common_suspend, 388 .resume = soc_v1_0_common_resume, 389 .is_idle = soc_v1_0_common_is_idle, 390 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 391 .set_powergating_state = soc_v1_0_common_set_powergating_state, 392 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 393 }; 394 395 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 396 .type = AMD_IP_BLOCK_TYPE_COMMON, 397 .major = 1, 398 .minor = 0, 399 .rev = 0, 400 .funcs = &soc_v1_0_common_ip_funcs, 401 }; 402 403 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 404 { 405 struct amdgpu_device *adev = xcp_mgr->adev; 406 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 407 408 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 409 if (adev->gfx.funcs && 410 adev->gfx.funcs->get_xccs_per_xcp) 411 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 412 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 413 mode = num_xcc / num_xcc_per_xcp; 414 415 if (num_xcc_per_xcp == 1) 416 return AMDGPU_CPX_PARTITION_MODE; 417 418 switch (mode) { 419 case 1: 420 return AMDGPU_SPX_PARTITION_MODE; 421 case 2: 422 return AMDGPU_DPX_PARTITION_MODE; 423 case 3: 424 return AMDGPU_TPX_PARTITION_MODE; 425 case 4: 426 return AMDGPU_QPX_PARTITION_MODE; 427 default: 428 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 429 } 430 431 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 432 } 433 434 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 435 { 436 enum amdgpu_gfx_partition derv_mode, mode; 437 struct amdgpu_device *adev = xcp_mgr->adev; 438 439 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 440 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 441 442 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 443 return derv_mode; 444 445 if (adev->nbio.funcs && 446 adev->nbio.funcs->get_compute_partition_mode) { 447 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 448 if (mode != derv_mode) 449 dev_warn(adev->dev, 450 "Mismatch in compute partition mode - reported : %d derived : %d", 451 mode, derv_mode); 452 } 453 454 return mode; 455 } 456 457 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 458 { 459 int num_xcc, num_xcc_per_xcp = 0; 460 461 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 462 463 switch (mode) { 464 case AMDGPU_SPX_PARTITION_MODE: 465 num_xcc_per_xcp = num_xcc; 466 break; 467 case AMDGPU_DPX_PARTITION_MODE: 468 num_xcc_per_xcp = num_xcc / 2; 469 break; 470 case AMDGPU_TPX_PARTITION_MODE: 471 num_xcc_per_xcp = num_xcc / 3; 472 break; 473 case AMDGPU_QPX_PARTITION_MODE: 474 num_xcc_per_xcp = num_xcc / 4; 475 break; 476 case AMDGPU_CPX_PARTITION_MODE: 477 num_xcc_per_xcp = 1; 478 break; 479 } 480 481 return num_xcc_per_xcp; 482 } 483 484 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 485 enum AMDGPU_XCP_IP_BLOCK ip_id, 486 struct amdgpu_xcp_ip *ip) 487 { 488 struct amdgpu_device *adev = xcp_mgr->adev; 489 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 490 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 491 492 num_sdma = adev->sdma.num_instances; 493 num_vcn = adev->vcn.num_vcn_inst; 494 num_shared_vcn = 1; 495 496 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 497 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 498 499 switch (xcp_mgr->mode) { 500 case AMDGPU_SPX_PARTITION_MODE: 501 case AMDGPU_DPX_PARTITION_MODE: 502 case AMDGPU_TPX_PARTITION_MODE: 503 case AMDGPU_QPX_PARTITION_MODE: 504 case AMDGPU_CPX_PARTITION_MODE: 505 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 506 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 507 break; 508 default: 509 return -EINVAL; 510 } 511 512 if (num_vcn && num_xcp > num_vcn) 513 num_shared_vcn = num_xcp / num_vcn; 514 515 switch (ip_id) { 516 case AMDGPU_XCP_GFXHUB: 517 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 518 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 519 break; 520 case AMDGPU_XCP_GFX: 521 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 522 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 523 break; 524 case AMDGPU_XCP_SDMA: 525 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 526 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 527 break; 528 case AMDGPU_XCP_VCN: 529 ip->inst_mask = 530 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 531 /* TODO : Assign IP funcs */ 532 break; 533 default: 534 return -EINVAL; 535 } 536 537 ip->ip_id = ip_id; 538 539 return 0; 540 } 541 542 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 543 int mode, 544 struct amdgpu_xcp_cfg *xcp_cfg) 545 { 546 struct amdgpu_device *adev = xcp_mgr->adev; 547 int max_res[AMDGPU_XCP_RES_MAX] = {}; 548 bool res_lt_xcp; 549 int num_xcp, i; 550 u16 nps_modes; 551 552 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 553 return -EINVAL; 554 555 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 556 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 557 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 558 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 559 560 switch (mode) { 561 case AMDGPU_SPX_PARTITION_MODE: 562 num_xcp = 1; 563 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 564 break; 565 case AMDGPU_DPX_PARTITION_MODE: 566 num_xcp = 2; 567 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 568 break; 569 case AMDGPU_TPX_PARTITION_MODE: 570 num_xcp = 3; 571 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 572 BIT(AMDGPU_NPS4_PARTITION_MODE); 573 break; 574 case AMDGPU_QPX_PARTITION_MODE: 575 num_xcp = 4; 576 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 577 BIT(AMDGPU_NPS4_PARTITION_MODE); 578 break; 579 case AMDGPU_CPX_PARTITION_MODE: 580 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 581 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 582 BIT(AMDGPU_NPS4_PARTITION_MODE); 583 break; 584 default: 585 return -EINVAL; 586 } 587 588 xcp_cfg->compatible_nps_modes = 589 (adev->gmc.supported_nps_modes & nps_modes); 590 xcp_cfg->num_res = ARRAY_SIZE(max_res); 591 592 for (i = 0; i < xcp_cfg->num_res; i++) { 593 xcp_cfg->xcp_res[i].id = i; 594 if (!max_res[i]) 595 continue; 596 res_lt_xcp = max_res[i] < num_xcp; 597 xcp_cfg->xcp_res[i].num_inst = 598 res_lt_xcp ? 1 : max_res[i] / num_xcp; 599 xcp_cfg->xcp_res[i].num_inst = 600 i == AMDGPU_XCP_RES_JPEG ? 601 xcp_cfg->xcp_res[i].num_inst * 602 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 603 xcp_cfg->xcp_res[i].num_shared = 604 res_lt_xcp ? num_xcp / max_res[i] : 1; 605 } 606 607 return 0; 608 } 609 610 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 611 { 612 struct amdgpu_device *adev = xcp_mgr->adev; 613 int num_xcc; 614 615 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 616 617 if (adev->gmc.num_mem_partitions == 1) 618 return AMDGPU_SPX_PARTITION_MODE; 619 620 if (adev->gmc.num_mem_partitions == num_xcc) 621 return AMDGPU_CPX_PARTITION_MODE; 622 623 if (adev->gmc.num_mem_partitions == 2) 624 return AMDGPU_DPX_PARTITION_MODE; 625 626 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 627 } 628 629 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 630 enum amdgpu_gfx_partition mode) 631 { 632 struct amdgpu_device *adev = xcp_mgr->adev; 633 int num_xcc, num_xccs_per_xcp; 634 635 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 636 switch (mode) { 637 case AMDGPU_SPX_PARTITION_MODE: 638 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 639 case AMDGPU_DPX_PARTITION_MODE: 640 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 641 case AMDGPU_TPX_PARTITION_MODE: 642 return (adev->gmc.num_mem_partitions == 1 || 643 adev->gmc.num_mem_partitions == 3) && 644 ((num_xcc % 3) == 0); 645 case AMDGPU_QPX_PARTITION_MODE: 646 num_xccs_per_xcp = num_xcc / 4; 647 return (adev->gmc.num_mem_partitions == 1 || 648 adev->gmc.num_mem_partitions == 4) && 649 (num_xccs_per_xcp >= 2); 650 case AMDGPU_CPX_PARTITION_MODE: 651 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 652 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 653 * num_compute_partitions can't be less than num_mem_partitions 654 */ 655 return ((num_xcc > 1) && 656 (num_xcc % adev->gmc.num_mem_partitions) == 0); 657 default: 658 return false; 659 } 660 661 return false; 662 } 663 664 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 665 { 666 int mode; 667 668 xcp_mgr->avail_xcp_modes = 0; 669 670 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 671 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 672 xcp_mgr->avail_xcp_modes |= BIT(mode); 673 } 674 } 675 676 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 677 int mode, int *num_xcps) 678 { 679 int num_xcc_per_xcp, num_xcc, ret; 680 struct amdgpu_device *adev; 681 u32 flags = 0; 682 683 adev = xcp_mgr->adev; 684 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 685 686 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 687 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 688 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 689 dev_err(adev->dev, 690 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 691 adev->gmc.num_mem_partitions); 692 return -EINVAL; 693 } 694 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 695 dev_err(adev->dev, 696 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 697 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 698 return -EINVAL; 699 } 700 701 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 702 flags |= AMDGPU_XCP_OPS_KFD; 703 704 if (flags & AMDGPU_XCP_OPS_KFD) { 705 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 706 if (ret) 707 goto out; 708 } 709 710 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 711 if (ret) 712 goto unlock; 713 714 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 715 if (adev->gfx.imu.funcs && 716 adev->gfx.imu.funcs->switch_compute_partition) 717 adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 718 719 /* Init info about new xcps */ 720 *num_xcps = num_xcc / num_xcc_per_xcp; 721 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 722 723 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 724 if (!ret) 725 __soc_v1_0_update_available_partition_mode(xcp_mgr); 726 unlock: 727 if (flags & AMDGPU_XCP_OPS_KFD) 728 amdgpu_amdkfd_unlock_kfd(adev); 729 out: 730 return ret; 731 } 732 733 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 734 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 735 int xcc_id, uint8_t *mem_id) 736 { 737 /* memory/spatial modes validation check is already done */ 738 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 739 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 740 741 return 0; 742 } 743 744 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 745 struct amdgpu_xcp *xcp, uint8_t *mem_id) 746 { 747 struct amdgpu_numa_info numa_info; 748 struct amdgpu_device *adev; 749 uint32_t xcc_mask; 750 int r, i, xcc_id; 751 752 adev = xcp_mgr->adev; 753 /* TODO: BIOS is not returning the right info now 754 * Check on this later 755 */ 756 /* 757 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 758 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 759 */ 760 if (adev->gmc.num_mem_partitions == 1) { 761 /* Only one range */ 762 *mem_id = 0; 763 return 0; 764 } 765 766 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 767 if (r || !xcc_mask) 768 return -EINVAL; 769 770 xcc_id = ffs(xcc_mask) - 1; 771 if (!adev->gmc.is_app_apu) 772 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 773 774 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 775 776 if (r) 777 return r; 778 779 r = -EINVAL; 780 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 781 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 782 *mem_id = i; 783 r = 0; 784 break; 785 } 786 } 787 788 return r; 789 } 790 #endif 791 792 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 793 enum AMDGPU_XCP_IP_BLOCK ip_id, 794 struct amdgpu_xcp_ip *ip) 795 { 796 if (!ip) 797 return -EINVAL; 798 799 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 800 } 801 802 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 803 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 804 .query_partition_mode = &soc_v1_0_query_partition_mode, 805 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 806 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 807 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 808 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 809 #endif 810 }; 811 812 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 813 { 814 int ret; 815 816 if (amdgpu_sriov_vf(adev)) 817 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 818 819 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 820 1, &soc_v1_0_xcp_funcs); 821 if (ret) 822 return ret; 823 824 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 825 /* TODO: Default memory node affinity init */ 826 827 return ret; 828 } 829 830 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 831 { 832 int ret, i; 833 int xcc_inst_per_aid = 4; 834 uint16_t xcc_mask, sdma_mask = 0; 835 836 xcc_mask = adev->gfx.xcc_mask; 837 adev->aid_mask = 0; 838 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 839 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 840 adev->aid_mask |= (1 << i); 841 } 842 843 adev->sdma.num_inst_per_xcc = 2; 844 for_each_inst(i, adev->gfx.xcc_mask) 845 sdma_mask |= 846 GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << 847 (i * adev->sdma.num_inst_per_xcc); 848 adev->sdma.sdma_mask = sdma_mask; 849 adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); 850 851 ret = soc_v1_0_xcp_mgr_init(adev); 852 if (ret) 853 return ret; 854 855 amdgpu_ip_map_init(adev); 856 857 return 0; 858 } 859 860 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 861 { 862 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 863 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 864 return true; 865 else 866 return false; 867 } 868 869 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 870 { 871 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 872 873 /* If it is an XCC reg, normalize the reg to keep 874 * lower 16 bits in local xcc */ 875 876 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 877 return normalized_reg; 878 else 879 return reg; 880 } 881 882 bool soc_v1_0_mid1_reg_range(uint32_t reg) 883 { 884 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 885 886 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 887 return false; 888 889 if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) 890 return true; 891 else 892 return false; 893 } 894 895 uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) 896 { 897 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 898 899 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 900 return soc_v1_0_normalize_xcc_reg_offset(reg); 901 902 /* check if the reg offset is inside MID1. */ 903 if (soc_v1_0_mid1_reg_range(reg)) 904 return NORMALIZE_MID_REG_OFFSET(reg); 905 906 return reg; 907 } 908 909