1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 38 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 39 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 40 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 41 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 42 (offset & 0xFFFF) 43 44 /* Initialized doorbells for amdgpu including multimedia 45 * KFD can use all the rest in 2M doorbell bar */ 46 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 47 { 48 int i; 49 50 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 51 52 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 53 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 54 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 55 56 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 57 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 58 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 59 60 adev->doorbell_index.sdma_doorbell_range = 20; 61 for (i = 0; i < adev->sdma.num_instances; i++) 62 adev->doorbell_index.sdma_engine[i] = 63 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 64 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 65 66 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 67 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 68 69 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 70 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 71 72 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 73 } 74 75 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 76 { 77 return adev->nbio.funcs->get_memsize(adev); 78 } 79 80 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 81 { 82 return adev->clock.spll.reference_freq; 83 } 84 85 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 86 u32 me, u32 pipe, 87 u32 queue, u32 vmid, 88 int xcc_id) 89 { 90 u32 grbm_gfx_cntl = 0; 91 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 92 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 93 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 94 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 95 96 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 97 } 98 99 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 100 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 101 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 102 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 103 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 104 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 105 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 106 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 107 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 108 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 109 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 110 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 111 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 112 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 113 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 114 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 115 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 116 }; 117 118 static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, 119 u32 se_num, 120 u32 sh_num, 121 u32 reg_offset) 122 { 123 uint32_t val; 124 125 mutex_lock(&adev->grbm_idx_mutex); 126 if (se_num != 0xffffffff || sh_num != 0xffffffff) 127 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 128 129 val = RREG32(reg_offset); 130 131 if (se_num != 0xffffffff || sh_num != 0xffffffff) 132 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 133 mutex_unlock(&adev->grbm_idx_mutex); 134 return val; 135 } 136 137 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 138 bool indexed, u32 se_num, 139 u32 sh_num, u32 reg_offset) 140 { 141 if (indexed) { 142 return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); 143 } else { 144 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 145 adev->gfx.config.gb_addr_config) 146 return adev->gfx.config.gb_addr_config; 147 return RREG32(reg_offset); 148 } 149 } 150 151 static int soc_v1_0_read_register(struct amdgpu_device *adev, 152 u32 se_num, u32 sh_num, 153 u32 reg_offset, u32 *value) 154 { 155 uint32_t i; 156 struct soc15_allowed_register_entry *en; 157 158 *value = 0; 159 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 160 en = &soc_v1_0_allowed_read_registers[i]; 161 if (!adev->reg_offset[en->hwip][en->inst]) 162 continue; 163 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 164 + en->reg_offset)) 165 continue; 166 167 *value = soc_v1_0_get_register_value(adev, 168 soc_v1_0_allowed_read_registers[i].grbm_indexed, 169 se_num, sh_num, reg_offset); 170 return 0; 171 } 172 return -EINVAL; 173 } 174 175 static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) 176 { 177 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 178 case IP_VERSION(12, 1, 0): 179 default: 180 return true; 181 } 182 } 183 184 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 185 { 186 u32 sol_reg; 187 188 if (adev->flags & AMD_IS_APU) 189 return false; 190 191 /* Check sOS sign of life register to confirm sys driver and sOS 192 * are already been loaded. 193 */ 194 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 195 if (sol_reg) 196 return true; 197 198 return false; 199 } 200 201 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 202 { 203 return 0; 204 } 205 206 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 207 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 208 .read_register = &soc_v1_0_read_register, 209 .get_config_memsize = &soc_v1_0_get_config_memsize, 210 .get_xclk = &soc_v1_0_get_xclk, 211 .need_full_reset = &soc_v1_0_need_full_reset, 212 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 213 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 214 .reset = soc_v1_0_asic_reset, 215 }; 216 217 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 218 { 219 struct amdgpu_device *adev = ip_block->adev; 220 221 adev->smc_rreg = NULL; 222 adev->smc_wreg = NULL; 223 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 224 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 225 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 226 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 227 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 228 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 229 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 230 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 231 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 232 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 233 adev->uvd_ctx_rreg = NULL; 234 adev->uvd_ctx_wreg = NULL; 235 adev->didt_rreg = NULL; 236 adev->didt_wreg = NULL; 237 238 adev->asic_funcs = &soc_v1_0_asic_funcs; 239 240 adev->rev_id = amdgpu_device_get_rev_id(adev); 241 adev->external_rev_id = 0xff; 242 243 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 244 case IP_VERSION(12, 1, 0): 245 adev->cg_flags = 0; 246 adev->pg_flags = 0; 247 adev->external_rev_id = adev->rev_id + 0x50; 248 break; 249 default: 250 /* FIXME: not supported yet */ 251 return -EINVAL; 252 } 253 254 return 0; 255 } 256 257 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 258 { 259 struct amdgpu_device *adev = ip_block->adev; 260 261 /* Enable selfring doorbell aperture late because doorbell BAR 262 * aperture will change if resize BAR successfully in gmc sw_init. 263 */ 264 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 265 266 return 0; 267 } 268 269 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 270 { 271 return 0; 272 } 273 274 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 275 { 276 struct amdgpu_device *adev = ip_block->adev; 277 278 /* enable the doorbell aperture */ 279 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 280 281 return 0; 282 } 283 284 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 285 { 286 struct amdgpu_device *adev = ip_block->adev; 287 288 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 289 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 290 291 return 0; 292 } 293 294 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 295 { 296 return soc_v1_0_common_hw_fini(ip_block); 297 } 298 299 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 300 { 301 return soc_v1_0_common_hw_init(ip_block); 302 } 303 304 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 305 { 306 return true; 307 } 308 309 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 310 enum amd_clockgating_state state) 311 { 312 return 0; 313 } 314 315 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 316 enum amd_powergating_state state) 317 { 318 return 0; 319 } 320 321 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 322 u64 *flags) 323 { 324 return; 325 } 326 327 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 328 .name = "soc_v1_0_common", 329 .early_init = soc_v1_0_common_early_init, 330 .late_init = soc_v1_0_common_late_init, 331 .sw_init = soc_v1_0_common_sw_init, 332 .hw_init = soc_v1_0_common_hw_init, 333 .hw_fini = soc_v1_0_common_hw_fini, 334 .suspend = soc_v1_0_common_suspend, 335 .resume = soc_v1_0_common_resume, 336 .is_idle = soc_v1_0_common_is_idle, 337 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 338 .set_powergating_state = soc_v1_0_common_set_powergating_state, 339 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 340 }; 341 342 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 343 .type = AMD_IP_BLOCK_TYPE_COMMON, 344 .major = 1, 345 .minor = 0, 346 .rev = 0, 347 .funcs = &soc_v1_0_common_ip_funcs, 348 }; 349 350 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 351 { 352 struct amdgpu_device *adev = xcp_mgr->adev; 353 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 354 355 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 356 if (adev->gfx.funcs && 357 adev->gfx.funcs->get_xccs_per_xcp) 358 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 359 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 360 mode = num_xcc / num_xcc_per_xcp; 361 362 if (num_xcc_per_xcp == 1) 363 return AMDGPU_CPX_PARTITION_MODE; 364 365 switch (mode) { 366 case 1: 367 return AMDGPU_SPX_PARTITION_MODE; 368 case 2: 369 return AMDGPU_DPX_PARTITION_MODE; 370 case 3: 371 return AMDGPU_TPX_PARTITION_MODE; 372 case 4: 373 return AMDGPU_QPX_PARTITION_MODE; 374 default: 375 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 376 } 377 378 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 379 } 380 381 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 382 { 383 enum amdgpu_gfx_partition derv_mode, mode; 384 struct amdgpu_device *adev = xcp_mgr->adev; 385 386 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 387 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 388 389 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 390 return derv_mode; 391 392 if (adev->nbio.funcs && 393 adev->nbio.funcs->get_compute_partition_mode) { 394 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 395 if (mode != derv_mode) 396 dev_warn(adev->dev, 397 "Mismatch in compute partition mode - reported : %d derived : %d", 398 mode, derv_mode); 399 } 400 401 return mode; 402 } 403 404 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 405 { 406 int num_xcc, num_xcc_per_xcp = 0; 407 408 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 409 410 switch (mode) { 411 case AMDGPU_SPX_PARTITION_MODE: 412 num_xcc_per_xcp = num_xcc; 413 break; 414 case AMDGPU_DPX_PARTITION_MODE: 415 num_xcc_per_xcp = num_xcc / 2; 416 break; 417 case AMDGPU_TPX_PARTITION_MODE: 418 num_xcc_per_xcp = num_xcc / 3; 419 break; 420 case AMDGPU_QPX_PARTITION_MODE: 421 num_xcc_per_xcp = num_xcc / 4; 422 break; 423 case AMDGPU_CPX_PARTITION_MODE: 424 num_xcc_per_xcp = 1; 425 break; 426 } 427 428 return num_xcc_per_xcp; 429 } 430 431 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 432 enum AMDGPU_XCP_IP_BLOCK ip_id, 433 struct amdgpu_xcp_ip *ip) 434 { 435 struct amdgpu_device *adev = xcp_mgr->adev; 436 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 437 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 438 439 num_sdma = adev->sdma.num_instances; 440 num_vcn = adev->vcn.num_vcn_inst; 441 num_shared_vcn = 1; 442 443 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 444 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 445 446 switch (xcp_mgr->mode) { 447 case AMDGPU_SPX_PARTITION_MODE: 448 case AMDGPU_DPX_PARTITION_MODE: 449 case AMDGPU_TPX_PARTITION_MODE: 450 case AMDGPU_QPX_PARTITION_MODE: 451 case AMDGPU_CPX_PARTITION_MODE: 452 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 453 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 454 break; 455 default: 456 return -EINVAL; 457 } 458 459 if (num_vcn && num_xcp > num_vcn) 460 num_shared_vcn = num_xcp / num_vcn; 461 462 switch (ip_id) { 463 case AMDGPU_XCP_GFXHUB: 464 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 465 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 466 break; 467 case AMDGPU_XCP_GFX: 468 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 469 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 470 break; 471 case AMDGPU_XCP_SDMA: 472 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 473 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 474 break; 475 case AMDGPU_XCP_VCN: 476 ip->inst_mask = 477 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 478 /* TODO : Assign IP funcs */ 479 break; 480 default: 481 return -EINVAL; 482 } 483 484 ip->ip_id = ip_id; 485 486 return 0; 487 } 488 489 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 490 int mode, 491 struct amdgpu_xcp_cfg *xcp_cfg) 492 { 493 struct amdgpu_device *adev = xcp_mgr->adev; 494 int max_res[AMDGPU_XCP_RES_MAX] = {}; 495 bool res_lt_xcp; 496 int num_xcp, i; 497 u16 nps_modes; 498 499 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 500 return -EINVAL; 501 502 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 503 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 504 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 505 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 506 507 switch (mode) { 508 case AMDGPU_SPX_PARTITION_MODE: 509 num_xcp = 1; 510 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 511 break; 512 case AMDGPU_DPX_PARTITION_MODE: 513 num_xcp = 2; 514 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 515 break; 516 case AMDGPU_TPX_PARTITION_MODE: 517 num_xcp = 3; 518 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 519 BIT(AMDGPU_NPS4_PARTITION_MODE); 520 break; 521 case AMDGPU_QPX_PARTITION_MODE: 522 num_xcp = 4; 523 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 524 BIT(AMDGPU_NPS4_PARTITION_MODE); 525 break; 526 case AMDGPU_CPX_PARTITION_MODE: 527 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 528 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 529 BIT(AMDGPU_NPS4_PARTITION_MODE); 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 xcp_cfg->compatible_nps_modes = 536 (adev->gmc.supported_nps_modes & nps_modes); 537 xcp_cfg->num_res = ARRAY_SIZE(max_res); 538 539 for (i = 0; i < xcp_cfg->num_res; i++) { 540 res_lt_xcp = max_res[i] < num_xcp; 541 xcp_cfg->xcp_res[i].id = i; 542 xcp_cfg->xcp_res[i].num_inst = 543 res_lt_xcp ? 1 : max_res[i] / num_xcp; 544 xcp_cfg->xcp_res[i].num_inst = 545 i == AMDGPU_XCP_RES_JPEG ? 546 xcp_cfg->xcp_res[i].num_inst * 547 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 548 xcp_cfg->xcp_res[i].num_shared = 549 res_lt_xcp ? num_xcp / max_res[i] : 1; 550 } 551 552 return 0; 553 } 554 555 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 556 { 557 struct amdgpu_device *adev = xcp_mgr->adev; 558 int num_xcc; 559 560 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 561 562 if (adev->gmc.num_mem_partitions == 1) 563 return AMDGPU_SPX_PARTITION_MODE; 564 565 if (adev->gmc.num_mem_partitions == num_xcc) 566 return AMDGPU_CPX_PARTITION_MODE; 567 568 if (adev->gmc.num_mem_partitions == 2) 569 return AMDGPU_DPX_PARTITION_MODE; 570 571 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 572 } 573 574 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 575 enum amdgpu_gfx_partition mode) 576 { 577 struct amdgpu_device *adev = xcp_mgr->adev; 578 int num_xcc, num_xccs_per_xcp; 579 580 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 581 switch (mode) { 582 case AMDGPU_SPX_PARTITION_MODE: 583 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 584 case AMDGPU_DPX_PARTITION_MODE: 585 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 586 case AMDGPU_TPX_PARTITION_MODE: 587 return (adev->gmc.num_mem_partitions == 1 || 588 adev->gmc.num_mem_partitions == 3) && 589 ((num_xcc % 3) == 0); 590 case AMDGPU_QPX_PARTITION_MODE: 591 num_xccs_per_xcp = num_xcc / 4; 592 return (adev->gmc.num_mem_partitions == 1 || 593 adev->gmc.num_mem_partitions == 4) && 594 (num_xccs_per_xcp >= 2); 595 case AMDGPU_CPX_PARTITION_MODE: 596 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 597 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 598 * num_compute_partitions can't be less than num_mem_partitions 599 */ 600 return ((num_xcc > 1) && 601 (num_xcc % adev->gmc.num_mem_partitions) == 0); 602 default: 603 return false; 604 } 605 606 return false; 607 } 608 609 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 610 { 611 int mode; 612 613 xcp_mgr->avail_xcp_modes = 0; 614 615 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 616 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 617 xcp_mgr->avail_xcp_modes |= BIT(mode); 618 } 619 } 620 621 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 622 int mode, int *num_xcps) 623 { 624 int num_xcc_per_xcp, num_xcc, ret; 625 struct amdgpu_device *adev; 626 u32 flags = 0; 627 628 adev = xcp_mgr->adev; 629 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 630 631 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 632 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 633 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 634 dev_err(adev->dev, 635 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 636 adev->gmc.num_mem_partitions); 637 return -EINVAL; 638 } 639 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 640 dev_err(adev->dev, 641 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 642 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 643 return -EINVAL; 644 } 645 646 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 647 flags |= AMDGPU_XCP_OPS_KFD; 648 649 if (flags & AMDGPU_XCP_OPS_KFD) { 650 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 651 if (ret) 652 goto out; 653 } 654 655 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 656 if (ret) 657 goto unlock; 658 659 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 660 if (adev->gfx.imu.funcs && 661 adev->gfx.imu.funcs->switch_compute_partition) { 662 ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 663 if (ret) 664 goto out; 665 } 666 if (adev->gfx.imu.funcs && 667 adev->gfx.imu.funcs->init_mcm_addr_lut && 668 amdgpu_emu_mode) 669 adev->gfx.imu.funcs->init_mcm_addr_lut(adev); 670 671 /* Init info about new xcps */ 672 *num_xcps = num_xcc / num_xcc_per_xcp; 673 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 674 675 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 676 if (!ret) 677 __soc_v1_0_update_available_partition_mode(xcp_mgr); 678 unlock: 679 if (flags & AMDGPU_XCP_OPS_KFD) 680 amdgpu_amdkfd_unlock_kfd(adev); 681 out: 682 return ret; 683 } 684 685 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 686 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 687 int xcc_id, uint8_t *mem_id) 688 { 689 /* memory/spatial modes validation check is already done */ 690 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 691 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 692 693 return 0; 694 } 695 696 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 697 struct amdgpu_xcp *xcp, uint8_t *mem_id) 698 { 699 struct amdgpu_numa_info numa_info; 700 struct amdgpu_device *adev; 701 uint32_t xcc_mask; 702 int r, i, xcc_id; 703 704 adev = xcp_mgr->adev; 705 /* TODO: BIOS is not returning the right info now 706 * Check on this later 707 */ 708 /* 709 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 710 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 711 */ 712 if (adev->gmc.num_mem_partitions == 1) { 713 /* Only one range */ 714 *mem_id = 0; 715 return 0; 716 } 717 718 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 719 if (r || !xcc_mask) 720 return -EINVAL; 721 722 xcc_id = ffs(xcc_mask) - 1; 723 if (!adev->gmc.is_app_apu) 724 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 725 726 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 727 728 if (r) 729 return r; 730 731 r = -EINVAL; 732 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 733 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 734 *mem_id = i; 735 r = 0; 736 break; 737 } 738 } 739 740 return r; 741 } 742 #endif 743 744 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 745 enum AMDGPU_XCP_IP_BLOCK ip_id, 746 struct amdgpu_xcp_ip *ip) 747 { 748 if (!ip) 749 return -EINVAL; 750 751 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 752 } 753 754 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 755 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 756 .query_partition_mode = &soc_v1_0_query_partition_mode, 757 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 758 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 759 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 760 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 761 #endif 762 }; 763 764 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 765 { 766 int ret; 767 768 if (amdgpu_sriov_vf(adev)) 769 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 770 771 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 772 1, &soc_v1_0_xcp_funcs); 773 if (ret) 774 return ret; 775 776 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 777 /* TODO: Default memory node affinity init */ 778 779 return ret; 780 } 781 782 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 783 { 784 int ret, i; 785 int xcc_inst_per_aid = 4; 786 uint16_t xcc_mask; 787 788 xcc_mask = adev->gfx.xcc_mask; 789 adev->aid_mask = 0; 790 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 791 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 792 adev->aid_mask |= (1 << i); 793 } 794 795 adev->sdma.num_inst_per_xcc = 2; 796 adev->sdma.num_instances = 797 NUM_XCC(adev->gfx.xcc_mask) * adev->sdma.num_inst_per_xcc; 798 adev->sdma.sdma_mask = 799 GENMASK(adev->sdma.num_instances - 1, 0); 800 801 ret = soc_v1_0_xcp_mgr_init(adev); 802 if (ret) 803 return ret; 804 805 amdgpu_ip_map_init(adev); 806 807 return 0; 808 } 809 810 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 811 { 812 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 813 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 814 return true; 815 else 816 return false; 817 } 818 819 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 820 { 821 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 822 823 /* If it is an XCC reg, normalize the reg to keep 824 * lower 16 bits in local xcc */ 825 826 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 827 return normalized_reg; 828 else 829 return reg; 830 } 831