1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 #include "amdgpu_video_codecs.h" 33 34 #include "gc/gc_12_1_0_offset.h" 35 #include "gc/gc_12_1_0_sh_mask.h" 36 #include "mp/mp_15_0_8_offset.h" 37 38 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 39 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 40 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 41 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 42 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 43 (offset & 0xFFFF) 44 45 #define MID1_REG_RANGE_0_LOW 0x40000 46 #define MID1_REG_RANGE_0_HIGH 0x80000 47 #define NORMALIZE_MID_REG_OFFSET(offset) \ 48 (offset & 0x3FFFF) 49 50 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { 51 .codec_count = 0, 52 .codec_array = NULL, 53 }; 54 55 static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { 56 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 57 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 60 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 61 }; 62 63 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { 64 .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), 65 .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, 66 }; 67 68 static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, 69 const struct amdgpu_video_codecs **codecs) 70 { 71 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 72 case IP_VERSION(5, 0, 2): 73 if (encode) 74 *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; 75 else 76 *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; 77 return 0; 78 default: 79 return -EINVAL; 80 } 81 } 82 83 /* Initialized doorbells for amdgpu including multimedia 84 * KFD can use all the rest in 2M doorbell bar */ 85 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 86 { 87 int i; 88 89 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 90 91 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 92 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 93 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 94 95 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 96 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 97 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 98 99 adev->doorbell_index.sdma_doorbell_range = 14; 100 for (i = 0; i < adev->sdma.num_instances; i++) 101 adev->doorbell_index.sdma_engine[i] = 102 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 103 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 104 105 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 106 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 107 108 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 109 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 110 111 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 112 } 113 114 /* Fixed pattern for upper 32bits smn addressing. 115 * bit[47:40]: Socket ID 116 * bit[39:34]: Die ID 117 * bit[32]: local or remote die in same socket 118 * The ext_id is comprised of socket_id and die_id. 119 * ext_id = (socket_id << 6) | (die_id) 120 */ 121 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 122 { 123 u64 ext_offset; 124 int socket_id, die_id; 125 126 /* local die routing for MID0 on local socket */ 127 if (ext_id == 0) 128 return 0; 129 130 die_id = ext_id & 0x3; 131 socket_id = (ext_id >> 6) & 0xff; 132 133 /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 134 if (socket_id == 0) 135 ext_offset = ((u64)die_id << 34) | (1ULL << 32); 136 else if (socket_id != 0 && die_id != 0) 137 ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 138 (3ULL << 32); 139 else 140 ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 141 142 return ext_offset; 143 } 144 145 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 146 { 147 return adev->nbio.funcs->get_memsize(adev); 148 } 149 150 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 151 { 152 return adev->clock.spll.reference_freq; 153 } 154 155 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 156 u32 me, u32 pipe, 157 u32 queue, u32 vmid, 158 int xcc_id) 159 { 160 u32 grbm_gfx_cntl = 0; 161 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 162 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 163 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 164 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 165 166 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 167 } 168 169 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 170 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 171 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 172 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 173 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 174 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 175 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 176 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 177 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 178 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 179 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 180 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 181 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 182 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 183 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 184 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 185 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 186 }; 187 188 189 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 190 bool indexed, u32 se_num, 191 u32 sh_num, u32 reg_offset) 192 { 193 if (indexed) { 194 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 195 } else { 196 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 197 adev->gfx.config.gb_addr_config) 198 return adev->gfx.config.gb_addr_config; 199 return RREG32(reg_offset); 200 } 201 } 202 203 static int soc_v1_0_read_register(struct amdgpu_device *adev, 204 u32 se_num, u32 sh_num, 205 u32 reg_offset, u32 *value) 206 { 207 uint32_t i; 208 struct soc15_allowed_register_entry *en; 209 210 *value = 0; 211 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 212 en = &soc_v1_0_allowed_read_registers[i]; 213 if (!adev->reg_offset[en->hwip][en->inst]) 214 continue; 215 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 216 + en->reg_offset)) 217 continue; 218 219 *value = soc_v1_0_get_register_value(adev, 220 soc_v1_0_allowed_read_registers[i].grbm_indexed, 221 se_num, sh_num, reg_offset); 222 return 0; 223 } 224 return -EINVAL; 225 } 226 227 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 228 { 229 230 return false; 231 } 232 233 static enum amd_reset_method 234 soc_v1_0_asic_reset_method(struct amdgpu_device *adev) 235 { 236 if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || 237 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { 238 if (amdgpu_reset_method != -1) 239 dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); 240 241 return AMD_RESET_METHOD_MODE2; 242 } 243 244 return amdgpu_reset_method; 245 } 246 247 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 248 { 249 switch (soc_v1_0_asic_reset_method(adev)) { 250 case AMD_RESET_METHOD_MODE2: 251 dev_info(adev->dev, "MODE2 reset\n"); 252 return amdgpu_dpm_mode2_reset(adev); 253 default: 254 dev_info(adev->dev, "Invalid reset method Not supported\n"); 255 return -EOPNOTSUPP; 256 } 257 258 return 0; 259 } 260 261 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 262 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 263 .read_register = &soc_v1_0_read_register, 264 .get_config_memsize = &soc_v1_0_get_config_memsize, 265 .get_xclk = &soc_v1_0_get_xclk, 266 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 267 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 268 .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 269 .reset = soc_v1_0_asic_reset, 270 .reset_method = &soc_v1_0_asic_reset_method, 271 .query_video_codecs = &soc_v1_0_query_video_codecs, 272 }; 273 274 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 275 { 276 struct amdgpu_device *adev = ip_block->adev; 277 278 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 279 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 280 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 281 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 282 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 283 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 284 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 285 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 286 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 287 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 288 289 adev->asic_funcs = &soc_v1_0_asic_funcs; 290 291 adev->rev_id = amdgpu_device_get_rev_id(adev); 292 adev->external_rev_id = 0xff; 293 294 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 295 case IP_VERSION(12, 1, 0): 296 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 297 AMD_CG_SUPPORT_GFX_CGLS; 298 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 299 adev->external_rev_id = adev->rev_id + 0x50; 300 break; 301 default: 302 /* FIXME: not supported yet */ 303 return -EINVAL; 304 } 305 306 adev->nbio.funcs->init_registers(adev); 307 308 return 0; 309 } 310 311 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 312 { 313 struct amdgpu_device *adev = ip_block->adev; 314 315 /* Enable selfring doorbell aperture late because doorbell BAR 316 * aperture will change if resize BAR successfully in gmc sw_init. 317 */ 318 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 319 320 return 0; 321 } 322 323 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 324 { 325 return 0; 326 } 327 328 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 329 { 330 struct amdgpu_device *adev = ip_block->adev; 331 332 /* enable the doorbell aperture */ 333 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 334 335 return 0; 336 } 337 338 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 339 { 340 struct amdgpu_device *adev = ip_block->adev; 341 342 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 343 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 344 345 return 0; 346 } 347 348 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 349 { 350 return soc_v1_0_common_hw_fini(ip_block); 351 } 352 353 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 354 { 355 return soc_v1_0_common_hw_init(ip_block); 356 } 357 358 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 359 { 360 return true; 361 } 362 363 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 364 enum amd_clockgating_state state) 365 { 366 return 0; 367 } 368 369 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 370 enum amd_powergating_state state) 371 { 372 return 0; 373 } 374 375 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 376 u64 *flags) 377 { 378 return; 379 } 380 381 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 382 .name = "soc_v1_0_common", 383 .early_init = soc_v1_0_common_early_init, 384 .late_init = soc_v1_0_common_late_init, 385 .sw_init = soc_v1_0_common_sw_init, 386 .hw_init = soc_v1_0_common_hw_init, 387 .hw_fini = soc_v1_0_common_hw_fini, 388 .suspend = soc_v1_0_common_suspend, 389 .resume = soc_v1_0_common_resume, 390 .is_idle = soc_v1_0_common_is_idle, 391 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 392 .set_powergating_state = soc_v1_0_common_set_powergating_state, 393 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 394 }; 395 396 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 397 .type = AMD_IP_BLOCK_TYPE_COMMON, 398 .major = 1, 399 .minor = 0, 400 .rev = 0, 401 .funcs = &soc_v1_0_common_ip_funcs, 402 }; 403 404 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 405 { 406 struct amdgpu_device *adev = xcp_mgr->adev; 407 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 408 409 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 410 if (adev->gfx.funcs && 411 adev->gfx.funcs->get_xccs_per_xcp) 412 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 413 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 414 mode = num_xcc / num_xcc_per_xcp; 415 416 if (num_xcc_per_xcp == 1) 417 return AMDGPU_CPX_PARTITION_MODE; 418 419 switch (mode) { 420 case 1: 421 return AMDGPU_SPX_PARTITION_MODE; 422 case 2: 423 return AMDGPU_DPX_PARTITION_MODE; 424 case 3: 425 return AMDGPU_TPX_PARTITION_MODE; 426 case 4: 427 return AMDGPU_QPX_PARTITION_MODE; 428 default: 429 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 430 } 431 432 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 433 } 434 435 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 436 { 437 enum amdgpu_gfx_partition derv_mode, mode; 438 struct amdgpu_device *adev = xcp_mgr->adev; 439 440 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 441 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 442 443 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 444 return derv_mode; 445 446 if (adev->nbio.funcs && 447 adev->nbio.funcs->get_compute_partition_mode) { 448 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 449 if (mode != derv_mode) 450 dev_warn(adev->dev, 451 "Mismatch in compute partition mode - reported : %d derived : %d", 452 mode, derv_mode); 453 } 454 455 return mode; 456 } 457 458 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 459 { 460 int num_xcc, num_xcc_per_xcp = 0; 461 462 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 463 464 switch (mode) { 465 case AMDGPU_SPX_PARTITION_MODE: 466 num_xcc_per_xcp = num_xcc; 467 break; 468 case AMDGPU_DPX_PARTITION_MODE: 469 num_xcc_per_xcp = num_xcc / 2; 470 break; 471 case AMDGPU_TPX_PARTITION_MODE: 472 num_xcc_per_xcp = num_xcc / 3; 473 break; 474 case AMDGPU_QPX_PARTITION_MODE: 475 num_xcc_per_xcp = num_xcc / 4; 476 break; 477 case AMDGPU_CPX_PARTITION_MODE: 478 num_xcc_per_xcp = 1; 479 break; 480 } 481 482 return num_xcc_per_xcp; 483 } 484 485 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 486 enum AMDGPU_XCP_IP_BLOCK ip_id, 487 struct amdgpu_xcp_ip *ip) 488 { 489 struct amdgpu_device *adev = xcp_mgr->adev; 490 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 491 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 492 493 num_sdma = adev->sdma.num_instances; 494 num_vcn = adev->vcn.num_vcn_inst; 495 num_shared_vcn = 1; 496 497 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 498 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 499 500 switch (xcp_mgr->mode) { 501 case AMDGPU_SPX_PARTITION_MODE: 502 case AMDGPU_DPX_PARTITION_MODE: 503 case AMDGPU_TPX_PARTITION_MODE: 504 case AMDGPU_QPX_PARTITION_MODE: 505 case AMDGPU_CPX_PARTITION_MODE: 506 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 507 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 508 break; 509 default: 510 return -EINVAL; 511 } 512 513 if (num_vcn && num_xcp > num_vcn) 514 num_shared_vcn = num_xcp / num_vcn; 515 516 switch (ip_id) { 517 case AMDGPU_XCP_GFXHUB: 518 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 519 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 520 break; 521 case AMDGPU_XCP_GFX: 522 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 523 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 524 break; 525 case AMDGPU_XCP_SDMA: 526 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 527 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 528 break; 529 case AMDGPU_XCP_VCN: 530 ip->inst_mask = 531 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 532 /* TODO : Assign IP funcs */ 533 break; 534 default: 535 return -EINVAL; 536 } 537 538 ip->ip_id = ip_id; 539 540 return 0; 541 } 542 543 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 544 int mode, 545 struct amdgpu_xcp_cfg *xcp_cfg) 546 { 547 struct amdgpu_device *adev = xcp_mgr->adev; 548 int max_res[AMDGPU_XCP_RES_MAX] = {}; 549 bool res_lt_xcp; 550 int num_xcp, i; 551 u16 nps_modes; 552 553 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 554 return -EINVAL; 555 556 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 557 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 558 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 559 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 560 561 switch (mode) { 562 case AMDGPU_SPX_PARTITION_MODE: 563 num_xcp = 1; 564 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 565 break; 566 case AMDGPU_DPX_PARTITION_MODE: 567 num_xcp = 2; 568 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 569 break; 570 case AMDGPU_TPX_PARTITION_MODE: 571 num_xcp = 3; 572 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 573 BIT(AMDGPU_NPS4_PARTITION_MODE); 574 break; 575 case AMDGPU_QPX_PARTITION_MODE: 576 num_xcp = 4; 577 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 578 BIT(AMDGPU_NPS4_PARTITION_MODE); 579 break; 580 case AMDGPU_CPX_PARTITION_MODE: 581 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 582 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 583 BIT(AMDGPU_NPS4_PARTITION_MODE); 584 break; 585 default: 586 return -EINVAL; 587 } 588 589 xcp_cfg->compatible_nps_modes = 590 (adev->gmc.supported_nps_modes & nps_modes); 591 xcp_cfg->num_res = ARRAY_SIZE(max_res); 592 593 for (i = 0; i < xcp_cfg->num_res; i++) { 594 xcp_cfg->xcp_res[i].id = i; 595 if (!max_res[i]) 596 continue; 597 res_lt_xcp = max_res[i] < num_xcp; 598 xcp_cfg->xcp_res[i].num_inst = 599 res_lt_xcp ? 1 : max_res[i] / num_xcp; 600 xcp_cfg->xcp_res[i].num_inst = 601 i == AMDGPU_XCP_RES_JPEG ? 602 xcp_cfg->xcp_res[i].num_inst * 603 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 604 xcp_cfg->xcp_res[i].num_shared = 605 res_lt_xcp ? num_xcp / max_res[i] : 1; 606 } 607 608 return 0; 609 } 610 611 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 612 { 613 struct amdgpu_device *adev = xcp_mgr->adev; 614 int num_xcc; 615 616 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 617 618 if (adev->gmc.num_mem_partitions == 1) 619 return AMDGPU_SPX_PARTITION_MODE; 620 621 if (adev->gmc.num_mem_partitions == num_xcc) 622 return AMDGPU_CPX_PARTITION_MODE; 623 624 if (adev->gmc.num_mem_partitions == 2) 625 return AMDGPU_DPX_PARTITION_MODE; 626 627 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 628 } 629 630 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 631 enum amdgpu_gfx_partition mode) 632 { 633 struct amdgpu_device *adev = xcp_mgr->adev; 634 int num_xcc, num_xccs_per_xcp; 635 636 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 637 switch (mode) { 638 case AMDGPU_SPX_PARTITION_MODE: 639 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 640 case AMDGPU_DPX_PARTITION_MODE: 641 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 642 case AMDGPU_TPX_PARTITION_MODE: 643 return (adev->gmc.num_mem_partitions == 1 || 644 adev->gmc.num_mem_partitions == 3) && 645 ((num_xcc % 3) == 0); 646 case AMDGPU_QPX_PARTITION_MODE: 647 num_xccs_per_xcp = num_xcc / 4; 648 return (adev->gmc.num_mem_partitions == 1 || 649 adev->gmc.num_mem_partitions == 4) && 650 (num_xccs_per_xcp >= 2); 651 case AMDGPU_CPX_PARTITION_MODE: 652 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 653 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 654 * num_compute_partitions can't be less than num_mem_partitions 655 */ 656 return ((num_xcc > 1) && 657 (num_xcc % adev->gmc.num_mem_partitions) == 0); 658 default: 659 return false; 660 } 661 662 return false; 663 } 664 665 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 666 { 667 int mode; 668 669 xcp_mgr->avail_xcp_modes = 0; 670 671 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 672 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 673 xcp_mgr->avail_xcp_modes |= BIT(mode); 674 } 675 } 676 677 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 678 int mode, int *num_xcps) 679 { 680 int num_xcc_per_xcp, num_xcc, ret; 681 struct amdgpu_device *adev; 682 u32 flags = 0; 683 684 adev = xcp_mgr->adev; 685 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 686 687 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 688 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 689 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 690 dev_err(adev->dev, 691 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 692 adev->gmc.num_mem_partitions); 693 return -EINVAL; 694 } 695 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 696 dev_err(adev->dev, 697 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 698 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 699 return -EINVAL; 700 } 701 702 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 703 flags |= AMDGPU_XCP_OPS_KFD; 704 705 if (flags & AMDGPU_XCP_OPS_KFD) { 706 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 707 if (ret) 708 goto out; 709 } 710 711 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 712 if (ret) 713 goto unlock; 714 715 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 716 if (adev->gfx.imu.funcs && 717 adev->gfx.imu.funcs->switch_compute_partition) 718 adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 719 720 /* Init info about new xcps */ 721 *num_xcps = num_xcc / num_xcc_per_xcp; 722 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 723 724 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 725 if (!ret) 726 __soc_v1_0_update_available_partition_mode(xcp_mgr); 727 unlock: 728 if (flags & AMDGPU_XCP_OPS_KFD) 729 amdgpu_amdkfd_unlock_kfd(adev); 730 out: 731 return ret; 732 } 733 734 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 735 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 736 int xcc_id, uint8_t *mem_id) 737 { 738 /* memory/spatial modes validation check is already done */ 739 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 740 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 741 742 return 0; 743 } 744 745 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 746 struct amdgpu_xcp *xcp, uint8_t *mem_id) 747 { 748 struct amdgpu_numa_info numa_info; 749 struct amdgpu_device *adev; 750 uint32_t xcc_mask; 751 int r, i, xcc_id; 752 753 adev = xcp_mgr->adev; 754 /* TODO: BIOS is not returning the right info now 755 * Check on this later 756 */ 757 /* 758 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 759 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 760 */ 761 if (adev->gmc.num_mem_partitions == 1) { 762 /* Only one range */ 763 *mem_id = 0; 764 return 0; 765 } 766 767 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 768 if (r || !xcc_mask) 769 return -EINVAL; 770 771 xcc_id = ffs(xcc_mask) - 1; 772 if (!adev->gmc.is_app_apu) 773 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 774 775 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 776 777 if (r) 778 return r; 779 780 r = -EINVAL; 781 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 782 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 783 *mem_id = i; 784 r = 0; 785 break; 786 } 787 } 788 789 return r; 790 } 791 #endif 792 793 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 794 enum AMDGPU_XCP_IP_BLOCK ip_id, 795 struct amdgpu_xcp_ip *ip) 796 { 797 if (!ip) 798 return -EINVAL; 799 800 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 801 } 802 803 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 804 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 805 .query_partition_mode = &soc_v1_0_query_partition_mode, 806 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 807 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 808 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 809 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 810 #endif 811 }; 812 813 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 814 { 815 int ret; 816 817 if (amdgpu_sriov_vf(adev)) 818 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 819 820 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 821 1, &soc_v1_0_xcp_funcs); 822 if (ret) 823 return ret; 824 825 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 826 /* TODO: Default memory node affinity init */ 827 828 return ret; 829 } 830 831 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 832 { 833 int ret, i; 834 int xcc_inst_per_aid = 4; 835 uint16_t xcc_mask, sdma_mask = 0; 836 837 xcc_mask = adev->gfx.xcc_mask; 838 adev->aid_mask = 0; 839 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 840 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 841 adev->aid_mask |= (1 << i); 842 } 843 844 adev->sdma.num_inst_per_xcc = 2; 845 for_each_inst(i, adev->gfx.xcc_mask) 846 sdma_mask |= 847 GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << 848 (i * adev->sdma.num_inst_per_xcc); 849 adev->sdma.sdma_mask = sdma_mask; 850 adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); 851 852 ret = soc_v1_0_xcp_mgr_init(adev); 853 if (ret) 854 return ret; 855 856 amdgpu_ip_map_init(adev); 857 858 return 0; 859 } 860 861 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 862 { 863 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 864 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 865 return true; 866 else 867 return false; 868 } 869 870 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 871 { 872 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 873 874 /* If it is an XCC reg, normalize the reg to keep 875 * lower 16 bits in local xcc */ 876 877 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 878 return normalized_reg; 879 else 880 return reg; 881 } 882 883 bool soc_v1_0_mid1_reg_range(uint32_t reg) 884 { 885 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 886 887 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 888 return false; 889 890 if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) 891 return true; 892 else 893 return false; 894 } 895 896 uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) 897 { 898 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 899 900 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 901 return soc_v1_0_normalize_xcc_reg_offset(reg); 902 903 /* check if the reg offset is inside MID1. */ 904 if (soc_v1_0_mid1_reg_range(reg)) 905 return NORMALIZE_MID_REG_OFFSET(reg); 906 907 return reg; 908 } 909 910