1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 #define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ 38 #define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ 39 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 40 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 41 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 42 (offset & 0xFFFF) 43 44 #define MID1_REG_RANGE_0_LOW 0x40000 45 #define MID1_REG_RANGE_0_HIGH 0x80000 46 #define NORMALIZE_MID_REG_OFFSET(offset) \ 47 (offset & 0x3FFFF) 48 49 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { 50 .codec_count = 0, 51 .codec_array = NULL, 52 }; 53 54 static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { 55 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 56 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 57 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), 64 .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, 65 }; 66 67 static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, 68 const struct amdgpu_video_codecs **codecs) 69 { 70 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 71 case IP_VERSION(5, 0, 2): 72 if (encode) 73 *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; 74 else 75 *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; 76 return 0; 77 default: 78 return -EINVAL; 79 } 80 } 81 82 /* Initialized doorbells for amdgpu including multimedia 83 * KFD can use all the rest in 2M doorbell bar */ 84 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 85 { 86 int i; 87 88 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 89 90 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 91 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 92 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 93 94 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 95 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 96 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 97 98 adev->doorbell_index.sdma_doorbell_range = 14; 99 for (i = 0; i < adev->sdma.num_instances; i++) 100 adev->doorbell_index.sdma_engine[i] = 101 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 102 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 103 104 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 105 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 106 107 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 108 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 109 110 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 111 } 112 113 /* Fixed pattern for upper 32bits smn addressing. 114 * bit[47:40]: Socket ID 115 * bit[39:34]: Die ID 116 * bit[32]: local or remote die in same socket 117 * The ext_id is comprised of socket_id and die_id. 118 * ext_id = (socket_id << 6) | (die_id) 119 */ 120 u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) 121 { 122 u64 ext_offset; 123 int socket_id, die_id; 124 125 /* local die routing for MID0 on local socket */ 126 if (ext_id == 0) 127 return 0; 128 129 die_id = ext_id & 0x3; 130 socket_id = (ext_id >> 6) & 0xff; 131 132 /* Initiated from host, accessing to non-MID0 is cross-die traffic */ 133 if (socket_id == 0) 134 ext_offset = ((u64)die_id << 34) | (1ULL << 32); 135 else if (socket_id != 0 && die_id != 0) 136 ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | 137 (3ULL << 32); 138 else 139 ext_offset = ((u64)socket_id << 40) | (1ULL << 33); 140 141 return ext_offset; 142 } 143 144 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 145 { 146 return adev->nbio.funcs->get_memsize(adev); 147 } 148 149 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 150 { 151 return adev->clock.spll.reference_freq; 152 } 153 154 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 155 u32 me, u32 pipe, 156 u32 queue, u32 vmid, 157 int xcc_id) 158 { 159 u32 grbm_gfx_cntl = 0; 160 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 161 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 162 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 163 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 164 165 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 166 } 167 168 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 169 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 170 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 171 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 172 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 173 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 174 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 175 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 176 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 177 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 178 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 179 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 180 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 181 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 182 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 183 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 184 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 185 }; 186 187 188 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 189 bool indexed, u32 se_num, 190 u32 sh_num, u32 reg_offset) 191 { 192 if (indexed) { 193 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 194 } else { 195 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 196 adev->gfx.config.gb_addr_config) 197 return adev->gfx.config.gb_addr_config; 198 return RREG32(reg_offset); 199 } 200 } 201 202 static int soc_v1_0_read_register(struct amdgpu_device *adev, 203 u32 se_num, u32 sh_num, 204 u32 reg_offset, u32 *value) 205 { 206 uint32_t i; 207 struct soc15_allowed_register_entry *en; 208 209 *value = 0; 210 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 211 en = &soc_v1_0_allowed_read_registers[i]; 212 if (!adev->reg_offset[en->hwip][en->inst]) 213 continue; 214 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 215 + en->reg_offset)) 216 continue; 217 218 *value = soc_v1_0_get_register_value(adev, 219 soc_v1_0_allowed_read_registers[i].grbm_indexed, 220 se_num, sh_num, reg_offset); 221 return 0; 222 } 223 return -EINVAL; 224 } 225 226 static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) 227 { 228 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 229 case IP_VERSION(12, 1, 0): 230 default: 231 return true; 232 } 233 } 234 235 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 236 { 237 238 return false; 239 } 240 241 static enum amd_reset_method 242 soc_v1_0_asic_reset_method(struct amdgpu_device *adev) 243 { 244 if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || 245 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { 246 if (amdgpu_reset_method != -1) 247 dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); 248 249 return AMD_RESET_METHOD_MODE2; 250 } 251 252 return amdgpu_reset_method; 253 } 254 255 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 256 { 257 switch (soc_v1_0_asic_reset_method(adev)) { 258 case AMD_RESET_METHOD_MODE2: 259 dev_info(adev->dev, "MODE2 reset\n"); 260 return amdgpu_dpm_mode2_reset(adev); 261 default: 262 dev_info(adev->dev, "Invalid reset method Not supported\n"); 263 return -EOPNOTSUPP; 264 } 265 266 return 0; 267 } 268 269 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 270 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 271 .read_register = &soc_v1_0_read_register, 272 .get_config_memsize = &soc_v1_0_get_config_memsize, 273 .get_xclk = &soc_v1_0_get_xclk, 274 .need_full_reset = &soc_v1_0_need_full_reset, 275 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 276 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 277 .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, 278 .reset = soc_v1_0_asic_reset, 279 .reset_method = &soc_v1_0_asic_reset_method, 280 .query_video_codecs = &soc_v1_0_query_video_codecs, 281 }; 282 283 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 284 { 285 struct amdgpu_device *adev = ip_block->adev; 286 287 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 288 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 289 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 290 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 291 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 292 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 293 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 294 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 295 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 296 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 297 298 adev->asic_funcs = &soc_v1_0_asic_funcs; 299 300 adev->rev_id = amdgpu_device_get_rev_id(adev); 301 adev->external_rev_id = 0xff; 302 303 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 304 case IP_VERSION(12, 1, 0): 305 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 306 AMD_CG_SUPPORT_GFX_CGLS; 307 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 308 adev->external_rev_id = adev->rev_id + 0x50; 309 break; 310 default: 311 /* FIXME: not supported yet */ 312 return -EINVAL; 313 } 314 315 adev->nbio.funcs->init_registers(adev); 316 317 return 0; 318 } 319 320 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 321 { 322 struct amdgpu_device *adev = ip_block->adev; 323 324 /* Enable selfring doorbell aperture late because doorbell BAR 325 * aperture will change if resize BAR successfully in gmc sw_init. 326 */ 327 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 328 329 return 0; 330 } 331 332 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 333 { 334 return 0; 335 } 336 337 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 338 { 339 struct amdgpu_device *adev = ip_block->adev; 340 341 /* enable the doorbell aperture */ 342 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 343 344 return 0; 345 } 346 347 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 348 { 349 struct amdgpu_device *adev = ip_block->adev; 350 351 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 352 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 353 354 return 0; 355 } 356 357 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 358 { 359 return soc_v1_0_common_hw_fini(ip_block); 360 } 361 362 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 363 { 364 return soc_v1_0_common_hw_init(ip_block); 365 } 366 367 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 368 { 369 return true; 370 } 371 372 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 373 enum amd_clockgating_state state) 374 { 375 return 0; 376 } 377 378 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 379 enum amd_powergating_state state) 380 { 381 return 0; 382 } 383 384 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 385 u64 *flags) 386 { 387 return; 388 } 389 390 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 391 .name = "soc_v1_0_common", 392 .early_init = soc_v1_0_common_early_init, 393 .late_init = soc_v1_0_common_late_init, 394 .sw_init = soc_v1_0_common_sw_init, 395 .hw_init = soc_v1_0_common_hw_init, 396 .hw_fini = soc_v1_0_common_hw_fini, 397 .suspend = soc_v1_0_common_suspend, 398 .resume = soc_v1_0_common_resume, 399 .is_idle = soc_v1_0_common_is_idle, 400 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 401 .set_powergating_state = soc_v1_0_common_set_powergating_state, 402 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 403 }; 404 405 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 406 .type = AMD_IP_BLOCK_TYPE_COMMON, 407 .major = 1, 408 .minor = 0, 409 .rev = 0, 410 .funcs = &soc_v1_0_common_ip_funcs, 411 }; 412 413 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 414 { 415 struct amdgpu_device *adev = xcp_mgr->adev; 416 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 417 418 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 419 if (adev->gfx.funcs && 420 adev->gfx.funcs->get_xccs_per_xcp) 421 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 422 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 423 mode = num_xcc / num_xcc_per_xcp; 424 425 if (num_xcc_per_xcp == 1) 426 return AMDGPU_CPX_PARTITION_MODE; 427 428 switch (mode) { 429 case 1: 430 return AMDGPU_SPX_PARTITION_MODE; 431 case 2: 432 return AMDGPU_DPX_PARTITION_MODE; 433 case 3: 434 return AMDGPU_TPX_PARTITION_MODE; 435 case 4: 436 return AMDGPU_QPX_PARTITION_MODE; 437 default: 438 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 439 } 440 441 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 442 } 443 444 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 445 { 446 enum amdgpu_gfx_partition derv_mode, mode; 447 struct amdgpu_device *adev = xcp_mgr->adev; 448 449 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 450 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 451 452 if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) 453 return derv_mode; 454 455 if (adev->nbio.funcs && 456 adev->nbio.funcs->get_compute_partition_mode) { 457 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 458 if (mode != derv_mode) 459 dev_warn(adev->dev, 460 "Mismatch in compute partition mode - reported : %d derived : %d", 461 mode, derv_mode); 462 } 463 464 return mode; 465 } 466 467 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 468 { 469 int num_xcc, num_xcc_per_xcp = 0; 470 471 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 472 473 switch (mode) { 474 case AMDGPU_SPX_PARTITION_MODE: 475 num_xcc_per_xcp = num_xcc; 476 break; 477 case AMDGPU_DPX_PARTITION_MODE: 478 num_xcc_per_xcp = num_xcc / 2; 479 break; 480 case AMDGPU_TPX_PARTITION_MODE: 481 num_xcc_per_xcp = num_xcc / 3; 482 break; 483 case AMDGPU_QPX_PARTITION_MODE: 484 num_xcc_per_xcp = num_xcc / 4; 485 break; 486 case AMDGPU_CPX_PARTITION_MODE: 487 num_xcc_per_xcp = 1; 488 break; 489 } 490 491 return num_xcc_per_xcp; 492 } 493 494 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 495 enum AMDGPU_XCP_IP_BLOCK ip_id, 496 struct amdgpu_xcp_ip *ip) 497 { 498 struct amdgpu_device *adev = xcp_mgr->adev; 499 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 500 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 501 502 num_sdma = adev->sdma.num_instances; 503 num_vcn = adev->vcn.num_vcn_inst; 504 num_shared_vcn = 1; 505 506 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 507 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 508 509 switch (xcp_mgr->mode) { 510 case AMDGPU_SPX_PARTITION_MODE: 511 case AMDGPU_DPX_PARTITION_MODE: 512 case AMDGPU_TPX_PARTITION_MODE: 513 case AMDGPU_QPX_PARTITION_MODE: 514 case AMDGPU_CPX_PARTITION_MODE: 515 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 516 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 if (num_vcn && num_xcp > num_vcn) 523 num_shared_vcn = num_xcp / num_vcn; 524 525 switch (ip_id) { 526 case AMDGPU_XCP_GFXHUB: 527 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 528 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 529 break; 530 case AMDGPU_XCP_GFX: 531 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 532 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 533 break; 534 case AMDGPU_XCP_SDMA: 535 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 536 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 537 break; 538 case AMDGPU_XCP_VCN: 539 ip->inst_mask = 540 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 541 /* TODO : Assign IP funcs */ 542 break; 543 default: 544 return -EINVAL; 545 } 546 547 ip->ip_id = ip_id; 548 549 return 0; 550 } 551 552 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 553 int mode, 554 struct amdgpu_xcp_cfg *xcp_cfg) 555 { 556 struct amdgpu_device *adev = xcp_mgr->adev; 557 int max_res[AMDGPU_XCP_RES_MAX] = {}; 558 bool res_lt_xcp; 559 int num_xcp, i; 560 u16 nps_modes; 561 562 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 563 return -EINVAL; 564 565 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 566 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 567 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 568 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 569 570 switch (mode) { 571 case AMDGPU_SPX_PARTITION_MODE: 572 num_xcp = 1; 573 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 574 break; 575 case AMDGPU_DPX_PARTITION_MODE: 576 num_xcp = 2; 577 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 578 break; 579 case AMDGPU_TPX_PARTITION_MODE: 580 num_xcp = 3; 581 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 582 BIT(AMDGPU_NPS4_PARTITION_MODE); 583 break; 584 case AMDGPU_QPX_PARTITION_MODE: 585 num_xcp = 4; 586 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 587 BIT(AMDGPU_NPS4_PARTITION_MODE); 588 break; 589 case AMDGPU_CPX_PARTITION_MODE: 590 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 591 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 592 BIT(AMDGPU_NPS4_PARTITION_MODE); 593 break; 594 default: 595 return -EINVAL; 596 } 597 598 xcp_cfg->compatible_nps_modes = 599 (adev->gmc.supported_nps_modes & nps_modes); 600 xcp_cfg->num_res = ARRAY_SIZE(max_res); 601 602 for (i = 0; i < xcp_cfg->num_res; i++) { 603 res_lt_xcp = max_res[i] < num_xcp; 604 xcp_cfg->xcp_res[i].id = i; 605 xcp_cfg->xcp_res[i].num_inst = 606 res_lt_xcp ? 1 : max_res[i] / num_xcp; 607 xcp_cfg->xcp_res[i].num_inst = 608 i == AMDGPU_XCP_RES_JPEG ? 609 xcp_cfg->xcp_res[i].num_inst * 610 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 611 xcp_cfg->xcp_res[i].num_shared = 612 res_lt_xcp ? num_xcp / max_res[i] : 1; 613 } 614 615 return 0; 616 } 617 618 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 619 { 620 struct amdgpu_device *adev = xcp_mgr->adev; 621 int num_xcc; 622 623 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 624 625 if (adev->gmc.num_mem_partitions == 1) 626 return AMDGPU_SPX_PARTITION_MODE; 627 628 if (adev->gmc.num_mem_partitions == num_xcc) 629 return AMDGPU_CPX_PARTITION_MODE; 630 631 if (adev->gmc.num_mem_partitions == 2) 632 return AMDGPU_DPX_PARTITION_MODE; 633 634 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 635 } 636 637 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 638 enum amdgpu_gfx_partition mode) 639 { 640 struct amdgpu_device *adev = xcp_mgr->adev; 641 int num_xcc, num_xccs_per_xcp; 642 643 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 644 switch (mode) { 645 case AMDGPU_SPX_PARTITION_MODE: 646 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 647 case AMDGPU_DPX_PARTITION_MODE: 648 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 649 case AMDGPU_TPX_PARTITION_MODE: 650 return (adev->gmc.num_mem_partitions == 1 || 651 adev->gmc.num_mem_partitions == 3) && 652 ((num_xcc % 3) == 0); 653 case AMDGPU_QPX_PARTITION_MODE: 654 num_xccs_per_xcp = num_xcc / 4; 655 return (adev->gmc.num_mem_partitions == 1 || 656 adev->gmc.num_mem_partitions == 4) && 657 (num_xccs_per_xcp >= 2); 658 case AMDGPU_CPX_PARTITION_MODE: 659 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 660 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 661 * num_compute_partitions can't be less than num_mem_partitions 662 */ 663 return ((num_xcc > 1) && 664 (num_xcc % adev->gmc.num_mem_partitions) == 0); 665 default: 666 return false; 667 } 668 669 return false; 670 } 671 672 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 673 { 674 int mode; 675 676 xcp_mgr->avail_xcp_modes = 0; 677 678 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 679 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 680 xcp_mgr->avail_xcp_modes |= BIT(mode); 681 } 682 } 683 684 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 685 int mode, int *num_xcps) 686 { 687 int num_xcc_per_xcp, num_xcc, ret; 688 struct amdgpu_device *adev; 689 u32 flags = 0; 690 691 adev = xcp_mgr->adev; 692 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 693 694 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 695 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 696 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 697 dev_err(adev->dev, 698 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 699 adev->gmc.num_mem_partitions); 700 return -EINVAL; 701 } 702 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 703 dev_err(adev->dev, 704 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 705 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 706 return -EINVAL; 707 } 708 709 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 710 flags |= AMDGPU_XCP_OPS_KFD; 711 712 if (flags & AMDGPU_XCP_OPS_KFD) { 713 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 714 if (ret) 715 goto out; 716 } 717 718 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 719 if (ret) 720 goto unlock; 721 722 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 723 if (adev->gfx.imu.funcs && 724 adev->gfx.imu.funcs->switch_compute_partition) 725 adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); 726 727 /* Init info about new xcps */ 728 *num_xcps = num_xcc / num_xcc_per_xcp; 729 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 730 731 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 732 if (!ret) 733 __soc_v1_0_update_available_partition_mode(xcp_mgr); 734 unlock: 735 if (flags & AMDGPU_XCP_OPS_KFD) 736 amdgpu_amdkfd_unlock_kfd(adev); 737 out: 738 return ret; 739 } 740 741 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 742 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 743 int xcc_id, uint8_t *mem_id) 744 { 745 /* memory/spatial modes validation check is already done */ 746 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 747 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 748 749 return 0; 750 } 751 752 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 753 struct amdgpu_xcp *xcp, uint8_t *mem_id) 754 { 755 struct amdgpu_numa_info numa_info; 756 struct amdgpu_device *adev; 757 uint32_t xcc_mask; 758 int r, i, xcc_id; 759 760 adev = xcp_mgr->adev; 761 /* TODO: BIOS is not returning the right info now 762 * Check on this later 763 */ 764 /* 765 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 766 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 767 */ 768 if (adev->gmc.num_mem_partitions == 1) { 769 /* Only one range */ 770 *mem_id = 0; 771 return 0; 772 } 773 774 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 775 if (r || !xcc_mask) 776 return -EINVAL; 777 778 xcc_id = ffs(xcc_mask) - 1; 779 if (!adev->gmc.is_app_apu) 780 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 781 782 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 783 784 if (r) 785 return r; 786 787 r = -EINVAL; 788 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 789 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 790 *mem_id = i; 791 r = 0; 792 break; 793 } 794 } 795 796 return r; 797 } 798 #endif 799 800 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 801 enum AMDGPU_XCP_IP_BLOCK ip_id, 802 struct amdgpu_xcp_ip *ip) 803 { 804 if (!ip) 805 return -EINVAL; 806 807 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 808 } 809 810 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 811 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 812 .query_partition_mode = &soc_v1_0_query_partition_mode, 813 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 814 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 815 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 816 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 817 #endif 818 }; 819 820 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 821 { 822 int ret; 823 824 if (amdgpu_sriov_vf(adev)) 825 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 826 827 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 828 1, &soc_v1_0_xcp_funcs); 829 if (ret) 830 return ret; 831 832 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 833 /* TODO: Default memory node affinity init */ 834 835 return ret; 836 } 837 838 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 839 { 840 int ret, i; 841 int xcc_inst_per_aid = 4; 842 uint16_t xcc_mask, sdma_mask = 0; 843 844 xcc_mask = adev->gfx.xcc_mask; 845 adev->aid_mask = 0; 846 for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { 847 if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) 848 adev->aid_mask |= (1 << i); 849 } 850 851 adev->sdma.num_inst_per_xcc = 2; 852 for_each_inst(i, adev->gfx.xcc_mask) 853 sdma_mask |= 854 GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << 855 (i * adev->sdma.num_inst_per_xcc); 856 adev->sdma.sdma_mask = sdma_mask; 857 adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); 858 859 ret = soc_v1_0_xcp_mgr_init(adev); 860 if (ret) 861 return ret; 862 863 amdgpu_ip_map_init(adev); 864 865 return 0; 866 } 867 868 bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) 869 { 870 if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || 871 ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) 872 return true; 873 else 874 return false; 875 } 876 877 uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) 878 { 879 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 880 881 /* If it is an XCC reg, normalize the reg to keep 882 * lower 16 bits in local xcc */ 883 884 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 885 return normalized_reg; 886 else 887 return reg; 888 } 889 890 bool soc_v1_0_mid1_reg_range(uint32_t reg) 891 { 892 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 893 894 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 895 return false; 896 897 if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) 898 return true; 899 else 900 return false; 901 } 902 903 uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) 904 { 905 uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); 906 907 if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) 908 return soc_v1_0_normalize_xcc_reg_offset(reg); 909 910 /* check if the reg offset is inside MID1. */ 911 if (soc_v1_0_mid1_reg_range(reg)) 912 return NORMALIZE_MID_REG_OFFSET(reg); 913 914 return reg; 915 } 916 917