1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "soc15.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0.h" 27 #include "amdgpu_ip.h" 28 #include "amdgpu_imu.h" 29 #include "gfxhub_v12_1.h" 30 #include "sdma_v7_1.h" 31 #include "gfx_v12_1.h" 32 33 #include "gc/gc_12_1_0_offset.h" 34 #include "gc/gc_12_1_0_sh_mask.h" 35 #include "mp/mp_15_0_8_offset.h" 36 37 /* Initialized doorbells for amdgpu including multimedia 38 * KFD can use all the rest in 2M doorbell bar */ 39 static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) 40 { 41 int i; 42 43 adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; 44 45 adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; 46 adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; 47 adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; 48 49 adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; 50 adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; 51 adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; 52 53 adev->doorbell_index.sdma_doorbell_range = 20; 54 for (i = 0; i < adev->sdma.num_instances; i++) 55 adev->doorbell_index.sdma_engine[i] = 56 AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + 57 i * (adev->doorbell_index.sdma_doorbell_range >> 1); 58 59 adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; 60 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; 61 62 adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; 63 adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; 64 65 adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; 66 } 67 68 static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) 69 { 70 return adev->nbio.funcs->get_memsize(adev); 71 } 72 73 static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) 74 { 75 return adev->clock.spll.reference_freq; 76 } 77 78 void soc_v1_0_grbm_select(struct amdgpu_device *adev, 79 u32 me, u32 pipe, 80 u32 queue, u32 vmid, 81 int xcc_id) 82 { 83 u32 grbm_gfx_cntl = 0; 84 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 85 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 86 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 87 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 88 89 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); 90 } 91 92 static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { 93 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, 94 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, 95 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, 96 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, 97 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, 98 { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, 99 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, 100 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, 101 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, 102 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, 103 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, 104 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, 105 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, 106 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, 107 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, 108 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, 109 }; 110 111 static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, 112 u32 se_num, 113 u32 sh_num, 114 u32 reg_offset) 115 { 116 uint32_t val; 117 118 mutex_lock(&adev->grbm_idx_mutex); 119 if (se_num != 0xffffffff || sh_num != 0xffffffff) 120 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 121 122 val = RREG32(reg_offset); 123 124 if (se_num != 0xffffffff || sh_num != 0xffffffff) 125 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 126 mutex_unlock(&adev->grbm_idx_mutex); 127 return val; 128 } 129 130 static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, 131 bool indexed, u32 se_num, 132 u32 sh_num, u32 reg_offset) 133 { 134 if (indexed) { 135 return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); 136 } else { 137 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && 138 adev->gfx.config.gb_addr_config) 139 return adev->gfx.config.gb_addr_config; 140 return RREG32(reg_offset); 141 } 142 } 143 144 static int soc_v1_0_read_register(struct amdgpu_device *adev, 145 u32 se_num, u32 sh_num, 146 u32 reg_offset, u32 *value) 147 { 148 uint32_t i; 149 struct soc15_allowed_register_entry *en; 150 151 *value = 0; 152 for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { 153 en = &soc_v1_0_allowed_read_registers[i]; 154 if (!adev->reg_offset[en->hwip][en->inst]) 155 continue; 156 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 157 + en->reg_offset)) 158 continue; 159 160 *value = soc_v1_0_get_register_value(adev, 161 soc_v1_0_allowed_read_registers[i].grbm_indexed, 162 se_num, sh_num, reg_offset); 163 return 0; 164 } 165 return -EINVAL; 166 } 167 168 static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) 169 { 170 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 171 case IP_VERSION(12, 1, 0): 172 default: 173 return true; 174 } 175 } 176 177 static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) 178 { 179 u32 sol_reg; 180 181 if (adev->flags & AMD_IS_APU) 182 return false; 183 184 /* Check sOS sign of life register to confirm sys driver and sOS 185 * are already been loaded. 186 */ 187 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 188 if (sol_reg) 189 return true; 190 191 return false; 192 } 193 194 static int soc_v1_0_asic_reset(struct amdgpu_device *adev) 195 { 196 return 0; 197 } 198 199 static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { 200 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 201 .read_register = &soc_v1_0_read_register, 202 .get_config_memsize = &soc_v1_0_get_config_memsize, 203 .get_xclk = &soc_v1_0_get_xclk, 204 .need_full_reset = &soc_v1_0_need_full_reset, 205 .init_doorbell_index = &soc_v1_0_doorbell_index_init, 206 .need_reset_on_init = &soc_v1_0_need_reset_on_init, 207 .reset = soc_v1_0_asic_reset, 208 }; 209 210 static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) 211 { 212 struct amdgpu_device *adev = ip_block->adev; 213 214 adev->smc_rreg = NULL; 215 adev->smc_wreg = NULL; 216 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 217 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 218 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 219 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 220 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 221 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 222 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 223 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 224 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 225 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 226 adev->uvd_ctx_rreg = NULL; 227 adev->uvd_ctx_wreg = NULL; 228 adev->didt_rreg = NULL; 229 adev->didt_wreg = NULL; 230 231 adev->asic_funcs = &soc_v1_0_asic_funcs; 232 233 adev->rev_id = amdgpu_device_get_rev_id(adev); 234 adev->external_rev_id = 0xff; 235 236 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 237 case IP_VERSION(12, 1, 0): 238 adev->cg_flags = 0; 239 adev->pg_flags = 0; 240 adev->external_rev_id = adev->rev_id + 0x50; 241 break; 242 default: 243 /* FIXME: not supported yet */ 244 return -EINVAL; 245 } 246 247 return 0; 248 } 249 250 static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) 251 { 252 struct amdgpu_device *adev = ip_block->adev; 253 254 /* Enable selfring doorbell aperture late because doorbell BAR 255 * aperture will change if resize BAR successfully in gmc sw_init. 256 */ 257 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 258 259 return 0; 260 } 261 262 static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) 263 { 264 return 0; 265 } 266 267 static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) 268 { 269 struct amdgpu_device *adev = ip_block->adev; 270 271 /* enable the doorbell aperture */ 272 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 273 274 return 0; 275 } 276 277 static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) 278 { 279 struct amdgpu_device *adev = ip_block->adev; 280 281 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 282 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 283 284 return 0; 285 } 286 287 static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) 288 { 289 return soc_v1_0_common_hw_fini(ip_block); 290 } 291 292 static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) 293 { 294 return soc_v1_0_common_hw_init(ip_block); 295 } 296 297 static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) 298 { 299 return true; 300 } 301 302 static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 303 enum amd_clockgating_state state) 304 { 305 return 0; 306 } 307 308 static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 309 enum amd_powergating_state state) 310 { 311 return 0; 312 } 313 314 static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, 315 u64 *flags) 316 { 317 return; 318 } 319 320 static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { 321 .name = "soc_v1_0_common", 322 .early_init = soc_v1_0_common_early_init, 323 .late_init = soc_v1_0_common_late_init, 324 .sw_init = soc_v1_0_common_sw_init, 325 .hw_init = soc_v1_0_common_hw_init, 326 .hw_fini = soc_v1_0_common_hw_fini, 327 .suspend = soc_v1_0_common_suspend, 328 .resume = soc_v1_0_common_resume, 329 .is_idle = soc_v1_0_common_is_idle, 330 .set_clockgating_state = soc_v1_0_common_set_clockgating_state, 331 .set_powergating_state = soc_v1_0_common_set_powergating_state, 332 .get_clockgating_state = soc_v1_0_common_get_clockgating_state, 333 }; 334 335 const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { 336 .type = AMD_IP_BLOCK_TYPE_COMMON, 337 .major = 1, 338 .minor = 0, 339 .rev = 0, 340 .funcs = &soc_v1_0_common_ip_funcs, 341 }; 342 343 static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) 344 { 345 struct amdgpu_device *adev = xcp_mgr->adev; 346 int num_xcc, num_xcc_per_xcp = 0, mode = 0; 347 348 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 349 if (adev->gfx.funcs && 350 adev->gfx.funcs->get_xccs_per_xcp) 351 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 352 if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) 353 mode = num_xcc / num_xcc_per_xcp; 354 355 if (num_xcc_per_xcp == 1) 356 return AMDGPU_CPX_PARTITION_MODE; 357 358 switch (mode) { 359 case 1: 360 return AMDGPU_SPX_PARTITION_MODE; 361 case 2: 362 return AMDGPU_DPX_PARTITION_MODE; 363 case 3: 364 return AMDGPU_TPX_PARTITION_MODE; 365 case 4: 366 return AMDGPU_QPX_PARTITION_MODE; 367 default: 368 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 369 } 370 371 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 372 } 373 374 static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 375 { 376 enum amdgpu_gfx_partition derv_mode, mode; 377 struct amdgpu_device *adev = xcp_mgr->adev; 378 379 mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 380 derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); 381 382 if (amdgpu_sriov_vf(adev)) 383 return derv_mode; 384 385 if (adev->nbio.funcs && 386 adev->nbio.funcs->get_compute_partition_mode) { 387 mode = adev->nbio.funcs->get_compute_partition_mode(adev); 388 if (mode != derv_mode) 389 dev_warn(adev->dev, 390 "Mismatch in compute partition mode - reported : %d derived : %d", 391 mode, derv_mode); 392 } 393 394 return mode; 395 } 396 397 static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) 398 { 399 int num_xcc, num_xcc_per_xcp = 0; 400 401 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 402 403 switch (mode) { 404 case AMDGPU_SPX_PARTITION_MODE: 405 num_xcc_per_xcp = num_xcc; 406 break; 407 case AMDGPU_DPX_PARTITION_MODE: 408 num_xcc_per_xcp = num_xcc / 2; 409 break; 410 case AMDGPU_TPX_PARTITION_MODE: 411 num_xcc_per_xcp = num_xcc / 3; 412 break; 413 case AMDGPU_QPX_PARTITION_MODE: 414 num_xcc_per_xcp = num_xcc / 4; 415 break; 416 case AMDGPU_CPX_PARTITION_MODE: 417 num_xcc_per_xcp = 1; 418 break; 419 } 420 421 return num_xcc_per_xcp; 422 } 423 424 static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 425 enum AMDGPU_XCP_IP_BLOCK ip_id, 426 struct amdgpu_xcp_ip *ip) 427 { 428 struct amdgpu_device *adev = xcp_mgr->adev; 429 int num_sdma, num_vcn, num_shared_vcn, num_xcp; 430 int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; 431 432 num_sdma = adev->sdma.num_instances; 433 num_vcn = adev->vcn.num_vcn_inst; 434 num_shared_vcn = 1; 435 436 num_xcc_xcp = adev->gfx.num_xcc_per_xcp; 437 num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; 438 439 switch (xcp_mgr->mode) { 440 case AMDGPU_SPX_PARTITION_MODE: 441 case AMDGPU_DPX_PARTITION_MODE: 442 case AMDGPU_TPX_PARTITION_MODE: 443 case AMDGPU_QPX_PARTITION_MODE: 444 case AMDGPU_CPX_PARTITION_MODE: 445 num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); 446 num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); 447 break; 448 default: 449 return -EINVAL; 450 } 451 452 if (num_vcn && num_xcp > num_vcn) 453 num_shared_vcn = num_xcp / num_vcn; 454 455 switch (ip_id) { 456 case AMDGPU_XCP_GFXHUB: 457 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 458 ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; 459 break; 460 case AMDGPU_XCP_GFX: 461 ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); 462 ip->ip_funcs = &gfx_v12_1_xcp_funcs; 463 break; 464 case AMDGPU_XCP_SDMA: 465 ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); 466 ip->ip_funcs = &sdma_v7_1_xcp_funcs; 467 break; 468 case AMDGPU_XCP_VCN: 469 ip->inst_mask = 470 XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); 471 /* TODO : Assign IP funcs */ 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 ip->ip_id = ip_id; 478 479 return 0; 480 } 481 482 static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, 483 int mode, 484 struct amdgpu_xcp_cfg *xcp_cfg) 485 { 486 struct amdgpu_device *adev = xcp_mgr->adev; 487 int max_res[AMDGPU_XCP_RES_MAX] = {}; 488 bool res_lt_xcp; 489 int num_xcp, i; 490 u16 nps_modes; 491 492 if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) 493 return -EINVAL; 494 495 max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); 496 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; 497 max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; 498 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; 499 500 switch (mode) { 501 case AMDGPU_SPX_PARTITION_MODE: 502 num_xcp = 1; 503 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 504 break; 505 case AMDGPU_DPX_PARTITION_MODE: 506 num_xcp = 2; 507 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); 508 break; 509 case AMDGPU_TPX_PARTITION_MODE: 510 num_xcp = 3; 511 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 512 BIT(AMDGPU_NPS4_PARTITION_MODE); 513 break; 514 case AMDGPU_QPX_PARTITION_MODE: 515 num_xcp = 4; 516 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 517 BIT(AMDGPU_NPS4_PARTITION_MODE); 518 break; 519 case AMDGPU_CPX_PARTITION_MODE: 520 num_xcp = NUM_XCC(adev->gfx.xcc_mask); 521 nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | 522 BIT(AMDGPU_NPS4_PARTITION_MODE); 523 break; 524 default: 525 return -EINVAL; 526 } 527 528 xcp_cfg->compatible_nps_modes = 529 (adev->gmc.supported_nps_modes & nps_modes); 530 xcp_cfg->num_res = ARRAY_SIZE(max_res); 531 532 for (i = 0; i < xcp_cfg->num_res; i++) { 533 res_lt_xcp = max_res[i] < num_xcp; 534 xcp_cfg->xcp_res[i].id = i; 535 xcp_cfg->xcp_res[i].num_inst = 536 res_lt_xcp ? 1 : max_res[i] / num_xcp; 537 xcp_cfg->xcp_res[i].num_inst = 538 i == AMDGPU_XCP_RES_JPEG ? 539 xcp_cfg->xcp_res[i].num_inst * 540 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; 541 xcp_cfg->xcp_res[i].num_shared = 542 res_lt_xcp ? num_xcp / max_res[i] : 1; 543 } 544 545 return 0; 546 } 547 548 static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) 549 { 550 struct amdgpu_device *adev = xcp_mgr->adev; 551 int num_xcc; 552 553 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); 554 555 if (adev->gmc.num_mem_partitions == 1) 556 return AMDGPU_SPX_PARTITION_MODE; 557 558 if (adev->gmc.num_mem_partitions == num_xcc) 559 return AMDGPU_CPX_PARTITION_MODE; 560 561 if (adev->gmc.num_mem_partitions == 2) 562 return AMDGPU_DPX_PARTITION_MODE; 563 564 return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; 565 } 566 567 static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, 568 enum amdgpu_gfx_partition mode) 569 { 570 struct amdgpu_device *adev = xcp_mgr->adev; 571 int num_xcc, num_xccs_per_xcp; 572 573 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 574 switch (mode) { 575 case AMDGPU_SPX_PARTITION_MODE: 576 return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; 577 case AMDGPU_DPX_PARTITION_MODE: 578 return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; 579 case AMDGPU_TPX_PARTITION_MODE: 580 return (adev->gmc.num_mem_partitions == 1 || 581 adev->gmc.num_mem_partitions == 3) && 582 ((num_xcc % 3) == 0); 583 case AMDGPU_QPX_PARTITION_MODE: 584 num_xccs_per_xcp = num_xcc / 4; 585 return (adev->gmc.num_mem_partitions == 1 || 586 adev->gmc.num_mem_partitions == 4) && 587 (num_xccs_per_xcp >= 2); 588 case AMDGPU_CPX_PARTITION_MODE: 589 /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. 590 * (num_xcc % adev->gmc.num_mem_partitions) == 0 because 591 * num_compute_partitions can't be less than num_mem_partitions 592 */ 593 return ((num_xcc > 1) && 594 (num_xcc % adev->gmc.num_mem_partitions) == 0); 595 default: 596 return false; 597 } 598 599 return false; 600 } 601 602 static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) 603 { 604 int mode; 605 606 xcp_mgr->avail_xcp_modes = 0; 607 608 for_each_inst(mode, xcp_mgr->supp_xcp_modes) { 609 if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) 610 xcp_mgr->avail_xcp_modes |= BIT(mode); 611 } 612 } 613 614 static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, 615 int mode, int *num_xcps) 616 { 617 int num_xcc_per_xcp, num_xcc, ret; 618 struct amdgpu_device *adev; 619 u32 flags = 0; 620 621 adev = xcp_mgr->adev; 622 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 623 624 if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { 625 mode = __soc_v1_0_get_auto_mode(xcp_mgr); 626 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { 627 dev_err(adev->dev, 628 "Invalid config, no compatible compute partition mode found, available memory partitions: %d", 629 adev->gmc.num_mem_partitions); 630 return -EINVAL; 631 } 632 } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { 633 dev_err(adev->dev, 634 "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", 635 amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); 636 return -EINVAL; 637 } 638 639 if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) 640 flags |= AMDGPU_XCP_OPS_KFD; 641 642 if (flags & AMDGPU_XCP_OPS_KFD) { 643 ret = amdgpu_amdkfd_check_and_lock_kfd(adev); 644 if (ret) 645 goto out; 646 } 647 648 ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); 649 if (ret) 650 goto unlock; 651 652 num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); 653 if (adev->gfx.imu.funcs && 654 adev->gfx.imu.funcs->switch_compute_partition) 655 adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp); 656 657 /* Init info about new xcps */ 658 *num_xcps = num_xcc / num_xcc_per_xcp; 659 amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); 660 661 ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); 662 if (!ret) 663 __soc_v1_0_update_available_partition_mode(xcp_mgr); 664 unlock: 665 if (flags & AMDGPU_XCP_OPS_KFD) 666 amdgpu_amdkfd_unlock_kfd(adev); 667 out: 668 return ret; 669 } 670 671 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 672 static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, 673 int xcc_id, uint8_t *mem_id) 674 { 675 /* memory/spatial modes validation check is already done */ 676 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; 677 *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; 678 679 return 0; 680 } 681 682 static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, 683 struct amdgpu_xcp *xcp, uint8_t *mem_id) 684 { 685 struct amdgpu_numa_info numa_info; 686 struct amdgpu_device *adev; 687 uint32_t xcc_mask; 688 int r, i, xcc_id; 689 690 adev = xcp_mgr->adev; 691 /* TODO: BIOS is not returning the right info now 692 * Check on this later 693 */ 694 /* 695 if (adev->gmc.gmc_funcs->query_mem_partition_mode) 696 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); 697 */ 698 if (adev->gmc.num_mem_partitions == 1) { 699 /* Only one range */ 700 *mem_id = 0; 701 return 0; 702 } 703 704 r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); 705 if (r || !xcc_mask) 706 return -EINVAL; 707 708 xcc_id = ffs(xcc_mask) - 1; 709 if (!adev->gmc.is_app_apu) 710 return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); 711 712 r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); 713 714 if (r) 715 return r; 716 717 r = -EINVAL; 718 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { 719 if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { 720 *mem_id = i; 721 r = 0; 722 break; 723 } 724 } 725 726 return r; 727 } 728 #endif 729 730 static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, 731 enum AMDGPU_XCP_IP_BLOCK ip_id, 732 struct amdgpu_xcp_ip *ip) 733 { 734 if (!ip) 735 return -EINVAL; 736 737 return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); 738 } 739 740 struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { 741 .switch_partition_mode = &soc_v1_0_switch_partition_mode, 742 .query_partition_mode = &soc_v1_0_query_partition_mode, 743 .get_ip_details = &soc_v1_0_get_xcp_ip_details, 744 .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, 745 #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 746 .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, 747 #endif 748 }; 749 750 static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) 751 { 752 int ret; 753 754 if (amdgpu_sriov_vf(adev)) 755 soc_v1_0_xcp_funcs.switch_partition_mode = NULL; 756 757 ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, 758 1, &soc_v1_0_xcp_funcs); 759 if (ret) 760 return ret; 761 762 amdgpu_xcp_update_supported_modes(adev->xcp_mgr); 763 /* TODO: Default memory node affinity init */ 764 765 return ret; 766 } 767 768 int soc_v1_0_init_soc_config(struct amdgpu_device *adev) 769 { 770 int ret; 771 772 /*TODO: init soc config */ 773 adev->sdma.num_inst_per_xcc = 2; 774 adev->sdma.num_instances = 775 NUM_XCC(adev->gfx.xcc_mask) * adev->sdma.num_inst_per_xcc; 776 adev->sdma.sdma_mask = 777 GENMASK(adev->sdma.num_instances - 1, 0); 778 779 ret = soc_v1_0_xcp_mgr_init(adev); 780 if (ret) 781 return ret; 782 783 amdgpu_ip_map_init(adev); 784 785 return 0; 786 } 787