1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_ih.h" 30 #include "amdgpu_uvd.h" 31 #include "amdgpu_vce.h" 32 #include "amdgpu_ucode.h" 33 #include "amdgpu_psp.h" 34 #include "amdgpu_smu.h" 35 #include "atom.h" 36 #include "amd_pcie.h" 37 38 #include "gc/gc_12_0_0_offset.h" 39 #include "gc/gc_12_0_0_sh_mask.h" 40 #include "mp/mp_14_0_2_offset.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "soc24.h" 45 #include "mxgpu_nv.h" 46 47 static const struct amd_ip_funcs soc24_common_ip_funcs; 48 49 static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_encode_array_vcn0[] = { 50 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 51 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 53 }; 54 55 static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_encode_vcn0 = { 56 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_encode_array_vcn0), 57 .codec_array = vcn_5_0_0_video_codecs_encode_array_vcn0, 58 }; 59 60 static const struct amdgpu_video_codec_info vcn_5_0_0_video_codecs_decode_array_vcn0[] = { 61 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 62 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 63 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 64 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 65 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 66 }; 67 68 static const struct amdgpu_video_codecs vcn_5_0_0_video_codecs_decode_vcn0 = { 69 .codec_count = ARRAY_SIZE(vcn_5_0_0_video_codecs_decode_array_vcn0), 70 .codec_array = vcn_5_0_0_video_codecs_decode_array_vcn0, 71 }; 72 73 static int soc24_query_video_codecs(struct amdgpu_device *adev, bool encode, 74 const struct amdgpu_video_codecs **codecs) 75 { 76 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 77 return -EINVAL; 78 79 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 80 case IP_VERSION(5, 0, 0): 81 if (encode) 82 *codecs = &vcn_5_0_0_video_codecs_encode_vcn0; 83 else 84 *codecs = &vcn_5_0_0_video_codecs_decode_vcn0; 85 return 0; 86 default: 87 return -EINVAL; 88 } 89 } 90 91 static u32 soc24_get_config_memsize(struct amdgpu_device *adev) 92 { 93 return adev->nbio.funcs->get_memsize(adev); 94 } 95 96 static u32 soc24_get_xclk(struct amdgpu_device *adev) 97 { 98 return adev->clock.spll.reference_freq; 99 } 100 101 void soc24_grbm_select(struct amdgpu_device *adev, 102 u32 me, u32 pipe, u32 queue, u32 vmid) 103 { 104 u32 grbm_gfx_cntl = 0; 105 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 106 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 107 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 108 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 109 110 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 111 } 112 113 static struct soc15_allowed_register_entry soc24_allowed_read_registers[] = { 114 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 115 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 116 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 117 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 118 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 119 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 120 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 121 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 122 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 123 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 124 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 125 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 126 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 127 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 128 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 129 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 130 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 131 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 132 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 133 }; 134 135 static uint32_t soc24_get_register_value(struct amdgpu_device *adev, 136 bool indexed, u32 se_num, 137 u32 sh_num, u32 reg_offset) 138 { 139 if (indexed) { 140 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 141 } else { 142 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && 143 adev->gfx.config.gb_addr_config) 144 return adev->gfx.config.gb_addr_config; 145 return RREG32(reg_offset); 146 } 147 } 148 149 static int soc24_read_register(struct amdgpu_device *adev, u32 se_num, 150 u32 sh_num, u32 reg_offset, u32 *value) 151 { 152 uint32_t i; 153 struct soc15_allowed_register_entry *en; 154 155 *value = 0; 156 for (i = 0; i < ARRAY_SIZE(soc24_allowed_read_registers); i++) { 157 en = &soc24_allowed_read_registers[i]; 158 if (!adev->reg_offset[en->hwip][en->inst]) 159 continue; 160 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 161 + en->reg_offset)) 162 continue; 163 164 *value = soc24_get_register_value(adev, 165 soc24_allowed_read_registers[i].grbm_indexed, 166 se_num, sh_num, reg_offset); 167 return 0; 168 } 169 return -EINVAL; 170 } 171 172 static enum amd_reset_method 173 soc24_asic_reset_method(struct amdgpu_device *adev) 174 { 175 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 176 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 177 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 178 return amdgpu_reset_method; 179 180 if (amdgpu_reset_method != -1) 181 dev_warn(adev->dev, 182 "Specified reset method:%d isn't supported, using AUTO instead.\n", 183 amdgpu_reset_method); 184 185 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 186 case IP_VERSION(14, 0, 2): 187 case IP_VERSION(14, 0, 3): 188 return AMD_RESET_METHOD_MODE1; 189 default: 190 if (amdgpu_dpm_is_baco_supported(adev)) 191 return AMD_RESET_METHOD_BACO; 192 else 193 return AMD_RESET_METHOD_MODE1; 194 } 195 } 196 197 static int soc24_asic_reset(struct amdgpu_device *adev) 198 { 199 int ret = 0; 200 201 switch (soc24_asic_reset_method(adev)) { 202 case AMD_RESET_METHOD_PCI: 203 dev_info(adev->dev, "PCI reset\n"); 204 ret = amdgpu_device_pci_reset(adev); 205 break; 206 case AMD_RESET_METHOD_BACO: 207 dev_info(adev->dev, "BACO reset\n"); 208 ret = amdgpu_dpm_baco_reset(adev); 209 break; 210 case AMD_RESET_METHOD_MODE2: 211 dev_info(adev->dev, "MODE2 reset\n"); 212 ret = amdgpu_dpm_mode2_reset(adev); 213 break; 214 default: 215 dev_info(adev->dev, "MODE1 reset\n"); 216 ret = amdgpu_device_mode1_reset(adev); 217 break; 218 } 219 220 return ret; 221 } 222 223 static void soc24_program_aspm(struct amdgpu_device *adev) 224 { 225 if (!amdgpu_device_should_use_aspm(adev)) 226 return; 227 228 if (!(adev->flags & AMD_IS_APU) && 229 (adev->nbio.funcs->program_aspm)) 230 adev->nbio.funcs->program_aspm(adev); 231 } 232 233 const struct amdgpu_ip_block_version soc24_common_ip_block = { 234 .type = AMD_IP_BLOCK_TYPE_COMMON, 235 .major = 1, 236 .minor = 0, 237 .rev = 0, 238 .funcs = &soc24_common_ip_funcs, 239 }; 240 241 static bool soc24_need_reset_on_init(struct amdgpu_device *adev) 242 { 243 u32 sol_reg; 244 245 if (adev->flags & AMD_IS_APU) 246 return false; 247 248 /* Check sOS sign of life register to confirm sys driver and sOS 249 * are already been loaded. 250 */ 251 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 252 if (sol_reg) 253 return true; 254 255 return false; 256 } 257 258 static uint64_t soc24_get_pcie_replay_count(struct amdgpu_device *adev) 259 { 260 /* TODO 261 * dummy implement for pcie_replay_count sysfs interface 262 * */ 263 return 0; 264 } 265 266 static void soc24_init_doorbell_index(struct amdgpu_device *adev) 267 { 268 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 269 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 270 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 271 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 272 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 273 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 274 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 275 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 276 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 277 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 278 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 279 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 280 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 281 adev->doorbell_index.gfx_userqueue_start = 282 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 283 adev->doorbell_index.gfx_userqueue_end = 284 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 285 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 286 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 287 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 288 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 289 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 290 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 291 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 292 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 293 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 294 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 295 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 296 297 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 298 adev->doorbell_index.sdma_doorbell_range = 20; 299 } 300 301 static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev, 302 bool enter) 303 { 304 if (enter) 305 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 306 else 307 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 308 309 if (adev->gfx.funcs->update_perfmon_mgcg) 310 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 311 312 return 0; 313 } 314 315 static const struct amdgpu_asic_funcs soc24_asic_funcs = { 316 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 317 .read_register = &soc24_read_register, 318 .reset = &soc24_asic_reset, 319 .reset_method = &soc24_asic_reset_method, 320 .get_xclk = &soc24_get_xclk, 321 .get_config_memsize = &soc24_get_config_memsize, 322 .init_doorbell_index = &soc24_init_doorbell_index, 323 .need_reset_on_init = &soc24_need_reset_on_init, 324 .get_pcie_replay_count = &soc24_get_pcie_replay_count, 325 .supports_baco = &amdgpu_dpm_is_baco_supported, 326 .query_video_codecs = &soc24_query_video_codecs, 327 .update_umd_stable_pstate = &soc24_update_umd_stable_pstate, 328 }; 329 330 static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) 331 { 332 struct amdgpu_device *adev = ip_block->adev; 333 334 adev->nbio.funcs->set_reg_remap(adev); 335 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 336 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 337 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 338 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 339 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 340 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 341 342 adev->asic_funcs = &soc24_asic_funcs; 343 344 adev->rev_id = amdgpu_device_get_rev_id(adev); 345 adev->external_rev_id = 0xff; 346 347 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 348 case IP_VERSION(12, 0, 0): 349 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 350 AMD_CG_SUPPORT_GFX_CGLS | 351 AMD_CG_SUPPORT_GFX_MGCG | 352 AMD_CG_SUPPORT_GFX_3D_CGCG | 353 AMD_CG_SUPPORT_GFX_3D_CGLS | 354 AMD_CG_SUPPORT_REPEATER_FGCG | 355 AMD_CG_SUPPORT_GFX_FGCG | 356 AMD_CG_SUPPORT_GFX_PERF_CLK | 357 AMD_CG_SUPPORT_ATHUB_MGCG | 358 AMD_CG_SUPPORT_ATHUB_LS | 359 AMD_CG_SUPPORT_MC_MGCG | 360 AMD_CG_SUPPORT_HDP_SD | 361 AMD_CG_SUPPORT_MC_LS; 362 adev->pg_flags = AMD_PG_SUPPORT_VCN | 363 AMD_PG_SUPPORT_JPEG | 364 AMD_PG_SUPPORT_VCN_DPG; 365 adev->external_rev_id = adev->rev_id + 0x40; 366 break; 367 case IP_VERSION(12, 0, 1): 368 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 369 AMD_CG_SUPPORT_GFX_CGLS | 370 AMD_CG_SUPPORT_GFX_MGCG | 371 AMD_CG_SUPPORT_GFX_3D_CGCG | 372 AMD_CG_SUPPORT_GFX_3D_CGLS | 373 AMD_CG_SUPPORT_REPEATER_FGCG | 374 AMD_CG_SUPPORT_GFX_FGCG | 375 AMD_CG_SUPPORT_GFX_PERF_CLK | 376 AMD_CG_SUPPORT_ATHUB_MGCG | 377 AMD_CG_SUPPORT_ATHUB_LS | 378 AMD_CG_SUPPORT_MC_MGCG | 379 AMD_CG_SUPPORT_HDP_SD | 380 AMD_CG_SUPPORT_MC_LS; 381 382 adev->pg_flags = AMD_PG_SUPPORT_VCN | 383 AMD_PG_SUPPORT_JPEG | 384 AMD_PG_SUPPORT_JPEG_DPG | 385 AMD_PG_SUPPORT_VCN_DPG; 386 adev->external_rev_id = adev->rev_id + 0x50; 387 break; 388 default: 389 /* FIXME: not supported yet */ 390 return -EINVAL; 391 } 392 393 if (amdgpu_sriov_vf(adev)) { 394 amdgpu_virt_init_setting(adev); 395 xgpu_nv_mailbox_set_irq_funcs(adev); 396 } 397 398 return 0; 399 } 400 401 static int soc24_common_late_init(struct amdgpu_ip_block *ip_block) 402 { 403 struct amdgpu_device *adev = ip_block->adev; 404 405 if (amdgpu_sriov_vf(adev)) { 406 xgpu_nv_mailbox_get_irq(adev); 407 } else { 408 if (adev->nbio.ras && 409 adev->nbio.ras_err_event_athub_irq.funcs) 410 /* don't need to fail gpu late init 411 * if enabling athub_err_event interrupt failed 412 * nbif v6_3_1 only support fatal error hanlding 413 * just enable the interrupt directly 414 */ 415 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 416 } 417 418 /* Enable selfring doorbell aperture late because doorbell BAR 419 * aperture will change if resize BAR successfully in gmc sw_init. 420 */ 421 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 422 423 return 0; 424 } 425 426 static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block) 427 { 428 struct amdgpu_device *adev = ip_block->adev; 429 430 if (amdgpu_sriov_vf(adev)) 431 xgpu_nv_mailbox_add_irq_id(adev); 432 433 return 0; 434 } 435 436 static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block) 437 { 438 struct amdgpu_device *adev = ip_block->adev; 439 440 /* enable aspm */ 441 soc24_program_aspm(adev); 442 /* setup nbio registers */ 443 adev->nbio.funcs->init_registers(adev); 444 /* remap HDP registers to a hole in mmio space, 445 * for the purpose of expose those registers 446 * to process space 447 */ 448 if (adev->nbio.funcs->remap_hdp_registers) 449 adev->nbio.funcs->remap_hdp_registers(adev); 450 451 if (adev->df.funcs && adev->df.funcs->hw_init) 452 adev->df.funcs->hw_init(adev); 453 454 /* enable the doorbell aperture */ 455 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 456 457 return 0; 458 } 459 460 static int soc24_common_hw_fini(struct amdgpu_ip_block *ip_block) 461 { 462 struct amdgpu_device *adev = ip_block->adev; 463 464 /* Disable the doorbell aperture and selfring doorbell aperture 465 * separately in hw_fini because soc21_enable_doorbell_aperture 466 * has been removed and there is no need to delay disabling 467 * selfring doorbell. 468 */ 469 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 470 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 471 472 if (amdgpu_sriov_vf(adev)) { 473 xgpu_nv_mailbox_put_irq(adev); 474 } else { 475 if (adev->nbio.ras && 476 adev->nbio.ras_err_event_athub_irq.funcs) 477 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 478 } 479 480 return 0; 481 } 482 483 static int soc24_common_suspend(struct amdgpu_ip_block *ip_block) 484 { 485 return soc24_common_hw_fini(ip_block); 486 } 487 488 static bool soc24_need_reset_on_resume(struct amdgpu_device *adev) 489 { 490 u32 sol_reg1, sol_reg2; 491 492 /* Will reset for the following suspend abort cases. 493 * 1) Only reset dGPU side. 494 * 2) S3 suspend got aborted and TOS is active. 495 * As for dGPU suspend abort cases the SOL value 496 * will be kept as zero at this resume point. 497 */ 498 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 499 sol_reg1 = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 500 msleep(100); 501 sol_reg2 = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 502 503 return (sol_reg1 != sol_reg2); 504 } 505 506 return false; 507 } 508 509 static int soc24_common_resume(struct amdgpu_ip_block *ip_block) 510 { 511 struct amdgpu_device *adev = ip_block->adev; 512 513 if (soc24_need_reset_on_resume(adev)) { 514 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 515 soc24_asic_reset(adev); 516 } 517 518 return soc24_common_hw_init(ip_block); 519 } 520 521 static bool soc24_common_is_idle(struct amdgpu_ip_block *ip_block) 522 { 523 return true; 524 } 525 526 static int soc24_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 527 enum amd_clockgating_state state) 528 { 529 struct amdgpu_device *adev = ip_block->adev; 530 531 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 532 case IP_VERSION(6, 3, 1): 533 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 534 state == AMD_CG_STATE_GATE); 535 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 536 state == AMD_CG_STATE_GATE); 537 adev->hdp.funcs->update_clock_gating(adev, 538 state == AMD_CG_STATE_GATE); 539 break; 540 default: 541 break; 542 } 543 return 0; 544 } 545 546 static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 547 enum amd_powergating_state state) 548 { 549 struct amdgpu_device *adev = ip_block->adev; 550 551 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 552 case IP_VERSION(7, 0, 0): 553 case IP_VERSION(7, 0, 1): 554 adev->lsdma.funcs->update_memory_power_gating(adev, 555 state == AMD_PG_STATE_GATE); 556 break; 557 default: 558 break; 559 } 560 561 return 0; 562 } 563 564 static void soc24_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 565 { 566 struct amdgpu_device *adev = ip_block->adev; 567 568 adev->nbio.funcs->get_clockgating_state(adev, flags); 569 570 adev->hdp.funcs->get_clock_gating_state(adev, flags); 571 572 return; 573 } 574 575 static const struct amd_ip_funcs soc24_common_ip_funcs = { 576 .name = "soc24_common", 577 .early_init = soc24_common_early_init, 578 .late_init = soc24_common_late_init, 579 .sw_init = soc24_common_sw_init, 580 .hw_init = soc24_common_hw_init, 581 .hw_fini = soc24_common_hw_fini, 582 .suspend = soc24_common_suspend, 583 .resume = soc24_common_resume, 584 .is_idle = soc24_common_is_idle, 585 .set_clockgating_state = soc24_common_set_clockgating_state, 586 .set_powergating_state = soc24_common_set_powergating_state, 587 .get_clockgating_state = soc24_common_get_clockgating_state, 588 }; 589