1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 128 }; 129 130 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 136 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 137 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 138 }; 139 140 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 141 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 142 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 143 }; 144 145 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 146 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 147 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 148 }; 149 150 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 151 const struct amdgpu_video_codecs **codecs) 152 { 153 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 154 return -EINVAL; 155 156 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 157 case IP_VERSION(4, 0, 0): 158 case IP_VERSION(4, 0, 2): 159 case IP_VERSION(4, 0, 4): 160 case IP_VERSION(4, 0, 5): 161 if (amdgpu_sriov_vf(adev)) { 162 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 163 !amdgpu_sriov_is_av1_support(adev)) { 164 if (encode) 165 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 166 else 167 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 168 } else { 169 if (encode) 170 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 171 else 172 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 173 } 174 } else { 175 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 176 if (encode) 177 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 178 else 179 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 180 } else { 181 if (encode) 182 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 183 else 184 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 185 } 186 } 187 return 0; 188 case IP_VERSION(4, 0, 6): 189 if (encode) 190 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 191 else 192 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 193 return 0; 194 default: 195 return -EINVAL; 196 } 197 } 198 199 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 200 { 201 unsigned long flags, address, data; 202 u32 r; 203 204 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 205 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 206 207 spin_lock_irqsave(&adev->didt_idx_lock, flags); 208 WREG32(address, (reg)); 209 r = RREG32(data); 210 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 211 return r; 212 } 213 214 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 215 { 216 unsigned long flags, address, data; 217 218 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 219 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 220 221 spin_lock_irqsave(&adev->didt_idx_lock, flags); 222 WREG32(address, (reg)); 223 WREG32(data, (v)); 224 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 225 } 226 227 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 228 { 229 return adev->nbio.funcs->get_memsize(adev); 230 } 231 232 static u32 soc21_get_xclk(struct amdgpu_device *adev) 233 { 234 return adev->clock.spll.reference_freq; 235 } 236 237 238 void soc21_grbm_select(struct amdgpu_device *adev, 239 u32 me, u32 pipe, u32 queue, u32 vmid) 240 { 241 u32 grbm_gfx_cntl = 0; 242 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 243 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 244 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 245 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 246 247 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 248 } 249 250 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 251 { 252 /* todo */ 253 return false; 254 } 255 256 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 257 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 258 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 259 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 260 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 261 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 262 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 263 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 264 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 265 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 266 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 267 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 268 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 269 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 270 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 271 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 272 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 273 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 274 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 275 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 276 }; 277 278 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 279 u32 sh_num, u32 reg_offset) 280 { 281 uint32_t val; 282 283 mutex_lock(&adev->grbm_idx_mutex); 284 if (se_num != 0xffffffff || sh_num != 0xffffffff) 285 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 286 287 val = RREG32(reg_offset); 288 289 if (se_num != 0xffffffff || sh_num != 0xffffffff) 290 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 291 mutex_unlock(&adev->grbm_idx_mutex); 292 return val; 293 } 294 295 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 296 bool indexed, u32 se_num, 297 u32 sh_num, u32 reg_offset) 298 { 299 if (indexed) { 300 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 301 } else { 302 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 303 return adev->gfx.config.gb_addr_config; 304 return RREG32(reg_offset); 305 } 306 } 307 308 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 309 u32 sh_num, u32 reg_offset, u32 *value) 310 { 311 uint32_t i; 312 struct soc15_allowed_register_entry *en; 313 314 *value = 0; 315 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 316 en = &soc21_allowed_read_registers[i]; 317 if (!adev->reg_offset[en->hwip][en->inst]) 318 continue; 319 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 320 + en->reg_offset)) 321 continue; 322 323 *value = soc21_get_register_value(adev, 324 soc21_allowed_read_registers[i].grbm_indexed, 325 se_num, sh_num, reg_offset); 326 return 0; 327 } 328 return -EINVAL; 329 } 330 331 #if 0 332 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 333 { 334 u32 i; 335 int ret = 0; 336 337 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 338 339 /* disable BM */ 340 pci_clear_master(adev->pdev); 341 342 amdgpu_device_cache_pci_state(adev->pdev); 343 344 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 345 dev_info(adev->dev, "GPU smu mode1 reset\n"); 346 ret = amdgpu_dpm_mode1_reset(adev); 347 } else { 348 dev_info(adev->dev, "GPU psp mode1 reset\n"); 349 ret = psp_gpu_reset(adev); 350 } 351 352 if (ret) 353 dev_err(adev->dev, "GPU mode1 reset failed\n"); 354 amdgpu_device_load_pci_state(adev->pdev); 355 356 /* wait for asic to come out of reset */ 357 for (i = 0; i < adev->usec_timeout; i++) { 358 u32 memsize = adev->nbio.funcs->get_memsize(adev); 359 360 if (memsize != 0xffffffff) 361 break; 362 udelay(1); 363 } 364 365 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 366 367 return ret; 368 } 369 #endif 370 371 static enum amd_reset_method 372 soc21_asic_reset_method(struct amdgpu_device *adev) 373 { 374 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 375 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 376 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 377 return amdgpu_reset_method; 378 379 if (amdgpu_reset_method != -1) 380 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 381 amdgpu_reset_method); 382 383 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 384 case IP_VERSION(13, 0, 0): 385 case IP_VERSION(13, 0, 7): 386 case IP_VERSION(13, 0, 10): 387 return AMD_RESET_METHOD_MODE1; 388 case IP_VERSION(13, 0, 4): 389 case IP_VERSION(13, 0, 11): 390 case IP_VERSION(14, 0, 0): 391 case IP_VERSION(14, 0, 1): 392 case IP_VERSION(14, 0, 4): 393 return AMD_RESET_METHOD_MODE2; 394 default: 395 if (amdgpu_dpm_is_baco_supported(adev)) 396 return AMD_RESET_METHOD_BACO; 397 else 398 return AMD_RESET_METHOD_MODE1; 399 } 400 } 401 402 static int soc21_asic_reset(struct amdgpu_device *adev) 403 { 404 int ret = 0; 405 406 switch (soc21_asic_reset_method(adev)) { 407 case AMD_RESET_METHOD_PCI: 408 dev_info(adev->dev, "PCI reset\n"); 409 ret = amdgpu_device_pci_reset(adev); 410 break; 411 case AMD_RESET_METHOD_BACO: 412 dev_info(adev->dev, "BACO reset\n"); 413 ret = amdgpu_dpm_baco_reset(adev); 414 break; 415 case AMD_RESET_METHOD_MODE2: 416 dev_info(adev->dev, "MODE2 reset\n"); 417 ret = amdgpu_dpm_mode2_reset(adev); 418 break; 419 default: 420 dev_info(adev->dev, "MODE1 reset\n"); 421 ret = amdgpu_device_mode1_reset(adev); 422 break; 423 } 424 425 return ret; 426 } 427 428 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 429 { 430 /* todo */ 431 return 0; 432 } 433 434 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 435 { 436 /* todo */ 437 return 0; 438 } 439 440 static void soc21_program_aspm(struct amdgpu_device *adev) 441 { 442 if (!amdgpu_device_should_use_aspm(adev)) 443 return; 444 445 if (adev->nbio.funcs->program_aspm) 446 adev->nbio.funcs->program_aspm(adev); 447 } 448 449 const struct amdgpu_ip_block_version soc21_common_ip_block = { 450 .type = AMD_IP_BLOCK_TYPE_COMMON, 451 .major = 1, 452 .minor = 0, 453 .rev = 0, 454 .funcs = &soc21_common_ip_funcs, 455 }; 456 457 static bool soc21_need_full_reset(struct amdgpu_device *adev) 458 { 459 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 460 case IP_VERSION(11, 0, 0): 461 case IP_VERSION(11, 0, 2): 462 case IP_VERSION(11, 0, 3): 463 default: 464 return true; 465 } 466 } 467 468 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 469 { 470 u32 sol_reg; 471 472 if (adev->flags & AMD_IS_APU) 473 return false; 474 475 /* Check sOS sign of life register to confirm sys driver and sOS 476 * are already been loaded. 477 */ 478 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 479 if (sol_reg) 480 return true; 481 482 return false; 483 } 484 485 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 486 { 487 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 488 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 489 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 490 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 491 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 492 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 493 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 494 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 495 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 496 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 497 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 498 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 499 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 500 adev->doorbell_index.gfx_userqueue_start = 501 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 502 adev->doorbell_index.gfx_userqueue_end = 503 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 504 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 505 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 506 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 507 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 508 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 509 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 510 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 511 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 512 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 513 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 514 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 515 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 516 517 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 518 adev->doorbell_index.sdma_doorbell_range = 20; 519 } 520 521 static void soc21_pre_asic_init(struct amdgpu_device *adev) 522 { 523 } 524 525 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 526 bool enter) 527 { 528 if (enter) 529 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 530 else 531 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 532 533 if (adev->gfx.funcs->update_perfmon_mgcg) 534 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 535 536 return 0; 537 } 538 539 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 540 .read_disabled_bios = &soc21_read_disabled_bios, 541 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 542 .read_register = &soc21_read_register, 543 .reset = &soc21_asic_reset, 544 .reset_method = &soc21_asic_reset_method, 545 .get_xclk = &soc21_get_xclk, 546 .set_uvd_clocks = &soc21_set_uvd_clocks, 547 .set_vce_clocks = &soc21_set_vce_clocks, 548 .get_config_memsize = &soc21_get_config_memsize, 549 .init_doorbell_index = &soc21_init_doorbell_index, 550 .need_full_reset = &soc21_need_full_reset, 551 .need_reset_on_init = &soc21_need_reset_on_init, 552 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 553 .supports_baco = &amdgpu_dpm_is_baco_supported, 554 .pre_asic_init = &soc21_pre_asic_init, 555 .query_video_codecs = &soc21_query_video_codecs, 556 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 557 }; 558 559 static int soc21_common_early_init(void *handle) 560 { 561 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 562 563 adev->nbio.funcs->set_reg_remap(adev); 564 adev->smc_rreg = NULL; 565 adev->smc_wreg = NULL; 566 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 567 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 568 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 569 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 570 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 571 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 572 573 /* TODO: will add them during VCN v2 implementation */ 574 adev->uvd_ctx_rreg = NULL; 575 adev->uvd_ctx_wreg = NULL; 576 577 adev->didt_rreg = &soc21_didt_rreg; 578 adev->didt_wreg = &soc21_didt_wreg; 579 580 adev->asic_funcs = &soc21_asic_funcs; 581 582 adev->rev_id = amdgpu_device_get_rev_id(adev); 583 adev->external_rev_id = 0xff; 584 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 585 case IP_VERSION(11, 0, 0): 586 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 587 AMD_CG_SUPPORT_GFX_CGLS | 588 #if 0 589 AMD_CG_SUPPORT_GFX_3D_CGCG | 590 AMD_CG_SUPPORT_GFX_3D_CGLS | 591 #endif 592 AMD_CG_SUPPORT_GFX_MGCG | 593 AMD_CG_SUPPORT_REPEATER_FGCG | 594 AMD_CG_SUPPORT_GFX_FGCG | 595 AMD_CG_SUPPORT_GFX_PERF_CLK | 596 AMD_CG_SUPPORT_VCN_MGCG | 597 AMD_CG_SUPPORT_JPEG_MGCG | 598 AMD_CG_SUPPORT_ATHUB_MGCG | 599 AMD_CG_SUPPORT_ATHUB_LS | 600 AMD_CG_SUPPORT_MC_MGCG | 601 AMD_CG_SUPPORT_MC_LS | 602 AMD_CG_SUPPORT_IH_CG | 603 AMD_CG_SUPPORT_HDP_SD; 604 adev->pg_flags = AMD_PG_SUPPORT_VCN | 605 AMD_PG_SUPPORT_VCN_DPG | 606 AMD_PG_SUPPORT_JPEG | 607 AMD_PG_SUPPORT_ATHUB | 608 AMD_PG_SUPPORT_MMHUB; 609 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 610 break; 611 case IP_VERSION(11, 0, 2): 612 adev->cg_flags = 613 AMD_CG_SUPPORT_GFX_CGCG | 614 AMD_CG_SUPPORT_GFX_CGLS | 615 AMD_CG_SUPPORT_REPEATER_FGCG | 616 AMD_CG_SUPPORT_VCN_MGCG | 617 AMD_CG_SUPPORT_JPEG_MGCG | 618 AMD_CG_SUPPORT_ATHUB_MGCG | 619 AMD_CG_SUPPORT_ATHUB_LS | 620 AMD_CG_SUPPORT_IH_CG | 621 AMD_CG_SUPPORT_HDP_SD; 622 adev->pg_flags = 623 AMD_PG_SUPPORT_VCN | 624 AMD_PG_SUPPORT_VCN_DPG | 625 AMD_PG_SUPPORT_JPEG | 626 AMD_PG_SUPPORT_ATHUB | 627 AMD_PG_SUPPORT_MMHUB; 628 adev->external_rev_id = adev->rev_id + 0x10; 629 break; 630 case IP_VERSION(11, 0, 1): 631 adev->cg_flags = 632 AMD_CG_SUPPORT_GFX_CGCG | 633 AMD_CG_SUPPORT_GFX_CGLS | 634 AMD_CG_SUPPORT_GFX_MGCG | 635 AMD_CG_SUPPORT_GFX_FGCG | 636 AMD_CG_SUPPORT_REPEATER_FGCG | 637 AMD_CG_SUPPORT_GFX_PERF_CLK | 638 AMD_CG_SUPPORT_MC_MGCG | 639 AMD_CG_SUPPORT_MC_LS | 640 AMD_CG_SUPPORT_HDP_MGCG | 641 AMD_CG_SUPPORT_HDP_LS | 642 AMD_CG_SUPPORT_ATHUB_MGCG | 643 AMD_CG_SUPPORT_ATHUB_LS | 644 AMD_CG_SUPPORT_IH_CG | 645 AMD_CG_SUPPORT_BIF_MGCG | 646 AMD_CG_SUPPORT_BIF_LS | 647 AMD_CG_SUPPORT_VCN_MGCG | 648 AMD_CG_SUPPORT_JPEG_MGCG; 649 adev->pg_flags = 650 AMD_PG_SUPPORT_GFX_PG | 651 AMD_PG_SUPPORT_VCN | 652 AMD_PG_SUPPORT_VCN_DPG | 653 AMD_PG_SUPPORT_JPEG; 654 adev->external_rev_id = adev->rev_id + 0x1; 655 break; 656 case IP_VERSION(11, 0, 3): 657 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 658 AMD_CG_SUPPORT_JPEG_MGCG | 659 AMD_CG_SUPPORT_GFX_CGCG | 660 AMD_CG_SUPPORT_GFX_CGLS | 661 AMD_CG_SUPPORT_REPEATER_FGCG | 662 AMD_CG_SUPPORT_GFX_MGCG | 663 AMD_CG_SUPPORT_HDP_SD | 664 AMD_CG_SUPPORT_ATHUB_MGCG | 665 AMD_CG_SUPPORT_ATHUB_LS; 666 adev->pg_flags = AMD_PG_SUPPORT_VCN | 667 AMD_PG_SUPPORT_VCN_DPG | 668 AMD_PG_SUPPORT_JPEG; 669 adev->external_rev_id = adev->rev_id + 0x20; 670 break; 671 case IP_VERSION(11, 0, 4): 672 adev->cg_flags = 673 AMD_CG_SUPPORT_GFX_CGCG | 674 AMD_CG_SUPPORT_GFX_CGLS | 675 AMD_CG_SUPPORT_GFX_MGCG | 676 AMD_CG_SUPPORT_GFX_FGCG | 677 AMD_CG_SUPPORT_REPEATER_FGCG | 678 AMD_CG_SUPPORT_GFX_PERF_CLK | 679 AMD_CG_SUPPORT_MC_MGCG | 680 AMD_CG_SUPPORT_MC_LS | 681 AMD_CG_SUPPORT_HDP_MGCG | 682 AMD_CG_SUPPORT_HDP_LS | 683 AMD_CG_SUPPORT_ATHUB_MGCG | 684 AMD_CG_SUPPORT_ATHUB_LS | 685 AMD_CG_SUPPORT_IH_CG | 686 AMD_CG_SUPPORT_BIF_MGCG | 687 AMD_CG_SUPPORT_BIF_LS | 688 AMD_CG_SUPPORT_VCN_MGCG | 689 AMD_CG_SUPPORT_JPEG_MGCG; 690 adev->pg_flags = AMD_PG_SUPPORT_VCN | 691 AMD_PG_SUPPORT_VCN_DPG | 692 AMD_PG_SUPPORT_GFX_PG | 693 AMD_PG_SUPPORT_JPEG; 694 adev->external_rev_id = adev->rev_id + 0x80; 695 break; 696 case IP_VERSION(11, 5, 0): 697 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 698 AMD_CG_SUPPORT_JPEG_MGCG | 699 AMD_CG_SUPPORT_GFX_CGCG | 700 AMD_CG_SUPPORT_GFX_CGLS | 701 AMD_CG_SUPPORT_GFX_MGCG | 702 AMD_CG_SUPPORT_GFX_FGCG | 703 AMD_CG_SUPPORT_REPEATER_FGCG | 704 AMD_CG_SUPPORT_GFX_PERF_CLK | 705 AMD_CG_SUPPORT_GFX_3D_CGCG | 706 AMD_CG_SUPPORT_GFX_3D_CGLS | 707 AMD_CG_SUPPORT_MC_MGCG | 708 AMD_CG_SUPPORT_MC_LS | 709 AMD_CG_SUPPORT_HDP_LS | 710 AMD_CG_SUPPORT_HDP_DS | 711 AMD_CG_SUPPORT_HDP_SD | 712 AMD_CG_SUPPORT_ATHUB_MGCG | 713 AMD_CG_SUPPORT_ATHUB_LS | 714 AMD_CG_SUPPORT_IH_CG | 715 AMD_CG_SUPPORT_BIF_MGCG | 716 AMD_CG_SUPPORT_BIF_LS; 717 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 718 AMD_PG_SUPPORT_JPEG_DPG | 719 AMD_PG_SUPPORT_VCN | 720 AMD_PG_SUPPORT_JPEG | 721 AMD_PG_SUPPORT_GFX_PG; 722 if (adev->rev_id == 0) 723 adev->external_rev_id = 0x1; 724 else 725 adev->external_rev_id = adev->rev_id + 0x10; 726 break; 727 case IP_VERSION(11, 5, 1): 728 adev->cg_flags = 729 AMD_CG_SUPPORT_GFX_CGCG | 730 AMD_CG_SUPPORT_GFX_CGLS | 731 AMD_CG_SUPPORT_GFX_MGCG | 732 AMD_CG_SUPPORT_GFX_FGCG | 733 AMD_CG_SUPPORT_REPEATER_FGCG | 734 AMD_CG_SUPPORT_GFX_PERF_CLK | 735 AMD_CG_SUPPORT_GFX_3D_CGCG | 736 AMD_CG_SUPPORT_GFX_3D_CGLS | 737 AMD_CG_SUPPORT_MC_MGCG | 738 AMD_CG_SUPPORT_MC_LS | 739 AMD_CG_SUPPORT_HDP_LS | 740 AMD_CG_SUPPORT_HDP_DS | 741 AMD_CG_SUPPORT_HDP_SD | 742 AMD_CG_SUPPORT_ATHUB_MGCG | 743 AMD_CG_SUPPORT_ATHUB_LS | 744 AMD_CG_SUPPORT_IH_CG | 745 AMD_CG_SUPPORT_BIF_MGCG | 746 AMD_CG_SUPPORT_BIF_LS | 747 AMD_CG_SUPPORT_VCN_MGCG | 748 AMD_CG_SUPPORT_JPEG_MGCG; 749 adev->pg_flags = 750 AMD_PG_SUPPORT_GFX_PG | 751 AMD_PG_SUPPORT_VCN | 752 AMD_PG_SUPPORT_VCN_DPG | 753 AMD_PG_SUPPORT_JPEG; 754 adev->external_rev_id = adev->rev_id + 0xc1; 755 break; 756 case IP_VERSION(11, 5, 2): 757 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 758 AMD_CG_SUPPORT_JPEG_MGCG | 759 AMD_CG_SUPPORT_GFX_CGCG | 760 AMD_CG_SUPPORT_GFX_CGLS | 761 AMD_CG_SUPPORT_GFX_MGCG | 762 AMD_CG_SUPPORT_GFX_FGCG | 763 AMD_CG_SUPPORT_REPEATER_FGCG | 764 AMD_CG_SUPPORT_GFX_PERF_CLK | 765 AMD_CG_SUPPORT_GFX_3D_CGCG | 766 AMD_CG_SUPPORT_GFX_3D_CGLS | 767 AMD_CG_SUPPORT_MC_MGCG | 768 AMD_CG_SUPPORT_MC_LS | 769 AMD_CG_SUPPORT_HDP_LS | 770 AMD_CG_SUPPORT_HDP_DS | 771 AMD_CG_SUPPORT_HDP_SD | 772 AMD_CG_SUPPORT_ATHUB_MGCG | 773 AMD_CG_SUPPORT_ATHUB_LS | 774 AMD_CG_SUPPORT_IH_CG | 775 AMD_CG_SUPPORT_BIF_MGCG | 776 AMD_CG_SUPPORT_BIF_LS; 777 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 778 AMD_PG_SUPPORT_VCN | 779 AMD_PG_SUPPORT_JPEG_DPG | 780 AMD_PG_SUPPORT_JPEG | 781 AMD_PG_SUPPORT_GFX_PG; 782 adev->external_rev_id = adev->rev_id + 0x40; 783 break; 784 default: 785 /* FIXME: not supported yet */ 786 return -EINVAL; 787 } 788 789 if (amdgpu_sriov_vf(adev)) { 790 amdgpu_virt_init_setting(adev); 791 xgpu_nv_mailbox_set_irq_funcs(adev); 792 } 793 794 return 0; 795 } 796 797 static int soc21_common_late_init(void *handle) 798 { 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 801 if (amdgpu_sriov_vf(adev)) { 802 xgpu_nv_mailbox_get_irq(adev); 803 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 804 !amdgpu_sriov_is_av1_support(adev)) { 805 amdgpu_virt_update_sriov_video_codec(adev, 806 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 807 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 808 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 809 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 810 } else { 811 amdgpu_virt_update_sriov_video_codec(adev, 812 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 813 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 814 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 815 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 816 } 817 } else { 818 if (adev->nbio.ras && 819 adev->nbio.ras_err_event_athub_irq.funcs) 820 /* don't need to fail gpu late init 821 * if enabling athub_err_event interrupt failed 822 * nbio v4_3 only support fatal error hanlding 823 * just enable the interrupt directly */ 824 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 825 } 826 827 /* Enable selfring doorbell aperture late because doorbell BAR 828 * aperture will change if resize BAR successfully in gmc sw_init. 829 */ 830 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 831 832 return 0; 833 } 834 835 static int soc21_common_sw_init(void *handle) 836 { 837 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 838 839 if (amdgpu_sriov_vf(adev)) 840 xgpu_nv_mailbox_add_irq_id(adev); 841 842 return 0; 843 } 844 845 static int soc21_common_sw_fini(void *handle) 846 { 847 return 0; 848 } 849 850 static int soc21_common_hw_init(void *handle) 851 { 852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 853 854 /* enable aspm */ 855 soc21_program_aspm(adev); 856 /* setup nbio registers */ 857 adev->nbio.funcs->init_registers(adev); 858 /* remap HDP registers to a hole in mmio space, 859 * for the purpose of expose those registers 860 * to process space 861 */ 862 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 863 adev->nbio.funcs->remap_hdp_registers(adev); 864 /* enable the doorbell aperture */ 865 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 866 867 return 0; 868 } 869 870 static int soc21_common_hw_fini(void *handle) 871 { 872 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 873 874 /* Disable the doorbell aperture and selfring doorbell aperture 875 * separately in hw_fini because soc21_enable_doorbell_aperture 876 * has been removed and there is no need to delay disabling 877 * selfring doorbell. 878 */ 879 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 880 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 881 882 if (amdgpu_sriov_vf(adev)) { 883 xgpu_nv_mailbox_put_irq(adev); 884 } else { 885 if (adev->nbio.ras && 886 adev->nbio.ras_err_event_athub_irq.funcs) 887 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 888 } 889 890 return 0; 891 } 892 893 static int soc21_common_suspend(void *handle) 894 { 895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 896 897 return soc21_common_hw_fini(adev); 898 } 899 900 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 901 { 902 u32 sol_reg1, sol_reg2; 903 904 /* Will reset for the following suspend abort cases. 905 * 1) Only reset dGPU side. 906 * 2) S3 suspend got aborted and TOS is active. 907 */ 908 if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && 909 !adev->suspend_complete) { 910 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 911 msleep(100); 912 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 913 914 return (sol_reg1 != sol_reg2); 915 } 916 917 return false; 918 } 919 920 static int soc21_common_resume(void *handle) 921 { 922 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 923 924 if (soc21_need_reset_on_resume(adev)) { 925 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 926 soc21_asic_reset(adev); 927 } 928 929 return soc21_common_hw_init(adev); 930 } 931 932 static bool soc21_common_is_idle(void *handle) 933 { 934 return true; 935 } 936 937 static int soc21_common_wait_for_idle(void *handle) 938 { 939 return 0; 940 } 941 942 static int soc21_common_soft_reset(void *handle) 943 { 944 return 0; 945 } 946 947 static int soc21_common_set_clockgating_state(void *handle, 948 enum amd_clockgating_state state) 949 { 950 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 951 952 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 953 case IP_VERSION(4, 3, 0): 954 case IP_VERSION(4, 3, 1): 955 case IP_VERSION(7, 7, 0): 956 case IP_VERSION(7, 7, 1): 957 case IP_VERSION(7, 11, 0): 958 case IP_VERSION(7, 11, 1): 959 case IP_VERSION(7, 11, 3): 960 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 961 state == AMD_CG_STATE_GATE); 962 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 963 state == AMD_CG_STATE_GATE); 964 adev->hdp.funcs->update_clock_gating(adev, 965 state == AMD_CG_STATE_GATE); 966 break; 967 default: 968 break; 969 } 970 return 0; 971 } 972 973 static int soc21_common_set_powergating_state(void *handle, 974 enum amd_powergating_state state) 975 { 976 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 977 978 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 979 case IP_VERSION(6, 0, 0): 980 case IP_VERSION(6, 0, 2): 981 adev->lsdma.funcs->update_memory_power_gating(adev, 982 state == AMD_PG_STATE_GATE); 983 break; 984 default: 985 break; 986 } 987 988 return 0; 989 } 990 991 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 995 adev->nbio.funcs->get_clockgating_state(adev, flags); 996 997 adev->hdp.funcs->get_clock_gating_state(adev, flags); 998 } 999 1000 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1001 .name = "soc21_common", 1002 .early_init = soc21_common_early_init, 1003 .late_init = soc21_common_late_init, 1004 .sw_init = soc21_common_sw_init, 1005 .sw_fini = soc21_common_sw_fini, 1006 .hw_init = soc21_common_hw_init, 1007 .hw_fini = soc21_common_hw_fini, 1008 .suspend = soc21_common_suspend, 1009 .resume = soc21_common_resume, 1010 .is_idle = soc21_common_is_idle, 1011 .wait_for_idle = soc21_common_wait_for_idle, 1012 .soft_reset = soc21_common_soft_reset, 1013 .set_clockgating_state = soc21_common_set_clockgating_state, 1014 .set_powergating_state = soc21_common_set_powergating_state, 1015 .get_clockgating_state = soc21_common_get_clockgating_state, 1016 .dump_ip_state = NULL, 1017 .print_ip_state = NULL, 1018 }; 1019