1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 137 }; 138 139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 142 }; 143 144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { 151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), 152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { 164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), 165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, 166 }; 167 168 169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 170 const struct amdgpu_video_codecs **codecs) 171 { 172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 173 return -EINVAL; 174 175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 176 case IP_VERSION(4, 0, 0): 177 case IP_VERSION(4, 0, 2): 178 case IP_VERSION(4, 0, 4): 179 case IP_VERSION(4, 0, 5): 180 if (amdgpu_sriov_vf(adev)) { 181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 182 !amdgpu_sriov_is_av1_support(adev)) { 183 if (encode) 184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } else { 194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 195 if (encode) 196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 197 else 198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 199 } else { 200 if (encode) 201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 202 else 203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 204 } 205 } 206 return 0; 207 case IP_VERSION(4, 0, 6): 208 if (encode) 209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 210 else 211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 212 return 0; 213 case IP_VERSION(5, 3, 0): 214 if (encode) 215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; 216 else 217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags, address, data; 227 u32 r; 228 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 232 spin_lock_irqsave(&adev->reg.didt.lock, flags); 233 WREG32(address, (reg)); 234 r = RREG32(data); 235 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 236 return r; 237 } 238 239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 240 { 241 unsigned long flags, address, data; 242 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 246 spin_lock_irqsave(&adev->reg.didt.lock, flags); 247 WREG32(address, (reg)); 248 WREG32(data, (v)); 249 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 250 } 251 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 253 { 254 return adev->nbio.funcs->get_memsize(adev); 255 } 256 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 { 259 u32 reference_clock = adev->clock.spll.reference_freq; 260 261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ 262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) 263 return 9981; 264 265 return reference_clock; 266 } 267 268 269 void soc21_grbm_select(struct amdgpu_device *adev, 270 u32 me, u32 pipe, u32 queue, u32 vmid) 271 { 272 u32 grbm_gfx_cntl = 0; 273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 277 278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 279 } 280 281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 282 { 283 /* todo */ 284 return false; 285 } 286 287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 307 }; 308 309 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 310 bool indexed, u32 se_num, 311 u32 sh_num, u32 reg_offset) 312 { 313 if (indexed) { 314 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 315 } else { 316 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 317 return adev->gfx.config.gb_addr_config; 318 return RREG32(reg_offset); 319 } 320 } 321 322 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 323 u32 sh_num, u32 reg_offset, u32 *value) 324 { 325 uint32_t i; 326 struct soc15_allowed_register_entry *en; 327 328 *value = 0; 329 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 330 en = &soc21_allowed_read_registers[i]; 331 if (!adev->reg_offset[en->hwip][en->inst]) 332 continue; 333 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 334 + en->reg_offset)) 335 continue; 336 337 *value = soc21_get_register_value(adev, 338 soc21_allowed_read_registers[i].grbm_indexed, 339 se_num, sh_num, reg_offset); 340 return 0; 341 } 342 return -EINVAL; 343 } 344 345 #if 0 346 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 347 { 348 u32 i; 349 int ret = 0; 350 351 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 352 353 /* disable BM */ 354 pci_clear_master(adev->pdev); 355 356 amdgpu_device_cache_pci_state(adev->pdev); 357 358 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 359 dev_info(adev->dev, "GPU smu mode1 reset\n"); 360 ret = amdgpu_dpm_mode1_reset(adev); 361 } else { 362 dev_info(adev->dev, "GPU psp mode1 reset\n"); 363 ret = psp_gpu_reset(adev); 364 } 365 366 if (ret) 367 dev_err(adev->dev, "GPU mode1 reset failed\n"); 368 amdgpu_device_load_pci_state(adev->pdev); 369 370 /* wait for asic to come out of reset */ 371 for (i = 0; i < adev->usec_timeout; i++) { 372 u32 memsize = adev->nbio.funcs->get_memsize(adev); 373 374 if (memsize != 0xffffffff) 375 break; 376 udelay(1); 377 } 378 379 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 380 381 return ret; 382 } 383 #endif 384 385 static enum amd_reset_method 386 soc21_asic_reset_method(struct amdgpu_device *adev) 387 { 388 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 389 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 390 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 391 return amdgpu_reset_method; 392 393 if (amdgpu_reset_method != -1) 394 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 395 amdgpu_reset_method); 396 397 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 398 case IP_VERSION(13, 0, 0): 399 case IP_VERSION(13, 0, 7): 400 case IP_VERSION(13, 0, 10): 401 return AMD_RESET_METHOD_MODE1; 402 case IP_VERSION(13, 0, 4): 403 case IP_VERSION(13, 0, 11): 404 case IP_VERSION(14, 0, 0): 405 case IP_VERSION(14, 0, 1): 406 case IP_VERSION(14, 0, 4): 407 case IP_VERSION(14, 0, 5): 408 case IP_VERSION(15, 0, 0): 409 return AMD_RESET_METHOD_MODE2; 410 default: 411 if (amdgpu_dpm_is_baco_supported(adev)) 412 return AMD_RESET_METHOD_BACO; 413 else 414 return AMD_RESET_METHOD_MODE1; 415 } 416 } 417 418 static int soc21_asic_reset(struct amdgpu_device *adev) 419 { 420 int ret = 0; 421 422 switch (soc21_asic_reset_method(adev)) { 423 case AMD_RESET_METHOD_PCI: 424 dev_info(adev->dev, "PCI reset\n"); 425 ret = amdgpu_device_pci_reset(adev); 426 break; 427 case AMD_RESET_METHOD_BACO: 428 dev_info(adev->dev, "BACO reset\n"); 429 ret = amdgpu_dpm_baco_reset(adev); 430 break; 431 case AMD_RESET_METHOD_MODE2: 432 dev_info(adev->dev, "MODE2 reset\n"); 433 ret = amdgpu_dpm_mode2_reset(adev); 434 break; 435 default: 436 dev_info(adev->dev, "MODE1 reset\n"); 437 ret = amdgpu_device_mode1_reset(adev); 438 break; 439 } 440 441 return ret; 442 } 443 444 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 445 { 446 /* todo */ 447 return 0; 448 } 449 450 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 451 { 452 /* todo */ 453 return 0; 454 } 455 456 const struct amdgpu_ip_block_version soc21_common_ip_block = { 457 .type = AMD_IP_BLOCK_TYPE_COMMON, 458 .major = 1, 459 .minor = 0, 460 .rev = 0, 461 .funcs = &soc21_common_ip_funcs, 462 }; 463 464 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 465 { 466 u32 sol_reg; 467 468 if (adev->flags & AMD_IS_APU) 469 return false; 470 471 /* Check sOS sign of life register to confirm sys driver and sOS 472 * are already been loaded. 473 */ 474 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 475 if (sol_reg) 476 return true; 477 478 return false; 479 } 480 481 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 482 { 483 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 484 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 485 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 486 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 487 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 488 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 489 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 490 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 491 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 492 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 493 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 494 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 495 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 496 adev->doorbell_index.gfx_userqueue_start = 497 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 498 adev->doorbell_index.gfx_userqueue_end = 499 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 500 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 501 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 502 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 503 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 504 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 505 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 506 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 507 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 508 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 509 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 510 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 511 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 512 513 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 514 adev->doorbell_index.sdma_doorbell_range = 20; 515 } 516 517 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 518 bool enter) 519 { 520 if (enter) 521 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 522 else 523 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 524 525 if (adev->gfx.funcs->update_perfmon_mgcg) 526 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 527 528 return 0; 529 } 530 531 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 532 .read_disabled_bios = &soc21_read_disabled_bios, 533 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 534 .read_register = &soc21_read_register, 535 .reset = &soc21_asic_reset, 536 .reset_method = &soc21_asic_reset_method, 537 .get_xclk = &soc21_get_xclk, 538 .set_uvd_clocks = &soc21_set_uvd_clocks, 539 .set_vce_clocks = &soc21_set_vce_clocks, 540 .get_config_memsize = &soc21_get_config_memsize, 541 .init_doorbell_index = &soc21_init_doorbell_index, 542 .need_reset_on_init = &soc21_need_reset_on_init, 543 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 544 .supports_baco = &amdgpu_dpm_is_baco_supported, 545 .query_video_codecs = &soc21_query_video_codecs, 546 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 547 }; 548 549 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) 550 { 551 struct amdgpu_device *adev = ip_block->adev; 552 553 adev->nbio.funcs->set_reg_remap(adev); 554 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 555 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 556 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 557 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 558 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 559 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 560 561 adev->reg.didt.rreg = &soc21_didt_rreg; 562 adev->reg.didt.wreg = &soc21_didt_wreg; 563 564 adev->asic_funcs = &soc21_asic_funcs; 565 566 adev->rev_id = amdgpu_device_get_rev_id(adev); 567 adev->external_rev_id = 0xff; 568 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 569 case IP_VERSION(11, 0, 0): 570 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 571 AMD_CG_SUPPORT_GFX_CGLS | 572 #if 0 573 AMD_CG_SUPPORT_GFX_3D_CGCG | 574 AMD_CG_SUPPORT_GFX_3D_CGLS | 575 #endif 576 AMD_CG_SUPPORT_GFX_MGCG | 577 AMD_CG_SUPPORT_REPEATER_FGCG | 578 AMD_CG_SUPPORT_GFX_FGCG | 579 AMD_CG_SUPPORT_GFX_PERF_CLK | 580 AMD_CG_SUPPORT_VCN_MGCG | 581 AMD_CG_SUPPORT_JPEG_MGCG | 582 AMD_CG_SUPPORT_ATHUB_MGCG | 583 AMD_CG_SUPPORT_ATHUB_LS | 584 AMD_CG_SUPPORT_MC_MGCG | 585 AMD_CG_SUPPORT_MC_LS | 586 AMD_CG_SUPPORT_IH_CG | 587 AMD_CG_SUPPORT_HDP_SD; 588 adev->pg_flags = AMD_PG_SUPPORT_VCN | 589 AMD_PG_SUPPORT_VCN_DPG | 590 AMD_PG_SUPPORT_JPEG | 591 AMD_PG_SUPPORT_ATHUB | 592 AMD_PG_SUPPORT_MMHUB; 593 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 594 break; 595 case IP_VERSION(11, 0, 2): 596 adev->cg_flags = 597 AMD_CG_SUPPORT_GFX_CGCG | 598 AMD_CG_SUPPORT_GFX_CGLS | 599 AMD_CG_SUPPORT_REPEATER_FGCG | 600 AMD_CG_SUPPORT_VCN_MGCG | 601 AMD_CG_SUPPORT_JPEG_MGCG | 602 AMD_CG_SUPPORT_ATHUB_MGCG | 603 AMD_CG_SUPPORT_ATHUB_LS | 604 AMD_CG_SUPPORT_IH_CG | 605 AMD_CG_SUPPORT_HDP_SD; 606 adev->pg_flags = 607 AMD_PG_SUPPORT_VCN | 608 AMD_PG_SUPPORT_VCN_DPG | 609 AMD_PG_SUPPORT_JPEG | 610 AMD_PG_SUPPORT_ATHUB | 611 AMD_PG_SUPPORT_MMHUB; 612 adev->external_rev_id = adev->rev_id + 0x10; 613 break; 614 case IP_VERSION(11, 0, 1): 615 adev->cg_flags = 616 AMD_CG_SUPPORT_GFX_CGCG | 617 AMD_CG_SUPPORT_GFX_CGLS | 618 AMD_CG_SUPPORT_GFX_MGCG | 619 AMD_CG_SUPPORT_GFX_FGCG | 620 AMD_CG_SUPPORT_REPEATER_FGCG | 621 AMD_CG_SUPPORT_GFX_PERF_CLK | 622 AMD_CG_SUPPORT_MC_MGCG | 623 AMD_CG_SUPPORT_MC_LS | 624 AMD_CG_SUPPORT_HDP_MGCG | 625 AMD_CG_SUPPORT_HDP_LS | 626 AMD_CG_SUPPORT_ATHUB_MGCG | 627 AMD_CG_SUPPORT_ATHUB_LS | 628 AMD_CG_SUPPORT_IH_CG | 629 AMD_CG_SUPPORT_BIF_MGCG | 630 AMD_CG_SUPPORT_BIF_LS | 631 AMD_CG_SUPPORT_VCN_MGCG | 632 AMD_CG_SUPPORT_JPEG_MGCG; 633 adev->pg_flags = 634 AMD_PG_SUPPORT_GFX_PG | 635 AMD_PG_SUPPORT_VCN | 636 AMD_PG_SUPPORT_VCN_DPG | 637 AMD_PG_SUPPORT_JPEG; 638 adev->external_rev_id = adev->rev_id + 0x1; 639 break; 640 case IP_VERSION(11, 0, 3): 641 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 642 AMD_CG_SUPPORT_JPEG_MGCG | 643 AMD_CG_SUPPORT_GFX_CGCG | 644 AMD_CG_SUPPORT_GFX_CGLS | 645 AMD_CG_SUPPORT_REPEATER_FGCG | 646 AMD_CG_SUPPORT_GFX_MGCG | 647 AMD_CG_SUPPORT_HDP_SD | 648 AMD_CG_SUPPORT_ATHUB_MGCG | 649 AMD_CG_SUPPORT_ATHUB_LS; 650 adev->pg_flags = AMD_PG_SUPPORT_VCN | 651 AMD_PG_SUPPORT_VCN_DPG | 652 AMD_PG_SUPPORT_JPEG; 653 adev->external_rev_id = adev->rev_id + 0x20; 654 break; 655 case IP_VERSION(11, 0, 4): 656 adev->cg_flags = 657 AMD_CG_SUPPORT_GFX_CGCG | 658 AMD_CG_SUPPORT_GFX_CGLS | 659 AMD_CG_SUPPORT_GFX_MGCG | 660 AMD_CG_SUPPORT_GFX_FGCG | 661 AMD_CG_SUPPORT_REPEATER_FGCG | 662 AMD_CG_SUPPORT_GFX_PERF_CLK | 663 AMD_CG_SUPPORT_MC_MGCG | 664 AMD_CG_SUPPORT_MC_LS | 665 AMD_CG_SUPPORT_HDP_MGCG | 666 AMD_CG_SUPPORT_HDP_LS | 667 AMD_CG_SUPPORT_ATHUB_MGCG | 668 AMD_CG_SUPPORT_ATHUB_LS | 669 AMD_CG_SUPPORT_IH_CG | 670 AMD_CG_SUPPORT_BIF_MGCG | 671 AMD_CG_SUPPORT_BIF_LS | 672 AMD_CG_SUPPORT_VCN_MGCG | 673 AMD_CG_SUPPORT_JPEG_MGCG; 674 adev->pg_flags = AMD_PG_SUPPORT_VCN | 675 AMD_PG_SUPPORT_VCN_DPG | 676 AMD_PG_SUPPORT_GFX_PG | 677 AMD_PG_SUPPORT_JPEG; 678 adev->external_rev_id = adev->rev_id + 0x80; 679 break; 680 case IP_VERSION(11, 5, 0): 681 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 682 AMD_CG_SUPPORT_JPEG_MGCG | 683 AMD_CG_SUPPORT_GFX_CGCG | 684 AMD_CG_SUPPORT_GFX_CGLS | 685 AMD_CG_SUPPORT_GFX_MGCG | 686 AMD_CG_SUPPORT_GFX_FGCG | 687 AMD_CG_SUPPORT_REPEATER_FGCG | 688 AMD_CG_SUPPORT_GFX_PERF_CLK | 689 AMD_CG_SUPPORT_GFX_3D_CGCG | 690 AMD_CG_SUPPORT_GFX_3D_CGLS | 691 AMD_CG_SUPPORT_MC_MGCG | 692 AMD_CG_SUPPORT_MC_LS | 693 AMD_CG_SUPPORT_HDP_LS | 694 AMD_CG_SUPPORT_HDP_DS | 695 AMD_CG_SUPPORT_HDP_SD | 696 AMD_CG_SUPPORT_ATHUB_MGCG | 697 AMD_CG_SUPPORT_ATHUB_LS | 698 AMD_CG_SUPPORT_IH_CG | 699 AMD_CG_SUPPORT_BIF_MGCG | 700 AMD_CG_SUPPORT_BIF_LS; 701 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 702 AMD_PG_SUPPORT_JPEG_DPG | 703 AMD_PG_SUPPORT_VCN | 704 AMD_PG_SUPPORT_JPEG | 705 AMD_PG_SUPPORT_GFX_PG; 706 if (adev->rev_id == 0) 707 adev->external_rev_id = 0x1; 708 else 709 adev->external_rev_id = adev->rev_id + 0x10; 710 break; 711 case IP_VERSION(11, 5, 1): 712 adev->cg_flags = 713 AMD_CG_SUPPORT_GFX_CGCG | 714 AMD_CG_SUPPORT_GFX_CGLS | 715 AMD_CG_SUPPORT_GFX_MGCG | 716 AMD_CG_SUPPORT_GFX_FGCG | 717 AMD_CG_SUPPORT_REPEATER_FGCG | 718 AMD_CG_SUPPORT_GFX_PERF_CLK | 719 AMD_CG_SUPPORT_GFX_3D_CGCG | 720 AMD_CG_SUPPORT_GFX_3D_CGLS | 721 AMD_CG_SUPPORT_MC_MGCG | 722 AMD_CG_SUPPORT_MC_LS | 723 AMD_CG_SUPPORT_HDP_LS | 724 AMD_CG_SUPPORT_HDP_DS | 725 AMD_CG_SUPPORT_HDP_SD | 726 AMD_CG_SUPPORT_ATHUB_MGCG | 727 AMD_CG_SUPPORT_ATHUB_LS | 728 AMD_CG_SUPPORT_IH_CG | 729 AMD_CG_SUPPORT_BIF_MGCG | 730 AMD_CG_SUPPORT_BIF_LS | 731 AMD_CG_SUPPORT_VCN_MGCG | 732 AMD_CG_SUPPORT_JPEG_MGCG; 733 adev->pg_flags = 734 AMD_PG_SUPPORT_GFX_PG | 735 AMD_PG_SUPPORT_VCN | 736 AMD_PG_SUPPORT_VCN_DPG | 737 AMD_PG_SUPPORT_JPEG; 738 adev->external_rev_id = adev->rev_id + 0xc1; 739 break; 740 case IP_VERSION(11, 5, 2): 741 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 742 AMD_CG_SUPPORT_JPEG_MGCG | 743 AMD_CG_SUPPORT_GFX_CGCG | 744 AMD_CG_SUPPORT_GFX_CGLS | 745 AMD_CG_SUPPORT_GFX_MGCG | 746 AMD_CG_SUPPORT_GFX_FGCG | 747 AMD_CG_SUPPORT_REPEATER_FGCG | 748 AMD_CG_SUPPORT_GFX_PERF_CLK | 749 AMD_CG_SUPPORT_GFX_3D_CGCG | 750 AMD_CG_SUPPORT_GFX_3D_CGLS | 751 AMD_CG_SUPPORT_MC_MGCG | 752 AMD_CG_SUPPORT_MC_LS | 753 AMD_CG_SUPPORT_HDP_LS | 754 AMD_CG_SUPPORT_HDP_DS | 755 AMD_CG_SUPPORT_HDP_SD | 756 AMD_CG_SUPPORT_ATHUB_MGCG | 757 AMD_CG_SUPPORT_ATHUB_LS | 758 AMD_CG_SUPPORT_IH_CG | 759 AMD_CG_SUPPORT_BIF_MGCG | 760 AMD_CG_SUPPORT_BIF_LS; 761 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 762 AMD_PG_SUPPORT_VCN | 763 AMD_PG_SUPPORT_JPEG_DPG | 764 AMD_PG_SUPPORT_JPEG | 765 AMD_PG_SUPPORT_GFX_PG; 766 adev->external_rev_id = adev->rev_id + 0x40; 767 break; 768 case IP_VERSION(11, 5, 3): 769 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 770 AMD_CG_SUPPORT_JPEG_MGCG | 771 AMD_CG_SUPPORT_GFX_CGCG | 772 AMD_CG_SUPPORT_GFX_CGLS | 773 AMD_CG_SUPPORT_GFX_MGCG | 774 AMD_CG_SUPPORT_GFX_FGCG | 775 AMD_CG_SUPPORT_REPEATER_FGCG | 776 AMD_CG_SUPPORT_GFX_PERF_CLK | 777 AMD_CG_SUPPORT_GFX_3D_CGCG | 778 AMD_CG_SUPPORT_GFX_3D_CGLS | 779 AMD_CG_SUPPORT_MC_MGCG | 780 AMD_CG_SUPPORT_MC_LS | 781 AMD_CG_SUPPORT_HDP_LS | 782 AMD_CG_SUPPORT_HDP_DS | 783 AMD_CG_SUPPORT_HDP_SD | 784 AMD_CG_SUPPORT_ATHUB_MGCG | 785 AMD_CG_SUPPORT_ATHUB_LS | 786 AMD_CG_SUPPORT_IH_CG | 787 AMD_CG_SUPPORT_BIF_MGCG | 788 AMD_CG_SUPPORT_BIF_LS; 789 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 790 AMD_PG_SUPPORT_VCN | 791 AMD_PG_SUPPORT_JPEG_DPG | 792 AMD_PG_SUPPORT_JPEG | 793 AMD_PG_SUPPORT_GFX_PG; 794 adev->external_rev_id = adev->rev_id + 0x50; 795 break; 796 case IP_VERSION(11, 5, 4): 797 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 798 AMD_CG_SUPPORT_JPEG_MGCG | 799 AMD_CG_SUPPORT_GFX_CGCG | 800 AMD_CG_SUPPORT_GFX_CGLS | 801 AMD_CG_SUPPORT_GFX_MGCG | 802 AMD_CG_SUPPORT_GFX_FGCG | 803 AMD_CG_SUPPORT_REPEATER_FGCG | 804 AMD_CG_SUPPORT_GFX_PERF_CLK | 805 AMD_CG_SUPPORT_GFX_3D_CGCG | 806 AMD_CG_SUPPORT_GFX_3D_CGLS | 807 AMD_CG_SUPPORT_MC_MGCG | 808 AMD_CG_SUPPORT_MC_LS | 809 AMD_CG_SUPPORT_HDP_LS | 810 AMD_CG_SUPPORT_HDP_DS | 811 AMD_CG_SUPPORT_HDP_SD | 812 AMD_CG_SUPPORT_ATHUB_MGCG | 813 AMD_CG_SUPPORT_ATHUB_LS | 814 AMD_CG_SUPPORT_IH_CG | 815 AMD_CG_SUPPORT_BIF_MGCG | 816 AMD_CG_SUPPORT_BIF_LS; 817 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 818 AMD_PG_SUPPORT_VCN | 819 AMD_PG_SUPPORT_JPEG_DPG | 820 AMD_PG_SUPPORT_JPEG | 821 AMD_PG_SUPPORT_GFX_PG; 822 adev->external_rev_id = adev->rev_id + 0x1; 823 break; 824 case IP_VERSION(11, 5, 6): 825 adev->cg_flags = 0; 826 adev->pg_flags = 0; 827 adev->external_rev_id = adev->rev_id + 0xd0; 828 break; 829 case IP_VERSION(11, 7, 0): 830 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 831 AMD_CG_SUPPORT_JPEG_MGCG | 832 AMD_CG_SUPPORT_GFX_CGCG | 833 AMD_CG_SUPPORT_GFX_CGLS | 834 AMD_CG_SUPPORT_GFX_MGCG | 835 AMD_CG_SUPPORT_GFX_FGCG | 836 AMD_CG_SUPPORT_REPEATER_FGCG | 837 AMD_CG_SUPPORT_GFX_PERF_CLK | 838 AMD_CG_SUPPORT_GFX_3D_CGCG | 839 AMD_CG_SUPPORT_GFX_3D_CGLS | 840 AMD_CG_SUPPORT_MC_MGCG | 841 AMD_CG_SUPPORT_MC_LS | 842 AMD_CG_SUPPORT_HDP_LS | 843 AMD_CG_SUPPORT_HDP_DS | 844 AMD_CG_SUPPORT_HDP_SD | 845 AMD_CG_SUPPORT_ATHUB_MGCG | 846 AMD_CG_SUPPORT_ATHUB_LS | 847 AMD_CG_SUPPORT_IH_CG | 848 AMD_CG_SUPPORT_BIF_MGCG | 849 AMD_CG_SUPPORT_BIF_LS; 850 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 851 AMD_PG_SUPPORT_VCN | 852 AMD_PG_SUPPORT_JPEG_DPG | 853 AMD_PG_SUPPORT_JPEG | 854 AMD_PG_SUPPORT_GFX_PG; 855 adev->external_rev_id = adev->rev_id + 0xF; 856 break; 857 case IP_VERSION(11, 7, 1): 858 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 859 AMD_CG_SUPPORT_JPEG_MGCG | 860 AMD_CG_SUPPORT_GFX_CGCG | 861 AMD_CG_SUPPORT_GFX_CGLS | 862 AMD_CG_SUPPORT_GFX_MGCG | 863 AMD_CG_SUPPORT_GFX_FGCG | 864 AMD_CG_SUPPORT_REPEATER_FGCG | 865 AMD_CG_SUPPORT_GFX_PERF_CLK | 866 AMD_CG_SUPPORT_GFX_3D_CGCG | 867 AMD_CG_SUPPORT_GFX_3D_CGLS | 868 AMD_CG_SUPPORT_MC_MGCG | 869 AMD_CG_SUPPORT_MC_LS | 870 AMD_CG_SUPPORT_HDP_LS | 871 AMD_CG_SUPPORT_HDP_DS | 872 AMD_CG_SUPPORT_HDP_SD | 873 AMD_CG_SUPPORT_ATHUB_MGCG | 874 AMD_CG_SUPPORT_ATHUB_LS | 875 AMD_CG_SUPPORT_IH_CG | 876 AMD_CG_SUPPORT_BIF_MGCG | 877 AMD_CG_SUPPORT_BIF_LS; 878 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 879 AMD_PG_SUPPORT_VCN | 880 AMD_PG_SUPPORT_JPEG_DPG | 881 AMD_PG_SUPPORT_JPEG | 882 AMD_PG_SUPPORT_GFX_PG; 883 adev->external_rev_id = adev->rev_id + 0x40; 884 break; 885 default: 886 /* FIXME: not supported yet */ 887 return -EINVAL; 888 } 889 890 if (amdgpu_sriov_vf(adev)) { 891 amdgpu_virt_init_setting(adev); 892 xgpu_nv_mailbox_set_irq_funcs(adev); 893 } 894 895 return 0; 896 } 897 898 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) 899 { 900 struct amdgpu_device *adev = ip_block->adev; 901 902 if (amdgpu_sriov_vf(adev)) { 903 xgpu_nv_mailbox_get_irq(adev); 904 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 905 !amdgpu_sriov_is_av1_support(adev)) { 906 amdgpu_virt_update_sriov_video_codec(adev, 907 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 908 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 909 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 910 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 911 } else { 912 amdgpu_virt_update_sriov_video_codec(adev, 913 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 914 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 915 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 916 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 917 } 918 } else { 919 if (adev->nbio.ras && 920 adev->nbio.ras_err_event_athub_irq.funcs) 921 /* don't need to fail gpu late init 922 * if enabling athub_err_event interrupt failed 923 * nbio v4_3 only support fatal error hanlding 924 * just enable the interrupt directly */ 925 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 926 } 927 928 /* Enable selfring doorbell aperture late because doorbell BAR 929 * aperture will change if resize BAR successfully in gmc sw_init. 930 */ 931 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 932 933 return 0; 934 } 935 936 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) 937 { 938 struct amdgpu_device *adev = ip_block->adev; 939 940 if (amdgpu_sriov_vf(adev)) 941 xgpu_nv_mailbox_add_irq_id(adev); 942 943 return 0; 944 } 945 946 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) 947 { 948 struct amdgpu_device *adev = ip_block->adev; 949 950 /* enable aspm */ 951 amdgpu_nbio_program_aspm(adev); 952 /* setup nbio registers */ 953 adev->nbio.funcs->init_registers(adev); 954 /* remap HDP registers to a hole in mmio space, 955 * for the purpose of expose those registers 956 * to process space 957 */ 958 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 959 adev->nbio.funcs->remap_hdp_registers(adev); 960 /* enable the doorbell aperture */ 961 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 962 963 return 0; 964 } 965 966 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) 967 { 968 struct amdgpu_device *adev = ip_block->adev; 969 970 /* Disable the doorbell aperture and selfring doorbell aperture 971 * separately in hw_fini because soc21_enable_doorbell_aperture 972 * has been removed and there is no need to delay disabling 973 * selfring doorbell. 974 */ 975 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 976 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 977 978 if (amdgpu_sriov_vf(adev)) { 979 xgpu_nv_mailbox_put_irq(adev); 980 } else { 981 if (adev->nbio.ras && 982 adev->nbio.ras_err_event_athub_irq.funcs) 983 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 984 } 985 986 return 0; 987 } 988 989 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) 990 { 991 return soc21_common_hw_fini(ip_block); 992 } 993 994 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 995 { 996 u32 sol_reg1, sol_reg2; 997 998 /* Will reset for the following suspend abort cases. 999 * 1) Only reset dGPU side. 1000 * 2) S3 suspend got aborted and TOS is active. 1001 * As for dGPU suspend abort cases the SOL value 1002 * will be kept as zero at this resume point. 1003 */ 1004 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 1005 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1006 msleep(100); 1007 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1008 1009 return (sol_reg1 != sol_reg2); 1010 } 1011 1012 return false; 1013 } 1014 1015 static int soc21_common_resume(struct amdgpu_ip_block *ip_block) 1016 { 1017 struct amdgpu_device *adev = ip_block->adev; 1018 1019 if (soc21_need_reset_on_resume(adev)) { 1020 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 1021 soc21_asic_reset(adev); 1022 } 1023 1024 return soc21_common_hw_init(ip_block); 1025 } 1026 1027 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block) 1028 { 1029 return true; 1030 } 1031 1032 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1033 enum amd_clockgating_state state) 1034 { 1035 struct amdgpu_device *adev = ip_block->adev; 1036 1037 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1038 case IP_VERSION(4, 3, 0): 1039 case IP_VERSION(4, 3, 1): 1040 case IP_VERSION(7, 7, 0): 1041 case IP_VERSION(7, 7, 1): 1042 case IP_VERSION(7, 11, 0): 1043 case IP_VERSION(7, 11, 1): 1044 case IP_VERSION(7, 11, 2): 1045 case IP_VERSION(7, 11, 3): 1046 case IP_VERSION(7, 11, 4): 1047 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1048 state == AMD_CG_STATE_GATE); 1049 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1050 state == AMD_CG_STATE_GATE); 1051 adev->hdp.funcs->update_clock_gating(adev, 1052 state == AMD_CG_STATE_GATE); 1053 break; 1054 default: 1055 break; 1056 } 1057 return 0; 1058 } 1059 1060 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1061 enum amd_powergating_state state) 1062 { 1063 struct amdgpu_device *adev = ip_block->adev; 1064 1065 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 1066 case IP_VERSION(6, 0, 0): 1067 case IP_VERSION(6, 0, 2): 1068 adev->lsdma.funcs->update_memory_power_gating(adev, 1069 state == AMD_PG_STATE_GATE); 1070 break; 1071 default: 1072 break; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1079 { 1080 struct amdgpu_device *adev = ip_block->adev; 1081 1082 adev->nbio.funcs->get_clockgating_state(adev, flags); 1083 1084 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1085 } 1086 1087 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1088 .name = "soc21_common", 1089 .early_init = soc21_common_early_init, 1090 .late_init = soc21_common_late_init, 1091 .sw_init = soc21_common_sw_init, 1092 .hw_init = soc21_common_hw_init, 1093 .hw_fini = soc21_common_hw_fini, 1094 .suspend = soc21_common_suspend, 1095 .resume = soc21_common_resume, 1096 .is_idle = soc21_common_is_idle, 1097 .set_clockgating_state = soc21_common_set_clockgating_state, 1098 .set_powergating_state = soc21_common_set_powergating_state, 1099 .get_clockgating_state = soc21_common_get_clockgating_state, 1100 }; 1101