1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 137 }; 138 139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 142 }; 143 144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { 151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), 152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { 164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), 165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, 166 }; 167 168 169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 170 const struct amdgpu_video_codecs **codecs) 171 { 172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 173 return -EINVAL; 174 175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 176 case IP_VERSION(4, 0, 0): 177 case IP_VERSION(4, 0, 2): 178 case IP_VERSION(4, 0, 4): 179 case IP_VERSION(4, 0, 5): 180 if (amdgpu_sriov_vf(adev)) { 181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 182 !amdgpu_sriov_is_av1_support(adev)) { 183 if (encode) 184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } else { 194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 195 if (encode) 196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 197 else 198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 199 } else { 200 if (encode) 201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 202 else 203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 204 } 205 } 206 return 0; 207 case IP_VERSION(4, 0, 6): 208 if (encode) 209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 210 else 211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 212 return 0; 213 case IP_VERSION(5, 3, 0): 214 if (encode) 215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; 216 else 217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags, address, data; 227 u32 r; 228 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 232 spin_lock_irqsave(&adev->reg.didt.lock, flags); 233 WREG32(address, (reg)); 234 r = RREG32(data); 235 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 236 return r; 237 } 238 239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 240 { 241 unsigned long flags, address, data; 242 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 246 spin_lock_irqsave(&adev->reg.didt.lock, flags); 247 WREG32(address, (reg)); 248 WREG32(data, (v)); 249 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 250 } 251 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 253 { 254 return adev->nbio.funcs->get_memsize(adev); 255 } 256 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 { 259 u32 reference_clock = adev->clock.spll.reference_freq; 260 261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ 262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) 263 return 9981; 264 265 return reference_clock; 266 } 267 268 269 void soc21_grbm_select(struct amdgpu_device *adev, 270 u32 me, u32 pipe, u32 queue, u32 vmid) 271 { 272 u32 grbm_gfx_cntl = 0; 273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 277 278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 279 } 280 281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 282 { 283 /* todo */ 284 return false; 285 } 286 287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 307 }; 308 309 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 310 bool indexed, u32 se_num, 311 u32 sh_num, u32 reg_offset) 312 { 313 if (indexed) { 314 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 315 } else { 316 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 317 return adev->gfx.config.gb_addr_config; 318 return RREG32(reg_offset); 319 } 320 } 321 322 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 323 u32 sh_num, u32 reg_offset, u32 *value) 324 { 325 uint32_t i; 326 struct soc15_allowed_register_entry *en; 327 328 *value = 0; 329 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 330 en = &soc21_allowed_read_registers[i]; 331 if (!adev->reg_offset[en->hwip][en->inst]) 332 continue; 333 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 334 + en->reg_offset)) 335 continue; 336 337 *value = soc21_get_register_value(adev, 338 soc21_allowed_read_registers[i].grbm_indexed, 339 se_num, sh_num, reg_offset); 340 return 0; 341 } 342 return -EINVAL; 343 } 344 345 #if 0 346 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 347 { 348 u32 i; 349 int ret = 0; 350 351 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 352 353 /* disable BM */ 354 pci_clear_master(adev->pdev); 355 356 amdgpu_device_cache_pci_state(adev->pdev); 357 358 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 359 dev_info(adev->dev, "GPU smu mode1 reset\n"); 360 ret = amdgpu_dpm_mode1_reset(adev); 361 } else { 362 dev_info(adev->dev, "GPU psp mode1 reset\n"); 363 ret = psp_gpu_reset(adev); 364 } 365 366 if (ret) 367 dev_err(adev->dev, "GPU mode1 reset failed\n"); 368 amdgpu_device_load_pci_state(adev->pdev); 369 370 /* wait for asic to come out of reset */ 371 for (i = 0; i < adev->usec_timeout; i++) { 372 u32 memsize = adev->nbio.funcs->get_memsize(adev); 373 374 if (memsize != 0xffffffff) 375 break; 376 udelay(1); 377 } 378 379 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 380 381 return ret; 382 } 383 #endif 384 385 static enum amd_reset_method 386 soc21_asic_reset_method(struct amdgpu_device *adev) 387 { 388 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 389 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 390 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 391 return amdgpu_reset_method; 392 393 if (amdgpu_reset_method != -1) 394 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 395 amdgpu_reset_method); 396 397 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 398 case IP_VERSION(13, 0, 0): 399 case IP_VERSION(13, 0, 7): 400 case IP_VERSION(13, 0, 10): 401 return AMD_RESET_METHOD_MODE1; 402 case IP_VERSION(13, 0, 4): 403 case IP_VERSION(13, 0, 11): 404 case IP_VERSION(14, 0, 0): 405 case IP_VERSION(14, 0, 1): 406 case IP_VERSION(14, 0, 4): 407 case IP_VERSION(14, 0, 5): 408 case IP_VERSION(15, 0, 0): 409 case IP_VERSION(15, 0, 5): 410 case IP_VERSION(15, 0, 9): 411 return AMD_RESET_METHOD_MODE2; 412 default: 413 if (amdgpu_dpm_is_baco_supported(adev)) 414 return AMD_RESET_METHOD_BACO; 415 else 416 return AMD_RESET_METHOD_MODE1; 417 } 418 } 419 420 static int soc21_asic_reset(struct amdgpu_device *adev) 421 { 422 int ret = 0; 423 424 switch (soc21_asic_reset_method(adev)) { 425 case AMD_RESET_METHOD_PCI: 426 dev_info(adev->dev, "PCI reset\n"); 427 ret = amdgpu_device_pci_reset(adev); 428 break; 429 case AMD_RESET_METHOD_BACO: 430 dev_info(adev->dev, "BACO reset\n"); 431 ret = amdgpu_dpm_baco_reset(adev); 432 break; 433 case AMD_RESET_METHOD_MODE2: 434 dev_info(adev->dev, "MODE2 reset\n"); 435 ret = amdgpu_dpm_mode2_reset(adev); 436 break; 437 default: 438 dev_info(adev->dev, "MODE1 reset\n"); 439 ret = amdgpu_device_mode1_reset(adev); 440 break; 441 } 442 443 return ret; 444 } 445 446 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 447 { 448 /* todo */ 449 return 0; 450 } 451 452 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 453 { 454 /* todo */ 455 return 0; 456 } 457 458 const struct amdgpu_ip_block_version soc21_common_ip_block = { 459 .type = AMD_IP_BLOCK_TYPE_COMMON, 460 .major = 1, 461 .minor = 0, 462 .rev = 0, 463 .funcs = &soc21_common_ip_funcs, 464 }; 465 466 static bool soc21_need_full_reset(struct amdgpu_device *adev) 467 { 468 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 469 case IP_VERSION(11, 0, 0): 470 case IP_VERSION(11, 0, 2): 471 case IP_VERSION(11, 0, 3): 472 default: 473 return true; 474 } 475 } 476 477 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 478 { 479 u32 sol_reg; 480 481 if (adev->flags & AMD_IS_APU) 482 return false; 483 484 /* Check sOS sign of life register to confirm sys driver and sOS 485 * are already been loaded. 486 */ 487 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 488 if (sol_reg) 489 return true; 490 491 return false; 492 } 493 494 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 495 { 496 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 497 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 498 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 499 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 500 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 501 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 502 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 503 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 504 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 505 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 506 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 507 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 508 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 509 adev->doorbell_index.gfx_userqueue_start = 510 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 511 adev->doorbell_index.gfx_userqueue_end = 512 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 513 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 514 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 515 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 516 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 517 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 518 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 519 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 520 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 521 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 522 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 523 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 524 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 525 526 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 527 adev->doorbell_index.sdma_doorbell_range = 20; 528 } 529 530 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 531 bool enter) 532 { 533 if (enter) 534 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 535 else 536 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 537 538 if (adev->gfx.funcs->update_perfmon_mgcg) 539 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 540 541 return 0; 542 } 543 544 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 545 .read_disabled_bios = &soc21_read_disabled_bios, 546 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 547 .read_register = &soc21_read_register, 548 .reset = &soc21_asic_reset, 549 .reset_method = &soc21_asic_reset_method, 550 .get_xclk = &soc21_get_xclk, 551 .set_uvd_clocks = &soc21_set_uvd_clocks, 552 .set_vce_clocks = &soc21_set_vce_clocks, 553 .get_config_memsize = &soc21_get_config_memsize, 554 .init_doorbell_index = &soc21_init_doorbell_index, 555 .need_full_reset = &soc21_need_full_reset, 556 .need_reset_on_init = &soc21_need_reset_on_init, 557 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 558 .supports_baco = &amdgpu_dpm_is_baco_supported, 559 .query_video_codecs = &soc21_query_video_codecs, 560 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 561 }; 562 563 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) 564 { 565 struct amdgpu_device *adev = ip_block->adev; 566 567 adev->nbio.funcs->set_reg_remap(adev); 568 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 569 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 570 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 571 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 572 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 573 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 574 575 adev->reg.didt.rreg = &soc21_didt_rreg; 576 adev->reg.didt.wreg = &soc21_didt_wreg; 577 578 adev->asic_funcs = &soc21_asic_funcs; 579 580 adev->rev_id = amdgpu_device_get_rev_id(adev); 581 adev->external_rev_id = 0xff; 582 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 583 case IP_VERSION(11, 0, 0): 584 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 585 AMD_CG_SUPPORT_GFX_CGLS | 586 #if 0 587 AMD_CG_SUPPORT_GFX_3D_CGCG | 588 AMD_CG_SUPPORT_GFX_3D_CGLS | 589 #endif 590 AMD_CG_SUPPORT_GFX_MGCG | 591 AMD_CG_SUPPORT_REPEATER_FGCG | 592 AMD_CG_SUPPORT_GFX_FGCG | 593 AMD_CG_SUPPORT_GFX_PERF_CLK | 594 AMD_CG_SUPPORT_VCN_MGCG | 595 AMD_CG_SUPPORT_JPEG_MGCG | 596 AMD_CG_SUPPORT_ATHUB_MGCG | 597 AMD_CG_SUPPORT_ATHUB_LS | 598 AMD_CG_SUPPORT_MC_MGCG | 599 AMD_CG_SUPPORT_MC_LS | 600 AMD_CG_SUPPORT_IH_CG | 601 AMD_CG_SUPPORT_HDP_SD; 602 adev->pg_flags = AMD_PG_SUPPORT_VCN | 603 AMD_PG_SUPPORT_VCN_DPG | 604 AMD_PG_SUPPORT_JPEG | 605 AMD_PG_SUPPORT_ATHUB | 606 AMD_PG_SUPPORT_MMHUB; 607 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 608 break; 609 case IP_VERSION(11, 0, 2): 610 adev->cg_flags = 611 AMD_CG_SUPPORT_GFX_CGCG | 612 AMD_CG_SUPPORT_GFX_CGLS | 613 AMD_CG_SUPPORT_REPEATER_FGCG | 614 AMD_CG_SUPPORT_VCN_MGCG | 615 AMD_CG_SUPPORT_JPEG_MGCG | 616 AMD_CG_SUPPORT_ATHUB_MGCG | 617 AMD_CG_SUPPORT_ATHUB_LS | 618 AMD_CG_SUPPORT_IH_CG | 619 AMD_CG_SUPPORT_HDP_SD; 620 adev->pg_flags = 621 AMD_PG_SUPPORT_VCN | 622 AMD_PG_SUPPORT_VCN_DPG | 623 AMD_PG_SUPPORT_JPEG | 624 AMD_PG_SUPPORT_ATHUB | 625 AMD_PG_SUPPORT_MMHUB; 626 adev->external_rev_id = adev->rev_id + 0x10; 627 break; 628 case IP_VERSION(11, 0, 1): 629 adev->cg_flags = 630 AMD_CG_SUPPORT_GFX_CGCG | 631 AMD_CG_SUPPORT_GFX_CGLS | 632 AMD_CG_SUPPORT_GFX_MGCG | 633 AMD_CG_SUPPORT_GFX_FGCG | 634 AMD_CG_SUPPORT_REPEATER_FGCG | 635 AMD_CG_SUPPORT_GFX_PERF_CLK | 636 AMD_CG_SUPPORT_MC_MGCG | 637 AMD_CG_SUPPORT_MC_LS | 638 AMD_CG_SUPPORT_HDP_MGCG | 639 AMD_CG_SUPPORT_HDP_LS | 640 AMD_CG_SUPPORT_ATHUB_MGCG | 641 AMD_CG_SUPPORT_ATHUB_LS | 642 AMD_CG_SUPPORT_IH_CG | 643 AMD_CG_SUPPORT_BIF_MGCG | 644 AMD_CG_SUPPORT_BIF_LS | 645 AMD_CG_SUPPORT_VCN_MGCG | 646 AMD_CG_SUPPORT_JPEG_MGCG; 647 adev->pg_flags = 648 AMD_PG_SUPPORT_GFX_PG | 649 AMD_PG_SUPPORT_VCN | 650 AMD_PG_SUPPORT_VCN_DPG | 651 AMD_PG_SUPPORT_JPEG; 652 adev->external_rev_id = adev->rev_id + 0x1; 653 break; 654 case IP_VERSION(11, 0, 3): 655 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 656 AMD_CG_SUPPORT_JPEG_MGCG | 657 AMD_CG_SUPPORT_GFX_CGCG | 658 AMD_CG_SUPPORT_GFX_CGLS | 659 AMD_CG_SUPPORT_REPEATER_FGCG | 660 AMD_CG_SUPPORT_GFX_MGCG | 661 AMD_CG_SUPPORT_HDP_SD | 662 AMD_CG_SUPPORT_ATHUB_MGCG | 663 AMD_CG_SUPPORT_ATHUB_LS; 664 adev->pg_flags = AMD_PG_SUPPORT_VCN | 665 AMD_PG_SUPPORT_VCN_DPG | 666 AMD_PG_SUPPORT_JPEG; 667 adev->external_rev_id = adev->rev_id + 0x20; 668 break; 669 case IP_VERSION(11, 0, 4): 670 adev->cg_flags = 671 AMD_CG_SUPPORT_GFX_CGCG | 672 AMD_CG_SUPPORT_GFX_CGLS | 673 AMD_CG_SUPPORT_GFX_MGCG | 674 AMD_CG_SUPPORT_GFX_FGCG | 675 AMD_CG_SUPPORT_REPEATER_FGCG | 676 AMD_CG_SUPPORT_GFX_PERF_CLK | 677 AMD_CG_SUPPORT_MC_MGCG | 678 AMD_CG_SUPPORT_MC_LS | 679 AMD_CG_SUPPORT_HDP_MGCG | 680 AMD_CG_SUPPORT_HDP_LS | 681 AMD_CG_SUPPORT_ATHUB_MGCG | 682 AMD_CG_SUPPORT_ATHUB_LS | 683 AMD_CG_SUPPORT_IH_CG | 684 AMD_CG_SUPPORT_BIF_MGCG | 685 AMD_CG_SUPPORT_BIF_LS | 686 AMD_CG_SUPPORT_VCN_MGCG | 687 AMD_CG_SUPPORT_JPEG_MGCG; 688 adev->pg_flags = AMD_PG_SUPPORT_VCN | 689 AMD_PG_SUPPORT_VCN_DPG | 690 AMD_PG_SUPPORT_GFX_PG | 691 AMD_PG_SUPPORT_JPEG; 692 adev->external_rev_id = adev->rev_id + 0x80; 693 break; 694 case IP_VERSION(11, 5, 0): 695 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 696 AMD_CG_SUPPORT_JPEG_MGCG | 697 AMD_CG_SUPPORT_GFX_CGCG | 698 AMD_CG_SUPPORT_GFX_CGLS | 699 AMD_CG_SUPPORT_GFX_MGCG | 700 AMD_CG_SUPPORT_GFX_FGCG | 701 AMD_CG_SUPPORT_REPEATER_FGCG | 702 AMD_CG_SUPPORT_GFX_PERF_CLK | 703 AMD_CG_SUPPORT_GFX_3D_CGCG | 704 AMD_CG_SUPPORT_GFX_3D_CGLS | 705 AMD_CG_SUPPORT_MC_MGCG | 706 AMD_CG_SUPPORT_MC_LS | 707 AMD_CG_SUPPORT_HDP_LS | 708 AMD_CG_SUPPORT_HDP_DS | 709 AMD_CG_SUPPORT_HDP_SD | 710 AMD_CG_SUPPORT_ATHUB_MGCG | 711 AMD_CG_SUPPORT_ATHUB_LS | 712 AMD_CG_SUPPORT_IH_CG | 713 AMD_CG_SUPPORT_BIF_MGCG | 714 AMD_CG_SUPPORT_BIF_LS; 715 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 716 AMD_PG_SUPPORT_JPEG_DPG | 717 AMD_PG_SUPPORT_VCN | 718 AMD_PG_SUPPORT_JPEG | 719 AMD_PG_SUPPORT_GFX_PG; 720 if (adev->rev_id == 0) 721 adev->external_rev_id = 0x1; 722 else 723 adev->external_rev_id = adev->rev_id + 0x10; 724 break; 725 case IP_VERSION(11, 5, 1): 726 adev->cg_flags = 727 AMD_CG_SUPPORT_GFX_CGCG | 728 AMD_CG_SUPPORT_GFX_CGLS | 729 AMD_CG_SUPPORT_GFX_MGCG | 730 AMD_CG_SUPPORT_GFX_FGCG | 731 AMD_CG_SUPPORT_REPEATER_FGCG | 732 AMD_CG_SUPPORT_GFX_PERF_CLK | 733 AMD_CG_SUPPORT_GFX_3D_CGCG | 734 AMD_CG_SUPPORT_GFX_3D_CGLS | 735 AMD_CG_SUPPORT_MC_MGCG | 736 AMD_CG_SUPPORT_MC_LS | 737 AMD_CG_SUPPORT_HDP_LS | 738 AMD_CG_SUPPORT_HDP_DS | 739 AMD_CG_SUPPORT_HDP_SD | 740 AMD_CG_SUPPORT_ATHUB_MGCG | 741 AMD_CG_SUPPORT_ATHUB_LS | 742 AMD_CG_SUPPORT_IH_CG | 743 AMD_CG_SUPPORT_BIF_MGCG | 744 AMD_CG_SUPPORT_BIF_LS | 745 AMD_CG_SUPPORT_VCN_MGCG | 746 AMD_CG_SUPPORT_JPEG_MGCG; 747 adev->pg_flags = 748 AMD_PG_SUPPORT_GFX_PG | 749 AMD_PG_SUPPORT_VCN | 750 AMD_PG_SUPPORT_VCN_DPG | 751 AMD_PG_SUPPORT_JPEG; 752 adev->external_rev_id = adev->rev_id + 0xc1; 753 break; 754 case IP_VERSION(11, 5, 2): 755 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 756 AMD_CG_SUPPORT_JPEG_MGCG | 757 AMD_CG_SUPPORT_GFX_CGCG | 758 AMD_CG_SUPPORT_GFX_CGLS | 759 AMD_CG_SUPPORT_GFX_MGCG | 760 AMD_CG_SUPPORT_GFX_FGCG | 761 AMD_CG_SUPPORT_REPEATER_FGCG | 762 AMD_CG_SUPPORT_GFX_PERF_CLK | 763 AMD_CG_SUPPORT_GFX_3D_CGCG | 764 AMD_CG_SUPPORT_GFX_3D_CGLS | 765 AMD_CG_SUPPORT_MC_MGCG | 766 AMD_CG_SUPPORT_MC_LS | 767 AMD_CG_SUPPORT_HDP_LS | 768 AMD_CG_SUPPORT_HDP_DS | 769 AMD_CG_SUPPORT_HDP_SD | 770 AMD_CG_SUPPORT_ATHUB_MGCG | 771 AMD_CG_SUPPORT_ATHUB_LS | 772 AMD_CG_SUPPORT_IH_CG | 773 AMD_CG_SUPPORT_BIF_MGCG | 774 AMD_CG_SUPPORT_BIF_LS; 775 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 776 AMD_PG_SUPPORT_VCN | 777 AMD_PG_SUPPORT_JPEG_DPG | 778 AMD_PG_SUPPORT_JPEG | 779 AMD_PG_SUPPORT_GFX_PG; 780 adev->external_rev_id = adev->rev_id + 0x40; 781 break; 782 case IP_VERSION(11, 5, 3): 783 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 784 AMD_CG_SUPPORT_JPEG_MGCG | 785 AMD_CG_SUPPORT_GFX_CGCG | 786 AMD_CG_SUPPORT_GFX_CGLS | 787 AMD_CG_SUPPORT_GFX_MGCG | 788 AMD_CG_SUPPORT_GFX_FGCG | 789 AMD_CG_SUPPORT_REPEATER_FGCG | 790 AMD_CG_SUPPORT_GFX_PERF_CLK | 791 AMD_CG_SUPPORT_GFX_3D_CGCG | 792 AMD_CG_SUPPORT_GFX_3D_CGLS | 793 AMD_CG_SUPPORT_MC_MGCG | 794 AMD_CG_SUPPORT_MC_LS | 795 AMD_CG_SUPPORT_HDP_LS | 796 AMD_CG_SUPPORT_HDP_DS | 797 AMD_CG_SUPPORT_HDP_SD | 798 AMD_CG_SUPPORT_ATHUB_MGCG | 799 AMD_CG_SUPPORT_ATHUB_LS | 800 AMD_CG_SUPPORT_IH_CG | 801 AMD_CG_SUPPORT_BIF_MGCG | 802 AMD_CG_SUPPORT_BIF_LS; 803 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 804 AMD_PG_SUPPORT_VCN | 805 AMD_PG_SUPPORT_JPEG_DPG | 806 AMD_PG_SUPPORT_JPEG | 807 AMD_PG_SUPPORT_GFX_PG; 808 adev->external_rev_id = adev->rev_id + 0x50; 809 break; 810 case IP_VERSION(11, 5, 4): 811 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 812 AMD_CG_SUPPORT_JPEG_MGCG | 813 AMD_CG_SUPPORT_GFX_CGCG | 814 AMD_CG_SUPPORT_GFX_CGLS | 815 AMD_CG_SUPPORT_GFX_MGCG | 816 AMD_CG_SUPPORT_GFX_FGCG | 817 AMD_CG_SUPPORT_REPEATER_FGCG | 818 AMD_CG_SUPPORT_GFX_PERF_CLK | 819 AMD_CG_SUPPORT_GFX_3D_CGCG | 820 AMD_CG_SUPPORT_GFX_3D_CGLS | 821 AMD_CG_SUPPORT_MC_MGCG | 822 AMD_CG_SUPPORT_MC_LS | 823 AMD_CG_SUPPORT_HDP_LS | 824 AMD_CG_SUPPORT_HDP_DS | 825 AMD_CG_SUPPORT_HDP_SD | 826 AMD_CG_SUPPORT_ATHUB_MGCG | 827 AMD_CG_SUPPORT_ATHUB_LS | 828 AMD_CG_SUPPORT_IH_CG | 829 AMD_CG_SUPPORT_BIF_MGCG | 830 AMD_CG_SUPPORT_BIF_LS; 831 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 832 AMD_PG_SUPPORT_VCN | 833 AMD_PG_SUPPORT_JPEG_DPG | 834 AMD_PG_SUPPORT_JPEG | 835 AMD_PG_SUPPORT_GFX_PG; 836 adev->external_rev_id = adev->rev_id + 0x1; 837 break; 838 case IP_VERSION(11, 5, 6): 839 adev->cg_flags = 0; 840 adev->pg_flags = 0; 841 adev->external_rev_id = adev->rev_id + 0xd0; 842 break; 843 case IP_VERSION(11, 7, 0): 844 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 845 AMD_CG_SUPPORT_JPEG_MGCG | 846 AMD_CG_SUPPORT_GFX_CGCG | 847 AMD_CG_SUPPORT_GFX_CGLS | 848 AMD_CG_SUPPORT_GFX_MGCG | 849 AMD_CG_SUPPORT_GFX_FGCG | 850 AMD_CG_SUPPORT_REPEATER_FGCG | 851 AMD_CG_SUPPORT_GFX_PERF_CLK | 852 AMD_CG_SUPPORT_GFX_3D_CGCG | 853 AMD_CG_SUPPORT_GFX_3D_CGLS | 854 AMD_CG_SUPPORT_MC_MGCG | 855 AMD_CG_SUPPORT_MC_LS | 856 AMD_CG_SUPPORT_HDP_LS | 857 AMD_CG_SUPPORT_HDP_DS | 858 AMD_CG_SUPPORT_HDP_SD | 859 AMD_CG_SUPPORT_ATHUB_MGCG | 860 AMD_CG_SUPPORT_ATHUB_LS | 861 AMD_CG_SUPPORT_IH_CG | 862 AMD_CG_SUPPORT_BIF_MGCG | 863 AMD_CG_SUPPORT_BIF_LS; 864 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 865 AMD_PG_SUPPORT_VCN | 866 AMD_PG_SUPPORT_JPEG | 867 AMD_PG_SUPPORT_GFX_PG; 868 adev->external_rev_id = adev->rev_id + 0xF; 869 break; 870 case IP_VERSION(11, 7, 1): 871 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 872 AMD_CG_SUPPORT_JPEG_MGCG | 873 AMD_CG_SUPPORT_GFX_CGCG | 874 AMD_CG_SUPPORT_GFX_CGLS | 875 AMD_CG_SUPPORT_GFX_MGCG | 876 AMD_CG_SUPPORT_GFX_FGCG | 877 AMD_CG_SUPPORT_REPEATER_FGCG | 878 AMD_CG_SUPPORT_GFX_PERF_CLK | 879 AMD_CG_SUPPORT_GFX_3D_CGCG | 880 AMD_CG_SUPPORT_GFX_3D_CGLS | 881 AMD_CG_SUPPORT_MC_MGCG | 882 AMD_CG_SUPPORT_MC_LS | 883 AMD_CG_SUPPORT_HDP_LS | 884 AMD_CG_SUPPORT_HDP_DS | 885 AMD_CG_SUPPORT_HDP_SD | 886 AMD_CG_SUPPORT_ATHUB_MGCG | 887 AMD_CG_SUPPORT_ATHUB_LS | 888 AMD_CG_SUPPORT_IH_CG | 889 AMD_CG_SUPPORT_BIF_MGCG | 890 AMD_CG_SUPPORT_BIF_LS; 891 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 892 AMD_PG_SUPPORT_VCN | 893 AMD_PG_SUPPORT_JPEG | 894 AMD_PG_SUPPORT_GFX_PG; 895 adev->external_rev_id = adev->rev_id + 0x40; 896 break; 897 default: 898 /* FIXME: not supported yet */ 899 return -EINVAL; 900 } 901 902 if (amdgpu_sriov_vf(adev)) { 903 amdgpu_virt_init_setting(adev); 904 xgpu_nv_mailbox_set_irq_funcs(adev); 905 } 906 907 return 0; 908 } 909 910 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) 911 { 912 struct amdgpu_device *adev = ip_block->adev; 913 914 if (amdgpu_sriov_vf(adev)) { 915 xgpu_nv_mailbox_get_irq(adev); 916 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 917 !amdgpu_sriov_is_av1_support(adev)) { 918 amdgpu_virt_update_sriov_video_codec(adev, 919 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 920 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 921 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 922 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 923 } else { 924 amdgpu_virt_update_sriov_video_codec(adev, 925 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 926 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 927 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 928 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 929 } 930 } else { 931 if (adev->nbio.ras && 932 adev->nbio.ras_err_event_athub_irq.funcs) 933 /* don't need to fail gpu late init 934 * if enabling athub_err_event interrupt failed 935 * nbio v4_3 only support fatal error hanlding 936 * just enable the interrupt directly */ 937 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 938 } 939 940 /* Enable selfring doorbell aperture late because doorbell BAR 941 * aperture will change if resize BAR successfully in gmc sw_init. 942 */ 943 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 944 945 return 0; 946 } 947 948 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) 949 { 950 struct amdgpu_device *adev = ip_block->adev; 951 952 if (amdgpu_sriov_vf(adev)) 953 xgpu_nv_mailbox_add_irq_id(adev); 954 955 return 0; 956 } 957 958 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) 959 { 960 struct amdgpu_device *adev = ip_block->adev; 961 962 /* enable aspm */ 963 amdgpu_nbio_program_aspm(adev); 964 /* setup nbio registers */ 965 adev->nbio.funcs->init_registers(adev); 966 /* remap HDP registers to a hole in mmio space, 967 * for the purpose of expose those registers 968 * to process space 969 */ 970 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 971 adev->nbio.funcs->remap_hdp_registers(adev); 972 /* enable the doorbell aperture */ 973 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 974 975 return 0; 976 } 977 978 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) 979 { 980 struct amdgpu_device *adev = ip_block->adev; 981 982 /* Disable the doorbell aperture and selfring doorbell aperture 983 * separately in hw_fini because soc21_enable_doorbell_aperture 984 * has been removed and there is no need to delay disabling 985 * selfring doorbell. 986 */ 987 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 988 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 989 990 if (amdgpu_sriov_vf(adev)) { 991 xgpu_nv_mailbox_put_irq(adev); 992 } else { 993 if (adev->nbio.ras && 994 adev->nbio.ras_err_event_athub_irq.funcs) 995 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 996 } 997 998 return 0; 999 } 1000 1001 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) 1002 { 1003 return soc21_common_hw_fini(ip_block); 1004 } 1005 1006 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 1007 { 1008 u32 sol_reg1, sol_reg2; 1009 1010 /* Will reset for the following suspend abort cases. 1011 * 1) Only reset dGPU side. 1012 * 2) S3 suspend got aborted and TOS is active. 1013 * As for dGPU suspend abort cases the SOL value 1014 * will be kept as zero at this resume point. 1015 */ 1016 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 1017 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1018 msleep(100); 1019 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 1020 1021 return (sol_reg1 != sol_reg2); 1022 } 1023 1024 return false; 1025 } 1026 1027 static int soc21_common_resume(struct amdgpu_ip_block *ip_block) 1028 { 1029 struct amdgpu_device *adev = ip_block->adev; 1030 1031 if (soc21_need_reset_on_resume(adev)) { 1032 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 1033 soc21_asic_reset(adev); 1034 } 1035 1036 return soc21_common_hw_init(ip_block); 1037 } 1038 1039 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block) 1040 { 1041 return true; 1042 } 1043 1044 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1045 enum amd_clockgating_state state) 1046 { 1047 struct amdgpu_device *adev = ip_block->adev; 1048 1049 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1050 case IP_VERSION(4, 3, 0): 1051 case IP_VERSION(4, 3, 1): 1052 case IP_VERSION(7, 7, 0): 1053 case IP_VERSION(7, 7, 1): 1054 case IP_VERSION(7, 11, 0): 1055 case IP_VERSION(7, 11, 1): 1056 case IP_VERSION(7, 11, 2): 1057 case IP_VERSION(7, 11, 3): 1058 case IP_VERSION(7, 11, 4): 1059 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1060 state == AMD_CG_STATE_GATE); 1061 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1062 state == AMD_CG_STATE_GATE); 1063 adev->hdp.funcs->update_clock_gating(adev, 1064 state == AMD_CG_STATE_GATE); 1065 break; 1066 default: 1067 break; 1068 } 1069 return 0; 1070 } 1071 1072 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1073 enum amd_powergating_state state) 1074 { 1075 struct amdgpu_device *adev = ip_block->adev; 1076 1077 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 1078 case IP_VERSION(6, 0, 0): 1079 case IP_VERSION(6, 0, 2): 1080 adev->lsdma.funcs->update_memory_power_gating(adev, 1081 state == AMD_PG_STATE_GATE); 1082 break; 1083 default: 1084 break; 1085 } 1086 1087 return 0; 1088 } 1089 1090 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1091 { 1092 struct amdgpu_device *adev = ip_block->adev; 1093 1094 adev->nbio.funcs->get_clockgating_state(adev, flags); 1095 1096 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1097 } 1098 1099 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1100 .name = "soc21_common", 1101 .early_init = soc21_common_early_init, 1102 .late_init = soc21_common_late_init, 1103 .sw_init = soc21_common_sw_init, 1104 .hw_init = soc21_common_hw_init, 1105 .hw_fini = soc21_common_hw_fini, 1106 .suspend = soc21_common_suspend, 1107 .resume = soc21_common_resume, 1108 .is_idle = soc21_common_is_idle, 1109 .set_clockgating_state = soc21_common_set_clockgating_state, 1110 .set_powergating_state = soc21_common_set_powergating_state, 1111 .get_clockgating_state = soc21_common_get_clockgating_state, 1112 }; 1113