1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 137 }; 138 139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 142 }; 143 144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { 151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), 152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { 164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), 165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, 166 }; 167 168 169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 170 const struct amdgpu_video_codecs **codecs) 171 { 172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 173 return -EINVAL; 174 175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 176 case IP_VERSION(4, 0, 0): 177 case IP_VERSION(4, 0, 2): 178 case IP_VERSION(4, 0, 4): 179 case IP_VERSION(4, 0, 5): 180 if (amdgpu_sriov_vf(adev)) { 181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 182 !amdgpu_sriov_is_av1_support(adev)) { 183 if (encode) 184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } else { 194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 195 if (encode) 196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 197 else 198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 199 } else { 200 if (encode) 201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 202 else 203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 204 } 205 } 206 return 0; 207 case IP_VERSION(4, 0, 6): 208 if (encode) 209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 210 else 211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 212 return 0; 213 case IP_VERSION(5, 3, 0): 214 if (encode) 215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; 216 else 217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags, address, data; 227 u32 r; 228 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 232 spin_lock_irqsave(&adev->reg.didt.lock, flags); 233 WREG32(address, (reg)); 234 r = RREG32(data); 235 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 236 return r; 237 } 238 239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 240 { 241 unsigned long flags, address, data; 242 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 246 spin_lock_irqsave(&adev->reg.didt.lock, flags); 247 WREG32(address, (reg)); 248 WREG32(data, (v)); 249 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 250 } 251 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 253 { 254 return adev->nbio.funcs->get_memsize(adev); 255 } 256 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 { 259 u32 reference_clock = adev->clock.spll.reference_freq; 260 261 /* reference clock is actually 99.81 Mhz rather than 100 Mhz */ 262 if ((adev->flags & AMD_IS_APU) && reference_clock == 10000) 263 return 9981; 264 265 return reference_clock; 266 } 267 268 269 void soc21_grbm_select(struct amdgpu_device *adev, 270 u32 me, u32 pipe, u32 queue, u32 vmid) 271 { 272 u32 grbm_gfx_cntl = 0; 273 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 274 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 275 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 276 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 277 278 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 279 } 280 281 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 282 { 283 /* todo */ 284 return false; 285 } 286 287 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 288 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 289 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 290 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 291 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 292 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 293 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 295 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 296 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 297 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 298 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 299 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 300 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 301 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 302 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 303 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 304 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 305 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 306 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 307 }; 308 309 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 310 bool indexed, u32 se_num, 311 u32 sh_num, u32 reg_offset) 312 { 313 if (indexed) { 314 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 315 } else { 316 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 317 return adev->gfx.config.gb_addr_config; 318 return RREG32(reg_offset); 319 } 320 } 321 322 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 323 u32 sh_num, u32 reg_offset, u32 *value) 324 { 325 uint32_t i; 326 struct soc15_allowed_register_entry *en; 327 328 *value = 0; 329 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 330 en = &soc21_allowed_read_registers[i]; 331 if (!adev->reg_offset[en->hwip][en->inst]) 332 continue; 333 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 334 + en->reg_offset)) 335 continue; 336 337 *value = soc21_get_register_value(adev, 338 soc21_allowed_read_registers[i].grbm_indexed, 339 se_num, sh_num, reg_offset); 340 return 0; 341 } 342 return -EINVAL; 343 } 344 345 #if 0 346 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 347 { 348 u32 i; 349 int ret = 0; 350 351 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 352 353 /* disable BM */ 354 pci_clear_master(adev->pdev); 355 356 amdgpu_device_cache_pci_state(adev->pdev); 357 358 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 359 dev_info(adev->dev, "GPU smu mode1 reset\n"); 360 ret = amdgpu_dpm_mode1_reset(adev); 361 } else { 362 dev_info(adev->dev, "GPU psp mode1 reset\n"); 363 ret = psp_gpu_reset(adev); 364 } 365 366 if (ret) 367 dev_err(adev->dev, "GPU mode1 reset failed\n"); 368 amdgpu_device_load_pci_state(adev->pdev); 369 370 /* wait for asic to come out of reset */ 371 for (i = 0; i < adev->usec_timeout; i++) { 372 u32 memsize = adev->nbio.funcs->get_memsize(adev); 373 374 if (memsize != 0xffffffff) 375 break; 376 udelay(1); 377 } 378 379 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 380 381 return ret; 382 } 383 #endif 384 385 static enum amd_reset_method 386 soc21_asic_reset_method(struct amdgpu_device *adev) 387 { 388 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 389 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 390 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 391 return amdgpu_reset_method; 392 393 if (amdgpu_reset_method != -1) 394 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 395 amdgpu_reset_method); 396 397 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 398 case IP_VERSION(13, 0, 0): 399 case IP_VERSION(13, 0, 7): 400 case IP_VERSION(13, 0, 10): 401 return AMD_RESET_METHOD_MODE1; 402 case IP_VERSION(13, 0, 4): 403 case IP_VERSION(13, 0, 11): 404 case IP_VERSION(14, 0, 0): 405 case IP_VERSION(14, 0, 1): 406 case IP_VERSION(14, 0, 4): 407 case IP_VERSION(14, 0, 5): 408 case IP_VERSION(15, 0, 0): 409 return AMD_RESET_METHOD_MODE2; 410 default: 411 if (amdgpu_dpm_is_baco_supported(adev)) 412 return AMD_RESET_METHOD_BACO; 413 else 414 return AMD_RESET_METHOD_MODE1; 415 } 416 } 417 418 static int soc21_asic_reset(struct amdgpu_device *adev) 419 { 420 int ret = 0; 421 422 switch (soc21_asic_reset_method(adev)) { 423 case AMD_RESET_METHOD_PCI: 424 dev_info(adev->dev, "PCI reset\n"); 425 ret = amdgpu_device_pci_reset(adev); 426 break; 427 case AMD_RESET_METHOD_BACO: 428 dev_info(adev->dev, "BACO reset\n"); 429 ret = amdgpu_dpm_baco_reset(adev); 430 break; 431 case AMD_RESET_METHOD_MODE2: 432 dev_info(adev->dev, "MODE2 reset\n"); 433 ret = amdgpu_dpm_mode2_reset(adev); 434 break; 435 default: 436 dev_info(adev->dev, "MODE1 reset\n"); 437 ret = amdgpu_device_mode1_reset(adev); 438 break; 439 } 440 441 return ret; 442 } 443 444 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 445 { 446 /* todo */ 447 return 0; 448 } 449 450 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 451 { 452 /* todo */ 453 return 0; 454 } 455 456 const struct amdgpu_ip_block_version soc21_common_ip_block = { 457 .type = AMD_IP_BLOCK_TYPE_COMMON, 458 .major = 1, 459 .minor = 0, 460 .rev = 0, 461 .funcs = &soc21_common_ip_funcs, 462 }; 463 464 static bool soc21_need_full_reset(struct amdgpu_device *adev) 465 { 466 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 467 case IP_VERSION(11, 0, 0): 468 case IP_VERSION(11, 0, 2): 469 case IP_VERSION(11, 0, 3): 470 default: 471 return true; 472 } 473 } 474 475 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 476 { 477 u32 sol_reg; 478 479 if (adev->flags & AMD_IS_APU) 480 return false; 481 482 /* Check sOS sign of life register to confirm sys driver and sOS 483 * are already been loaded. 484 */ 485 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 486 if (sol_reg) 487 return true; 488 489 return false; 490 } 491 492 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 493 { 494 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 495 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 496 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 497 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 498 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 499 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 500 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 501 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 502 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 503 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 504 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 505 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 506 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 507 adev->doorbell_index.gfx_userqueue_start = 508 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 509 adev->doorbell_index.gfx_userqueue_end = 510 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 511 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 512 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 513 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 514 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 515 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 516 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 517 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 518 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 519 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 520 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 521 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 522 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 523 524 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 525 adev->doorbell_index.sdma_doorbell_range = 20; 526 } 527 528 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 529 bool enter) 530 { 531 if (enter) 532 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 533 else 534 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 535 536 if (adev->gfx.funcs->update_perfmon_mgcg) 537 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 538 539 return 0; 540 } 541 542 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 543 .read_disabled_bios = &soc21_read_disabled_bios, 544 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 545 .read_register = &soc21_read_register, 546 .reset = &soc21_asic_reset, 547 .reset_method = &soc21_asic_reset_method, 548 .get_xclk = &soc21_get_xclk, 549 .set_uvd_clocks = &soc21_set_uvd_clocks, 550 .set_vce_clocks = &soc21_set_vce_clocks, 551 .get_config_memsize = &soc21_get_config_memsize, 552 .init_doorbell_index = &soc21_init_doorbell_index, 553 .need_full_reset = &soc21_need_full_reset, 554 .need_reset_on_init = &soc21_need_reset_on_init, 555 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 556 .supports_baco = &amdgpu_dpm_is_baco_supported, 557 .query_video_codecs = &soc21_query_video_codecs, 558 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 559 }; 560 561 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) 562 { 563 struct amdgpu_device *adev = ip_block->adev; 564 565 adev->nbio.funcs->set_reg_remap(adev); 566 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 567 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 568 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 569 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 570 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 571 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 572 573 adev->reg.didt.rreg = &soc21_didt_rreg; 574 adev->reg.didt.wreg = &soc21_didt_wreg; 575 576 adev->asic_funcs = &soc21_asic_funcs; 577 578 adev->rev_id = amdgpu_device_get_rev_id(adev); 579 adev->external_rev_id = 0xff; 580 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 581 case IP_VERSION(11, 0, 0): 582 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 583 AMD_CG_SUPPORT_GFX_CGLS | 584 #if 0 585 AMD_CG_SUPPORT_GFX_3D_CGCG | 586 AMD_CG_SUPPORT_GFX_3D_CGLS | 587 #endif 588 AMD_CG_SUPPORT_GFX_MGCG | 589 AMD_CG_SUPPORT_REPEATER_FGCG | 590 AMD_CG_SUPPORT_GFX_FGCG | 591 AMD_CG_SUPPORT_GFX_PERF_CLK | 592 AMD_CG_SUPPORT_VCN_MGCG | 593 AMD_CG_SUPPORT_JPEG_MGCG | 594 AMD_CG_SUPPORT_ATHUB_MGCG | 595 AMD_CG_SUPPORT_ATHUB_LS | 596 AMD_CG_SUPPORT_MC_MGCG | 597 AMD_CG_SUPPORT_MC_LS | 598 AMD_CG_SUPPORT_IH_CG | 599 AMD_CG_SUPPORT_HDP_SD; 600 adev->pg_flags = AMD_PG_SUPPORT_VCN | 601 AMD_PG_SUPPORT_VCN_DPG | 602 AMD_PG_SUPPORT_JPEG | 603 AMD_PG_SUPPORT_ATHUB | 604 AMD_PG_SUPPORT_MMHUB; 605 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 606 break; 607 case IP_VERSION(11, 0, 2): 608 adev->cg_flags = 609 AMD_CG_SUPPORT_GFX_CGCG | 610 AMD_CG_SUPPORT_GFX_CGLS | 611 AMD_CG_SUPPORT_REPEATER_FGCG | 612 AMD_CG_SUPPORT_VCN_MGCG | 613 AMD_CG_SUPPORT_JPEG_MGCG | 614 AMD_CG_SUPPORT_ATHUB_MGCG | 615 AMD_CG_SUPPORT_ATHUB_LS | 616 AMD_CG_SUPPORT_IH_CG | 617 AMD_CG_SUPPORT_HDP_SD; 618 adev->pg_flags = 619 AMD_PG_SUPPORT_VCN | 620 AMD_PG_SUPPORT_VCN_DPG | 621 AMD_PG_SUPPORT_JPEG | 622 AMD_PG_SUPPORT_ATHUB | 623 AMD_PG_SUPPORT_MMHUB; 624 adev->external_rev_id = adev->rev_id + 0x10; 625 break; 626 case IP_VERSION(11, 0, 1): 627 adev->cg_flags = 628 AMD_CG_SUPPORT_GFX_CGCG | 629 AMD_CG_SUPPORT_GFX_CGLS | 630 AMD_CG_SUPPORT_GFX_MGCG | 631 AMD_CG_SUPPORT_GFX_FGCG | 632 AMD_CG_SUPPORT_REPEATER_FGCG | 633 AMD_CG_SUPPORT_GFX_PERF_CLK | 634 AMD_CG_SUPPORT_MC_MGCG | 635 AMD_CG_SUPPORT_MC_LS | 636 AMD_CG_SUPPORT_HDP_MGCG | 637 AMD_CG_SUPPORT_HDP_LS | 638 AMD_CG_SUPPORT_ATHUB_MGCG | 639 AMD_CG_SUPPORT_ATHUB_LS | 640 AMD_CG_SUPPORT_IH_CG | 641 AMD_CG_SUPPORT_BIF_MGCG | 642 AMD_CG_SUPPORT_BIF_LS | 643 AMD_CG_SUPPORT_VCN_MGCG | 644 AMD_CG_SUPPORT_JPEG_MGCG; 645 adev->pg_flags = 646 AMD_PG_SUPPORT_GFX_PG | 647 AMD_PG_SUPPORT_VCN | 648 AMD_PG_SUPPORT_VCN_DPG | 649 AMD_PG_SUPPORT_JPEG; 650 adev->external_rev_id = adev->rev_id + 0x1; 651 break; 652 case IP_VERSION(11, 0, 3): 653 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 654 AMD_CG_SUPPORT_JPEG_MGCG | 655 AMD_CG_SUPPORT_GFX_CGCG | 656 AMD_CG_SUPPORT_GFX_CGLS | 657 AMD_CG_SUPPORT_REPEATER_FGCG | 658 AMD_CG_SUPPORT_GFX_MGCG | 659 AMD_CG_SUPPORT_HDP_SD | 660 AMD_CG_SUPPORT_ATHUB_MGCG | 661 AMD_CG_SUPPORT_ATHUB_LS; 662 adev->pg_flags = AMD_PG_SUPPORT_VCN | 663 AMD_PG_SUPPORT_VCN_DPG | 664 AMD_PG_SUPPORT_JPEG; 665 adev->external_rev_id = adev->rev_id + 0x20; 666 break; 667 case IP_VERSION(11, 0, 4): 668 adev->cg_flags = 669 AMD_CG_SUPPORT_GFX_CGCG | 670 AMD_CG_SUPPORT_GFX_CGLS | 671 AMD_CG_SUPPORT_GFX_MGCG | 672 AMD_CG_SUPPORT_GFX_FGCG | 673 AMD_CG_SUPPORT_REPEATER_FGCG | 674 AMD_CG_SUPPORT_GFX_PERF_CLK | 675 AMD_CG_SUPPORT_MC_MGCG | 676 AMD_CG_SUPPORT_MC_LS | 677 AMD_CG_SUPPORT_HDP_MGCG | 678 AMD_CG_SUPPORT_HDP_LS | 679 AMD_CG_SUPPORT_ATHUB_MGCG | 680 AMD_CG_SUPPORT_ATHUB_LS | 681 AMD_CG_SUPPORT_IH_CG | 682 AMD_CG_SUPPORT_BIF_MGCG | 683 AMD_CG_SUPPORT_BIF_LS | 684 AMD_CG_SUPPORT_VCN_MGCG | 685 AMD_CG_SUPPORT_JPEG_MGCG; 686 adev->pg_flags = AMD_PG_SUPPORT_VCN | 687 AMD_PG_SUPPORT_VCN_DPG | 688 AMD_PG_SUPPORT_GFX_PG | 689 AMD_PG_SUPPORT_JPEG; 690 adev->external_rev_id = adev->rev_id + 0x80; 691 break; 692 case IP_VERSION(11, 5, 0): 693 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 694 AMD_CG_SUPPORT_JPEG_MGCG | 695 AMD_CG_SUPPORT_GFX_CGCG | 696 AMD_CG_SUPPORT_GFX_CGLS | 697 AMD_CG_SUPPORT_GFX_MGCG | 698 AMD_CG_SUPPORT_GFX_FGCG | 699 AMD_CG_SUPPORT_REPEATER_FGCG | 700 AMD_CG_SUPPORT_GFX_PERF_CLK | 701 AMD_CG_SUPPORT_GFX_3D_CGCG | 702 AMD_CG_SUPPORT_GFX_3D_CGLS | 703 AMD_CG_SUPPORT_MC_MGCG | 704 AMD_CG_SUPPORT_MC_LS | 705 AMD_CG_SUPPORT_HDP_LS | 706 AMD_CG_SUPPORT_HDP_DS | 707 AMD_CG_SUPPORT_HDP_SD | 708 AMD_CG_SUPPORT_ATHUB_MGCG | 709 AMD_CG_SUPPORT_ATHUB_LS | 710 AMD_CG_SUPPORT_IH_CG | 711 AMD_CG_SUPPORT_BIF_MGCG | 712 AMD_CG_SUPPORT_BIF_LS; 713 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 714 AMD_PG_SUPPORT_JPEG_DPG | 715 AMD_PG_SUPPORT_VCN | 716 AMD_PG_SUPPORT_JPEG | 717 AMD_PG_SUPPORT_GFX_PG; 718 if (adev->rev_id == 0) 719 adev->external_rev_id = 0x1; 720 else 721 adev->external_rev_id = adev->rev_id + 0x10; 722 break; 723 case IP_VERSION(11, 5, 1): 724 adev->cg_flags = 725 AMD_CG_SUPPORT_GFX_CGCG | 726 AMD_CG_SUPPORT_GFX_CGLS | 727 AMD_CG_SUPPORT_GFX_MGCG | 728 AMD_CG_SUPPORT_GFX_FGCG | 729 AMD_CG_SUPPORT_REPEATER_FGCG | 730 AMD_CG_SUPPORT_GFX_PERF_CLK | 731 AMD_CG_SUPPORT_GFX_3D_CGCG | 732 AMD_CG_SUPPORT_GFX_3D_CGLS | 733 AMD_CG_SUPPORT_MC_MGCG | 734 AMD_CG_SUPPORT_MC_LS | 735 AMD_CG_SUPPORT_HDP_LS | 736 AMD_CG_SUPPORT_HDP_DS | 737 AMD_CG_SUPPORT_HDP_SD | 738 AMD_CG_SUPPORT_ATHUB_MGCG | 739 AMD_CG_SUPPORT_ATHUB_LS | 740 AMD_CG_SUPPORT_IH_CG | 741 AMD_CG_SUPPORT_BIF_MGCG | 742 AMD_CG_SUPPORT_BIF_LS | 743 AMD_CG_SUPPORT_VCN_MGCG | 744 AMD_CG_SUPPORT_JPEG_MGCG; 745 adev->pg_flags = 746 AMD_PG_SUPPORT_GFX_PG | 747 AMD_PG_SUPPORT_VCN | 748 AMD_PG_SUPPORT_VCN_DPG | 749 AMD_PG_SUPPORT_JPEG; 750 adev->external_rev_id = adev->rev_id + 0xc1; 751 break; 752 case IP_VERSION(11, 5, 2): 753 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 754 AMD_CG_SUPPORT_JPEG_MGCG | 755 AMD_CG_SUPPORT_GFX_CGCG | 756 AMD_CG_SUPPORT_GFX_CGLS | 757 AMD_CG_SUPPORT_GFX_MGCG | 758 AMD_CG_SUPPORT_GFX_FGCG | 759 AMD_CG_SUPPORT_REPEATER_FGCG | 760 AMD_CG_SUPPORT_GFX_PERF_CLK | 761 AMD_CG_SUPPORT_GFX_3D_CGCG | 762 AMD_CG_SUPPORT_GFX_3D_CGLS | 763 AMD_CG_SUPPORT_MC_MGCG | 764 AMD_CG_SUPPORT_MC_LS | 765 AMD_CG_SUPPORT_HDP_LS | 766 AMD_CG_SUPPORT_HDP_DS | 767 AMD_CG_SUPPORT_HDP_SD | 768 AMD_CG_SUPPORT_ATHUB_MGCG | 769 AMD_CG_SUPPORT_ATHUB_LS | 770 AMD_CG_SUPPORT_IH_CG | 771 AMD_CG_SUPPORT_BIF_MGCG | 772 AMD_CG_SUPPORT_BIF_LS; 773 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 774 AMD_PG_SUPPORT_VCN | 775 AMD_PG_SUPPORT_JPEG_DPG | 776 AMD_PG_SUPPORT_JPEG | 777 AMD_PG_SUPPORT_GFX_PG; 778 adev->external_rev_id = adev->rev_id + 0x40; 779 break; 780 case IP_VERSION(11, 5, 3): 781 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 782 AMD_CG_SUPPORT_JPEG_MGCG | 783 AMD_CG_SUPPORT_GFX_CGCG | 784 AMD_CG_SUPPORT_GFX_CGLS | 785 AMD_CG_SUPPORT_GFX_MGCG | 786 AMD_CG_SUPPORT_GFX_FGCG | 787 AMD_CG_SUPPORT_REPEATER_FGCG | 788 AMD_CG_SUPPORT_GFX_PERF_CLK | 789 AMD_CG_SUPPORT_GFX_3D_CGCG | 790 AMD_CG_SUPPORT_GFX_3D_CGLS | 791 AMD_CG_SUPPORT_MC_MGCG | 792 AMD_CG_SUPPORT_MC_LS | 793 AMD_CG_SUPPORT_HDP_LS | 794 AMD_CG_SUPPORT_HDP_DS | 795 AMD_CG_SUPPORT_HDP_SD | 796 AMD_CG_SUPPORT_ATHUB_MGCG | 797 AMD_CG_SUPPORT_ATHUB_LS | 798 AMD_CG_SUPPORT_IH_CG | 799 AMD_CG_SUPPORT_BIF_MGCG | 800 AMD_CG_SUPPORT_BIF_LS; 801 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 802 AMD_PG_SUPPORT_VCN | 803 AMD_PG_SUPPORT_JPEG_DPG | 804 AMD_PG_SUPPORT_JPEG | 805 AMD_PG_SUPPORT_GFX_PG; 806 adev->external_rev_id = adev->rev_id + 0x50; 807 break; 808 case IP_VERSION(11, 5, 4): 809 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 810 AMD_CG_SUPPORT_JPEG_MGCG | 811 AMD_CG_SUPPORT_GFX_CGCG | 812 AMD_CG_SUPPORT_GFX_CGLS | 813 AMD_CG_SUPPORT_GFX_MGCG | 814 AMD_CG_SUPPORT_GFX_FGCG | 815 AMD_CG_SUPPORT_REPEATER_FGCG | 816 AMD_CG_SUPPORT_GFX_PERF_CLK | 817 AMD_CG_SUPPORT_GFX_3D_CGCG | 818 AMD_CG_SUPPORT_GFX_3D_CGLS | 819 AMD_CG_SUPPORT_MC_MGCG | 820 AMD_CG_SUPPORT_MC_LS | 821 AMD_CG_SUPPORT_HDP_LS | 822 AMD_CG_SUPPORT_HDP_DS | 823 AMD_CG_SUPPORT_HDP_SD | 824 AMD_CG_SUPPORT_ATHUB_MGCG | 825 AMD_CG_SUPPORT_ATHUB_LS | 826 AMD_CG_SUPPORT_IH_CG | 827 AMD_CG_SUPPORT_BIF_MGCG | 828 AMD_CG_SUPPORT_BIF_LS; 829 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 830 AMD_PG_SUPPORT_VCN | 831 AMD_PG_SUPPORT_JPEG_DPG | 832 AMD_PG_SUPPORT_JPEG | 833 AMD_PG_SUPPORT_GFX_PG; 834 adev->external_rev_id = adev->rev_id + 0x1; 835 break; 836 default: 837 /* FIXME: not supported yet */ 838 return -EINVAL; 839 } 840 841 if (amdgpu_sriov_vf(adev)) { 842 amdgpu_virt_init_setting(adev); 843 xgpu_nv_mailbox_set_irq_funcs(adev); 844 } 845 846 return 0; 847 } 848 849 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) 850 { 851 struct amdgpu_device *adev = ip_block->adev; 852 853 if (amdgpu_sriov_vf(adev)) { 854 xgpu_nv_mailbox_get_irq(adev); 855 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 856 !amdgpu_sriov_is_av1_support(adev)) { 857 amdgpu_virt_update_sriov_video_codec(adev, 858 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 859 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 860 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 861 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 862 } else { 863 amdgpu_virt_update_sriov_video_codec(adev, 864 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 865 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 866 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 867 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 868 } 869 } else { 870 if (adev->nbio.ras && 871 adev->nbio.ras_err_event_athub_irq.funcs) 872 /* don't need to fail gpu late init 873 * if enabling athub_err_event interrupt failed 874 * nbio v4_3 only support fatal error hanlding 875 * just enable the interrupt directly */ 876 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 877 } 878 879 /* Enable selfring doorbell aperture late because doorbell BAR 880 * aperture will change if resize BAR successfully in gmc sw_init. 881 */ 882 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 883 884 return 0; 885 } 886 887 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) 888 { 889 struct amdgpu_device *adev = ip_block->adev; 890 891 if (amdgpu_sriov_vf(adev)) 892 xgpu_nv_mailbox_add_irq_id(adev); 893 894 return 0; 895 } 896 897 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) 898 { 899 struct amdgpu_device *adev = ip_block->adev; 900 901 /* enable aspm */ 902 amdgpu_nbio_program_aspm(adev); 903 /* setup nbio registers */ 904 adev->nbio.funcs->init_registers(adev); 905 /* remap HDP registers to a hole in mmio space, 906 * for the purpose of expose those registers 907 * to process space 908 */ 909 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 910 adev->nbio.funcs->remap_hdp_registers(adev); 911 /* enable the doorbell aperture */ 912 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 913 914 return 0; 915 } 916 917 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) 918 { 919 struct amdgpu_device *adev = ip_block->adev; 920 921 /* Disable the doorbell aperture and selfring doorbell aperture 922 * separately in hw_fini because soc21_enable_doorbell_aperture 923 * has been removed and there is no need to delay disabling 924 * selfring doorbell. 925 */ 926 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 927 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 928 929 if (amdgpu_sriov_vf(adev)) { 930 xgpu_nv_mailbox_put_irq(adev); 931 } else { 932 if (adev->nbio.ras && 933 adev->nbio.ras_err_event_athub_irq.funcs) 934 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 935 } 936 937 return 0; 938 } 939 940 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) 941 { 942 return soc21_common_hw_fini(ip_block); 943 } 944 945 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 946 { 947 u32 sol_reg1, sol_reg2; 948 949 /* Will reset for the following suspend abort cases. 950 * 1) Only reset dGPU side. 951 * 2) S3 suspend got aborted and TOS is active. 952 * As for dGPU suspend abort cases the SOL value 953 * will be kept as zero at this resume point. 954 */ 955 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 956 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 957 msleep(100); 958 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 959 960 return (sol_reg1 != sol_reg2); 961 } 962 963 return false; 964 } 965 966 static int soc21_common_resume(struct amdgpu_ip_block *ip_block) 967 { 968 struct amdgpu_device *adev = ip_block->adev; 969 970 if (soc21_need_reset_on_resume(adev)) { 971 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 972 soc21_asic_reset(adev); 973 } 974 975 return soc21_common_hw_init(ip_block); 976 } 977 978 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block) 979 { 980 return true; 981 } 982 983 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 984 enum amd_clockgating_state state) 985 { 986 struct amdgpu_device *adev = ip_block->adev; 987 988 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 989 case IP_VERSION(4, 3, 0): 990 case IP_VERSION(4, 3, 1): 991 case IP_VERSION(7, 7, 0): 992 case IP_VERSION(7, 7, 1): 993 case IP_VERSION(7, 11, 0): 994 case IP_VERSION(7, 11, 1): 995 case IP_VERSION(7, 11, 2): 996 case IP_VERSION(7, 11, 3): 997 case IP_VERSION(7, 11, 4): 998 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 999 state == AMD_CG_STATE_GATE); 1000 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1001 state == AMD_CG_STATE_GATE); 1002 adev->hdp.funcs->update_clock_gating(adev, 1003 state == AMD_CG_STATE_GATE); 1004 break; 1005 default: 1006 break; 1007 } 1008 return 0; 1009 } 1010 1011 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1012 enum amd_powergating_state state) 1013 { 1014 struct amdgpu_device *adev = ip_block->adev; 1015 1016 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 1017 case IP_VERSION(6, 0, 0): 1018 case IP_VERSION(6, 0, 2): 1019 adev->lsdma.funcs->update_memory_power_gating(adev, 1020 state == AMD_PG_STATE_GATE); 1021 break; 1022 default: 1023 break; 1024 } 1025 1026 return 0; 1027 } 1028 1029 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1030 { 1031 struct amdgpu_device *adev = ip_block->adev; 1032 1033 adev->nbio.funcs->get_clockgating_state(adev, flags); 1034 1035 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1036 } 1037 1038 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1039 .name = "soc21_common", 1040 .early_init = soc21_common_early_init, 1041 .late_init = soc21_common_late_init, 1042 .sw_init = soc21_common_sw_init, 1043 .hw_init = soc21_common_hw_init, 1044 .hw_fini = soc21_common_hw_fini, 1045 .suspend = soc21_common_suspend, 1046 .resume = soc21_common_resume, 1047 .is_idle = soc21_common_is_idle, 1048 .set_clockgating_state = soc21_common_set_clockgating_state, 1049 .set_powergating_state = soc21_common_set_powergating_state, 1050 .get_clockgating_state = soc21_common_get_clockgating_state, 1051 }; 1052