1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 #include "mxgpu_nv.h" 47 48 static const struct amd_ip_funcs soc21_common_ip_funcs; 49 50 /* SOC21 */ 51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 55 }; 56 57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = { 63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 65 }; 66 67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = { 68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 70 }; 71 72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 78 }; 79 80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 85 }; 86 87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = { 88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 90 }; 91 92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 95 }; 96 97 /* SRIOV SOC21, not const since data is controlled by host */ 98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = { 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 102 }; 103 104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 107 }; 108 109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = { 110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 112 }; 113 114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = { 115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 117 }; 118 119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = { 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 125 }; 126 127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 132 }; 133 134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = { 135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0), 136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 137 }; 138 139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { 140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1), 141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 142 }; 143 144 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { 151 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), 152 .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { 164 .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), 165 .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, 166 }; 167 168 169 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 170 const struct amdgpu_video_codecs **codecs) 171 { 172 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 173 return -EINVAL; 174 175 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 176 case IP_VERSION(4, 0, 0): 177 case IP_VERSION(4, 0, 2): 178 case IP_VERSION(4, 0, 4): 179 case IP_VERSION(4, 0, 5): 180 if (amdgpu_sriov_vf(adev)) { 181 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 182 !amdgpu_sriov_is_av1_support(adev)) { 183 if (encode) 184 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1; 185 else 186 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1; 187 } else { 188 if (encode) 189 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0; 190 else 191 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0; 192 } 193 } else { 194 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) { 195 if (encode) 196 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 197 else 198 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 199 } else { 200 if (encode) 201 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 202 else 203 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 204 } 205 } 206 return 0; 207 case IP_VERSION(4, 0, 6): 208 if (encode) 209 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 210 else 211 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 212 return 0; 213 case IP_VERSION(5, 3, 0): 214 if (encode) 215 *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; 216 else 217 *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; 218 return 0; 219 default: 220 return -EINVAL; 221 } 222 } 223 224 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 225 { 226 unsigned long flags, address, data; 227 u32 r; 228 229 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 230 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 231 232 spin_lock_irqsave(&adev->didt_idx_lock, flags); 233 WREG32(address, (reg)); 234 r = RREG32(data); 235 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 236 return r; 237 } 238 239 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 240 { 241 unsigned long flags, address, data; 242 243 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 244 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 245 246 spin_lock_irqsave(&adev->didt_idx_lock, flags); 247 WREG32(address, (reg)); 248 WREG32(data, (v)); 249 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 250 } 251 252 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 253 { 254 return adev->nbio.funcs->get_memsize(adev); 255 } 256 257 static u32 soc21_get_xclk(struct amdgpu_device *adev) 258 { 259 return adev->clock.spll.reference_freq; 260 } 261 262 263 void soc21_grbm_select(struct amdgpu_device *adev, 264 u32 me, u32 pipe, u32 queue, u32 vmid) 265 { 266 u32 grbm_gfx_cntl = 0; 267 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 268 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 269 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 270 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 271 272 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 273 } 274 275 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 276 { 277 /* todo */ 278 return false; 279 } 280 281 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 282 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 283 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 284 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 285 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 286 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 287 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 288 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 289 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 290 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 291 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 292 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 293 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 294 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 295 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 296 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 297 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 298 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 299 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 300 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 301 }; 302 303 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 304 u32 sh_num, u32 reg_offset) 305 { 306 uint32_t val; 307 308 mutex_lock(&adev->grbm_idx_mutex); 309 if (se_num != 0xffffffff || sh_num != 0xffffffff) 310 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 311 312 val = RREG32(reg_offset); 313 314 if (se_num != 0xffffffff || sh_num != 0xffffffff) 315 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 316 mutex_unlock(&adev->grbm_idx_mutex); 317 return val; 318 } 319 320 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 321 bool indexed, u32 se_num, 322 u32 sh_num, u32 reg_offset) 323 { 324 if (indexed) { 325 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 326 } else { 327 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 328 return adev->gfx.config.gb_addr_config; 329 return RREG32(reg_offset); 330 } 331 } 332 333 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 334 u32 sh_num, u32 reg_offset, u32 *value) 335 { 336 uint32_t i; 337 struct soc15_allowed_register_entry *en; 338 339 *value = 0; 340 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 341 en = &soc21_allowed_read_registers[i]; 342 if (!adev->reg_offset[en->hwip][en->inst]) 343 continue; 344 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 345 + en->reg_offset)) 346 continue; 347 348 *value = soc21_get_register_value(adev, 349 soc21_allowed_read_registers[i].grbm_indexed, 350 se_num, sh_num, reg_offset); 351 return 0; 352 } 353 return -EINVAL; 354 } 355 356 #if 0 357 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 358 { 359 u32 i; 360 int ret = 0; 361 362 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 363 364 /* disable BM */ 365 pci_clear_master(adev->pdev); 366 367 amdgpu_device_cache_pci_state(adev->pdev); 368 369 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 370 dev_info(adev->dev, "GPU smu mode1 reset\n"); 371 ret = amdgpu_dpm_mode1_reset(adev); 372 } else { 373 dev_info(adev->dev, "GPU psp mode1 reset\n"); 374 ret = psp_gpu_reset(adev); 375 } 376 377 if (ret) 378 dev_err(adev->dev, "GPU mode1 reset failed\n"); 379 amdgpu_device_load_pci_state(adev->pdev); 380 381 /* wait for asic to come out of reset */ 382 for (i = 0; i < adev->usec_timeout; i++) { 383 u32 memsize = adev->nbio.funcs->get_memsize(adev); 384 385 if (memsize != 0xffffffff) 386 break; 387 udelay(1); 388 } 389 390 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 391 392 return ret; 393 } 394 #endif 395 396 static enum amd_reset_method 397 soc21_asic_reset_method(struct amdgpu_device *adev) 398 { 399 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 400 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 401 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 402 return amdgpu_reset_method; 403 404 if (amdgpu_reset_method != -1) 405 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 406 amdgpu_reset_method); 407 408 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 409 case IP_VERSION(13, 0, 0): 410 case IP_VERSION(13, 0, 7): 411 case IP_VERSION(13, 0, 10): 412 return AMD_RESET_METHOD_MODE1; 413 case IP_VERSION(13, 0, 4): 414 case IP_VERSION(13, 0, 11): 415 case IP_VERSION(14, 0, 0): 416 case IP_VERSION(14, 0, 1): 417 case IP_VERSION(14, 0, 4): 418 case IP_VERSION(14, 0, 5): 419 return AMD_RESET_METHOD_MODE2; 420 default: 421 if (amdgpu_dpm_is_baco_supported(adev)) 422 return AMD_RESET_METHOD_BACO; 423 else 424 return AMD_RESET_METHOD_MODE1; 425 } 426 } 427 428 static int soc21_asic_reset(struct amdgpu_device *adev) 429 { 430 int ret = 0; 431 432 switch (soc21_asic_reset_method(adev)) { 433 case AMD_RESET_METHOD_PCI: 434 dev_info(adev->dev, "PCI reset\n"); 435 ret = amdgpu_device_pci_reset(adev); 436 break; 437 case AMD_RESET_METHOD_BACO: 438 dev_info(adev->dev, "BACO reset\n"); 439 ret = amdgpu_dpm_baco_reset(adev); 440 break; 441 case AMD_RESET_METHOD_MODE2: 442 dev_info(adev->dev, "MODE2 reset\n"); 443 ret = amdgpu_dpm_mode2_reset(adev); 444 break; 445 default: 446 dev_info(adev->dev, "MODE1 reset\n"); 447 ret = amdgpu_device_mode1_reset(adev); 448 break; 449 } 450 451 return ret; 452 } 453 454 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 455 { 456 /* todo */ 457 return 0; 458 } 459 460 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 461 { 462 /* todo */ 463 return 0; 464 } 465 466 static void soc21_program_aspm(struct amdgpu_device *adev) 467 { 468 if (!amdgpu_device_should_use_aspm(adev)) 469 return; 470 471 if (adev->nbio.funcs->program_aspm) 472 adev->nbio.funcs->program_aspm(adev); 473 } 474 475 const struct amdgpu_ip_block_version soc21_common_ip_block = { 476 .type = AMD_IP_BLOCK_TYPE_COMMON, 477 .major = 1, 478 .minor = 0, 479 .rev = 0, 480 .funcs = &soc21_common_ip_funcs, 481 }; 482 483 static bool soc21_need_full_reset(struct amdgpu_device *adev) 484 { 485 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 486 case IP_VERSION(11, 0, 0): 487 case IP_VERSION(11, 0, 2): 488 case IP_VERSION(11, 0, 3): 489 default: 490 return true; 491 } 492 } 493 494 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 495 { 496 u32 sol_reg; 497 498 if (adev->flags & AMD_IS_APU) 499 return false; 500 501 /* Check sOS sign of life register to confirm sys driver and sOS 502 * are already been loaded. 503 */ 504 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 505 if (sol_reg) 506 return true; 507 508 return false; 509 } 510 511 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 512 { 513 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 514 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 515 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 516 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 517 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 518 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 519 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 520 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 521 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 522 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 523 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 524 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 525 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 526 adev->doorbell_index.gfx_userqueue_start = 527 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 528 adev->doorbell_index.gfx_userqueue_end = 529 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 530 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 531 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 532 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 533 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 534 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 535 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 536 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 537 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 538 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 539 adev->doorbell_index.vpe_ring = AMDGPU_NAVI10_DOORBELL64_VPE; 540 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 541 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 542 543 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 544 adev->doorbell_index.sdma_doorbell_range = 20; 545 } 546 547 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 548 bool enter) 549 { 550 if (enter) 551 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 552 else 553 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 554 555 if (adev->gfx.funcs->update_perfmon_mgcg) 556 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 557 558 return 0; 559 } 560 561 static const struct amdgpu_asic_funcs soc21_asic_funcs = { 562 .read_disabled_bios = &soc21_read_disabled_bios, 563 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 564 .read_register = &soc21_read_register, 565 .reset = &soc21_asic_reset, 566 .reset_method = &soc21_asic_reset_method, 567 .get_xclk = &soc21_get_xclk, 568 .set_uvd_clocks = &soc21_set_uvd_clocks, 569 .set_vce_clocks = &soc21_set_vce_clocks, 570 .get_config_memsize = &soc21_get_config_memsize, 571 .init_doorbell_index = &soc21_init_doorbell_index, 572 .need_full_reset = &soc21_need_full_reset, 573 .need_reset_on_init = &soc21_need_reset_on_init, 574 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 575 .supports_baco = &amdgpu_dpm_is_baco_supported, 576 .query_video_codecs = &soc21_query_video_codecs, 577 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 578 }; 579 580 static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) 581 { 582 struct amdgpu_device *adev = ip_block->adev; 583 584 adev->nbio.funcs->set_reg_remap(adev); 585 adev->smc_rreg = NULL; 586 adev->smc_wreg = NULL; 587 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 588 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 589 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 590 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 591 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 592 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 593 594 /* TODO: will add them during VCN v2 implementation */ 595 adev->uvd_ctx_rreg = NULL; 596 adev->uvd_ctx_wreg = NULL; 597 598 adev->didt_rreg = &soc21_didt_rreg; 599 adev->didt_wreg = &soc21_didt_wreg; 600 601 adev->asic_funcs = &soc21_asic_funcs; 602 603 adev->rev_id = amdgpu_device_get_rev_id(adev); 604 adev->external_rev_id = 0xff; 605 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 606 case IP_VERSION(11, 0, 0): 607 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 608 AMD_CG_SUPPORT_GFX_CGLS | 609 #if 0 610 AMD_CG_SUPPORT_GFX_3D_CGCG | 611 AMD_CG_SUPPORT_GFX_3D_CGLS | 612 #endif 613 AMD_CG_SUPPORT_GFX_MGCG | 614 AMD_CG_SUPPORT_REPEATER_FGCG | 615 AMD_CG_SUPPORT_GFX_FGCG | 616 AMD_CG_SUPPORT_GFX_PERF_CLK | 617 AMD_CG_SUPPORT_VCN_MGCG | 618 AMD_CG_SUPPORT_JPEG_MGCG | 619 AMD_CG_SUPPORT_ATHUB_MGCG | 620 AMD_CG_SUPPORT_ATHUB_LS | 621 AMD_CG_SUPPORT_MC_MGCG | 622 AMD_CG_SUPPORT_MC_LS | 623 AMD_CG_SUPPORT_IH_CG | 624 AMD_CG_SUPPORT_HDP_SD; 625 adev->pg_flags = AMD_PG_SUPPORT_VCN | 626 AMD_PG_SUPPORT_VCN_DPG | 627 AMD_PG_SUPPORT_JPEG | 628 AMD_PG_SUPPORT_ATHUB | 629 AMD_PG_SUPPORT_MMHUB; 630 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 631 break; 632 case IP_VERSION(11, 0, 2): 633 adev->cg_flags = 634 AMD_CG_SUPPORT_GFX_CGCG | 635 AMD_CG_SUPPORT_GFX_CGLS | 636 AMD_CG_SUPPORT_REPEATER_FGCG | 637 AMD_CG_SUPPORT_VCN_MGCG | 638 AMD_CG_SUPPORT_JPEG_MGCG | 639 AMD_CG_SUPPORT_ATHUB_MGCG | 640 AMD_CG_SUPPORT_ATHUB_LS | 641 AMD_CG_SUPPORT_IH_CG | 642 AMD_CG_SUPPORT_HDP_SD; 643 adev->pg_flags = 644 AMD_PG_SUPPORT_VCN | 645 AMD_PG_SUPPORT_VCN_DPG | 646 AMD_PG_SUPPORT_JPEG | 647 AMD_PG_SUPPORT_ATHUB | 648 AMD_PG_SUPPORT_MMHUB; 649 adev->external_rev_id = adev->rev_id + 0x10; 650 break; 651 case IP_VERSION(11, 0, 1): 652 adev->cg_flags = 653 AMD_CG_SUPPORT_GFX_CGCG | 654 AMD_CG_SUPPORT_GFX_CGLS | 655 AMD_CG_SUPPORT_GFX_MGCG | 656 AMD_CG_SUPPORT_GFX_FGCG | 657 AMD_CG_SUPPORT_REPEATER_FGCG | 658 AMD_CG_SUPPORT_GFX_PERF_CLK | 659 AMD_CG_SUPPORT_MC_MGCG | 660 AMD_CG_SUPPORT_MC_LS | 661 AMD_CG_SUPPORT_HDP_MGCG | 662 AMD_CG_SUPPORT_HDP_LS | 663 AMD_CG_SUPPORT_ATHUB_MGCG | 664 AMD_CG_SUPPORT_ATHUB_LS | 665 AMD_CG_SUPPORT_IH_CG | 666 AMD_CG_SUPPORT_BIF_MGCG | 667 AMD_CG_SUPPORT_BIF_LS | 668 AMD_CG_SUPPORT_VCN_MGCG | 669 AMD_CG_SUPPORT_JPEG_MGCG; 670 adev->pg_flags = 671 AMD_PG_SUPPORT_GFX_PG | 672 AMD_PG_SUPPORT_VCN | 673 AMD_PG_SUPPORT_VCN_DPG | 674 AMD_PG_SUPPORT_JPEG; 675 adev->external_rev_id = adev->rev_id + 0x1; 676 break; 677 case IP_VERSION(11, 0, 3): 678 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 679 AMD_CG_SUPPORT_JPEG_MGCG | 680 AMD_CG_SUPPORT_GFX_CGCG | 681 AMD_CG_SUPPORT_GFX_CGLS | 682 AMD_CG_SUPPORT_REPEATER_FGCG | 683 AMD_CG_SUPPORT_GFX_MGCG | 684 AMD_CG_SUPPORT_HDP_SD | 685 AMD_CG_SUPPORT_ATHUB_MGCG | 686 AMD_CG_SUPPORT_ATHUB_LS; 687 adev->pg_flags = AMD_PG_SUPPORT_VCN | 688 AMD_PG_SUPPORT_VCN_DPG | 689 AMD_PG_SUPPORT_JPEG; 690 adev->external_rev_id = adev->rev_id + 0x20; 691 break; 692 case IP_VERSION(11, 0, 4): 693 adev->cg_flags = 694 AMD_CG_SUPPORT_GFX_CGCG | 695 AMD_CG_SUPPORT_GFX_CGLS | 696 AMD_CG_SUPPORT_GFX_MGCG | 697 AMD_CG_SUPPORT_GFX_FGCG | 698 AMD_CG_SUPPORT_REPEATER_FGCG | 699 AMD_CG_SUPPORT_GFX_PERF_CLK | 700 AMD_CG_SUPPORT_MC_MGCG | 701 AMD_CG_SUPPORT_MC_LS | 702 AMD_CG_SUPPORT_HDP_MGCG | 703 AMD_CG_SUPPORT_HDP_LS | 704 AMD_CG_SUPPORT_ATHUB_MGCG | 705 AMD_CG_SUPPORT_ATHUB_LS | 706 AMD_CG_SUPPORT_IH_CG | 707 AMD_CG_SUPPORT_BIF_MGCG | 708 AMD_CG_SUPPORT_BIF_LS | 709 AMD_CG_SUPPORT_VCN_MGCG | 710 AMD_CG_SUPPORT_JPEG_MGCG; 711 adev->pg_flags = AMD_PG_SUPPORT_VCN | 712 AMD_PG_SUPPORT_VCN_DPG | 713 AMD_PG_SUPPORT_GFX_PG | 714 AMD_PG_SUPPORT_JPEG; 715 adev->external_rev_id = adev->rev_id + 0x80; 716 break; 717 case IP_VERSION(11, 5, 0): 718 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 719 AMD_CG_SUPPORT_JPEG_MGCG | 720 AMD_CG_SUPPORT_GFX_CGCG | 721 AMD_CG_SUPPORT_GFX_CGLS | 722 AMD_CG_SUPPORT_GFX_MGCG | 723 AMD_CG_SUPPORT_GFX_FGCG | 724 AMD_CG_SUPPORT_REPEATER_FGCG | 725 AMD_CG_SUPPORT_GFX_PERF_CLK | 726 AMD_CG_SUPPORT_GFX_3D_CGCG | 727 AMD_CG_SUPPORT_GFX_3D_CGLS | 728 AMD_CG_SUPPORT_MC_MGCG | 729 AMD_CG_SUPPORT_MC_LS | 730 AMD_CG_SUPPORT_HDP_LS | 731 AMD_CG_SUPPORT_HDP_DS | 732 AMD_CG_SUPPORT_HDP_SD | 733 AMD_CG_SUPPORT_ATHUB_MGCG | 734 AMD_CG_SUPPORT_ATHUB_LS | 735 AMD_CG_SUPPORT_IH_CG | 736 AMD_CG_SUPPORT_BIF_MGCG | 737 AMD_CG_SUPPORT_BIF_LS; 738 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 739 AMD_PG_SUPPORT_JPEG_DPG | 740 AMD_PG_SUPPORT_VCN | 741 AMD_PG_SUPPORT_JPEG | 742 AMD_PG_SUPPORT_GFX_PG; 743 if (adev->rev_id == 0) 744 adev->external_rev_id = 0x1; 745 else 746 adev->external_rev_id = adev->rev_id + 0x10; 747 break; 748 case IP_VERSION(11, 5, 1): 749 adev->cg_flags = 750 AMD_CG_SUPPORT_GFX_CGCG | 751 AMD_CG_SUPPORT_GFX_CGLS | 752 AMD_CG_SUPPORT_GFX_MGCG | 753 AMD_CG_SUPPORT_GFX_FGCG | 754 AMD_CG_SUPPORT_REPEATER_FGCG | 755 AMD_CG_SUPPORT_GFX_PERF_CLK | 756 AMD_CG_SUPPORT_GFX_3D_CGCG | 757 AMD_CG_SUPPORT_GFX_3D_CGLS | 758 AMD_CG_SUPPORT_MC_MGCG | 759 AMD_CG_SUPPORT_MC_LS | 760 AMD_CG_SUPPORT_HDP_LS | 761 AMD_CG_SUPPORT_HDP_DS | 762 AMD_CG_SUPPORT_HDP_SD | 763 AMD_CG_SUPPORT_ATHUB_MGCG | 764 AMD_CG_SUPPORT_ATHUB_LS | 765 AMD_CG_SUPPORT_IH_CG | 766 AMD_CG_SUPPORT_BIF_MGCG | 767 AMD_CG_SUPPORT_BIF_LS | 768 AMD_CG_SUPPORT_VCN_MGCG | 769 AMD_CG_SUPPORT_JPEG_MGCG; 770 adev->pg_flags = 771 AMD_PG_SUPPORT_GFX_PG | 772 AMD_PG_SUPPORT_VCN | 773 AMD_PG_SUPPORT_VCN_DPG | 774 AMD_PG_SUPPORT_JPEG; 775 adev->external_rev_id = adev->rev_id + 0xc1; 776 break; 777 case IP_VERSION(11, 5, 2): 778 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 779 AMD_CG_SUPPORT_JPEG_MGCG | 780 AMD_CG_SUPPORT_GFX_CGCG | 781 AMD_CG_SUPPORT_GFX_CGLS | 782 AMD_CG_SUPPORT_GFX_MGCG | 783 AMD_CG_SUPPORT_GFX_FGCG | 784 AMD_CG_SUPPORT_REPEATER_FGCG | 785 AMD_CG_SUPPORT_GFX_PERF_CLK | 786 AMD_CG_SUPPORT_GFX_3D_CGCG | 787 AMD_CG_SUPPORT_GFX_3D_CGLS | 788 AMD_CG_SUPPORT_MC_MGCG | 789 AMD_CG_SUPPORT_MC_LS | 790 AMD_CG_SUPPORT_HDP_LS | 791 AMD_CG_SUPPORT_HDP_DS | 792 AMD_CG_SUPPORT_HDP_SD | 793 AMD_CG_SUPPORT_ATHUB_MGCG | 794 AMD_CG_SUPPORT_ATHUB_LS | 795 AMD_CG_SUPPORT_IH_CG | 796 AMD_CG_SUPPORT_BIF_MGCG | 797 AMD_CG_SUPPORT_BIF_LS; 798 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 799 AMD_PG_SUPPORT_VCN | 800 AMD_PG_SUPPORT_JPEG_DPG | 801 AMD_PG_SUPPORT_JPEG | 802 AMD_PG_SUPPORT_GFX_PG; 803 adev->external_rev_id = adev->rev_id + 0x40; 804 break; 805 case IP_VERSION(11, 5, 3): 806 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 807 AMD_CG_SUPPORT_JPEG_MGCG | 808 AMD_CG_SUPPORT_GFX_CGCG | 809 AMD_CG_SUPPORT_GFX_CGLS | 810 AMD_CG_SUPPORT_GFX_MGCG | 811 AMD_CG_SUPPORT_GFX_FGCG | 812 AMD_CG_SUPPORT_REPEATER_FGCG | 813 AMD_CG_SUPPORT_GFX_PERF_CLK | 814 AMD_CG_SUPPORT_GFX_3D_CGCG | 815 AMD_CG_SUPPORT_GFX_3D_CGLS | 816 AMD_CG_SUPPORT_MC_MGCG | 817 AMD_CG_SUPPORT_MC_LS | 818 AMD_CG_SUPPORT_HDP_LS | 819 AMD_CG_SUPPORT_HDP_DS | 820 AMD_CG_SUPPORT_HDP_SD | 821 AMD_CG_SUPPORT_ATHUB_MGCG | 822 AMD_CG_SUPPORT_ATHUB_LS | 823 AMD_CG_SUPPORT_IH_CG | 824 AMD_CG_SUPPORT_BIF_MGCG | 825 AMD_CG_SUPPORT_BIF_LS; 826 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | 827 AMD_PG_SUPPORT_VCN | 828 AMD_PG_SUPPORT_JPEG_DPG | 829 AMD_PG_SUPPORT_JPEG | 830 AMD_PG_SUPPORT_GFX_PG; 831 adev->external_rev_id = adev->rev_id + 0x50; 832 break; 833 case IP_VERSION(11, 5, 4): 834 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 835 AMD_CG_SUPPORT_JPEG_MGCG; 836 adev->pg_flags = AMD_PG_SUPPORT_VCN | 837 AMD_PG_SUPPORT_JPEG; 838 adev->external_rev_id = adev->rev_id + 0x1; 839 break; 840 default: 841 /* FIXME: not supported yet */ 842 return -EINVAL; 843 } 844 845 if (amdgpu_sriov_vf(adev)) { 846 amdgpu_virt_init_setting(adev); 847 xgpu_nv_mailbox_set_irq_funcs(adev); 848 } 849 850 return 0; 851 } 852 853 static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) 854 { 855 struct amdgpu_device *adev = ip_block->adev; 856 857 if (amdgpu_sriov_vf(adev)) { 858 xgpu_nv_mailbox_get_irq(adev); 859 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) || 860 !amdgpu_sriov_is_av1_support(adev)) { 861 amdgpu_virt_update_sriov_video_codec(adev, 862 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1, 863 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1), 864 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, 865 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1)); 866 } else { 867 amdgpu_virt_update_sriov_video_codec(adev, 868 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0, 869 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0), 870 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0, 871 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0)); 872 } 873 } else { 874 if (adev->nbio.ras && 875 adev->nbio.ras_err_event_athub_irq.funcs) 876 /* don't need to fail gpu late init 877 * if enabling athub_err_event interrupt failed 878 * nbio v4_3 only support fatal error hanlding 879 * just enable the interrupt directly */ 880 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0); 881 } 882 883 /* Enable selfring doorbell aperture late because doorbell BAR 884 * aperture will change if resize BAR successfully in gmc sw_init. 885 */ 886 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 887 888 return 0; 889 } 890 891 static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) 892 { 893 struct amdgpu_device *adev = ip_block->adev; 894 895 if (amdgpu_sriov_vf(adev)) 896 xgpu_nv_mailbox_add_irq_id(adev); 897 898 return 0; 899 } 900 901 static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) 902 { 903 struct amdgpu_device *adev = ip_block->adev; 904 905 /* enable aspm */ 906 soc21_program_aspm(adev); 907 /* setup nbio registers */ 908 adev->nbio.funcs->init_registers(adev); 909 /* remap HDP registers to a hole in mmio space, 910 * for the purpose of expose those registers 911 * to process space 912 */ 913 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 914 adev->nbio.funcs->remap_hdp_registers(adev); 915 /* enable the doorbell aperture */ 916 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 917 918 return 0; 919 } 920 921 static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) 922 { 923 struct amdgpu_device *adev = ip_block->adev; 924 925 /* Disable the doorbell aperture and selfring doorbell aperture 926 * separately in hw_fini because soc21_enable_doorbell_aperture 927 * has been removed and there is no need to delay disabling 928 * selfring doorbell. 929 */ 930 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 931 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 932 933 if (amdgpu_sriov_vf(adev)) { 934 xgpu_nv_mailbox_put_irq(adev); 935 } else { 936 if (adev->nbio.ras && 937 adev->nbio.ras_err_event_athub_irq.funcs) 938 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 939 } 940 941 return 0; 942 } 943 944 static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) 945 { 946 return soc21_common_hw_fini(ip_block); 947 } 948 949 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) 950 { 951 u32 sol_reg1, sol_reg2; 952 953 /* Will reset for the following suspend abort cases. 954 * 1) Only reset dGPU side. 955 * 2) S3 suspend got aborted and TOS is active. 956 * As for dGPU suspend abort cases the SOL value 957 * will be kept as zero at this resume point. 958 */ 959 if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { 960 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 961 msleep(100); 962 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 963 964 return (sol_reg1 != sol_reg2); 965 } 966 967 return false; 968 } 969 970 static int soc21_common_resume(struct amdgpu_ip_block *ip_block) 971 { 972 struct amdgpu_device *adev = ip_block->adev; 973 974 if (soc21_need_reset_on_resume(adev)) { 975 dev_info(adev->dev, "S3 suspend aborted, resetting..."); 976 soc21_asic_reset(adev); 977 } 978 979 return soc21_common_hw_init(ip_block); 980 } 981 982 static bool soc21_common_is_idle(struct amdgpu_ip_block *ip_block) 983 { 984 return true; 985 } 986 987 static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 988 enum amd_clockgating_state state) 989 { 990 struct amdgpu_device *adev = ip_block->adev; 991 992 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 993 case IP_VERSION(4, 3, 0): 994 case IP_VERSION(4, 3, 1): 995 case IP_VERSION(7, 7, 0): 996 case IP_VERSION(7, 7, 1): 997 case IP_VERSION(7, 11, 0): 998 case IP_VERSION(7, 11, 1): 999 case IP_VERSION(7, 11, 2): 1000 case IP_VERSION(7, 11, 3): 1001 case IP_VERSION(7, 11, 4): 1002 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1003 state == AMD_CG_STATE_GATE); 1004 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1005 state == AMD_CG_STATE_GATE); 1006 adev->hdp.funcs->update_clock_gating(adev, 1007 state == AMD_CG_STATE_GATE); 1008 break; 1009 default: 1010 break; 1011 } 1012 return 0; 1013 } 1014 1015 static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1016 enum amd_powergating_state state) 1017 { 1018 struct amdgpu_device *adev = ip_block->adev; 1019 1020 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 1021 case IP_VERSION(6, 0, 0): 1022 case IP_VERSION(6, 0, 2): 1023 adev->lsdma.funcs->update_memory_power_gating(adev, 1024 state == AMD_PG_STATE_GATE); 1025 break; 1026 default: 1027 break; 1028 } 1029 1030 return 0; 1031 } 1032 1033 static void soc21_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1034 { 1035 struct amdgpu_device *adev = ip_block->adev; 1036 1037 adev->nbio.funcs->get_clockgating_state(adev, flags); 1038 1039 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1040 } 1041 1042 static const struct amd_ip_funcs soc21_common_ip_funcs = { 1043 .name = "soc21_common", 1044 .early_init = soc21_common_early_init, 1045 .late_init = soc21_common_late_init, 1046 .sw_init = soc21_common_sw_init, 1047 .hw_init = soc21_common_hw_init, 1048 .hw_fini = soc21_common_hw_fini, 1049 .suspend = soc21_common_suspend, 1050 .resume = soc21_common_resume, 1051 .is_idle = soc21_common_is_idle, 1052 .set_clockgating_state = soc21_common_set_clockgating_state, 1053 .set_powergating_state = soc21_common_set_powergating_state, 1054 .get_clockgating_state = soc21_common_get_clockgating_state, 1055 }; 1056