1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 }; 112 113 static const struct amdgpu_video_codecs vega_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 116 .codec_array = vega_video_codecs_decode_array, 117 }; 118 119 /* Raven */ 120 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 129 }; 130 131 static const struct amdgpu_video_codecs rv_video_codecs_decode = 132 { 133 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 134 .codec_array = rv_video_codecs_decode_array, 135 }; 136 137 /* Renoir, Arcturus */ 138 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 139 { 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 147 }; 148 149 static const struct amdgpu_video_codecs rn_video_codecs_decode = 150 { 151 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 152 .codec_array = rn_video_codecs_decode_array, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 164 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 165 .codec_array = vcn_4_0_3_video_codecs_decode_array, 166 }; 167 168 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 169 .codec_count = 0, 170 .codec_array = NULL, 171 }; 172 173 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = { 174 .codec_count = 0, 175 .codec_array = NULL, 176 }; 177 178 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = { 179 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 180 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 184 }; 185 186 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = { 187 .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0), 188 .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0, 189 }; 190 191 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 192 const struct amdgpu_video_codecs **codecs) 193 { 194 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 195 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 196 case IP_VERSION(4, 0, 0): 197 case IP_VERSION(4, 1, 0): 198 if (encode) 199 *codecs = &vega_video_codecs_encode; 200 else 201 *codecs = &vega_video_codecs_decode; 202 return 0; 203 default: 204 return -EINVAL; 205 } 206 } else { 207 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 208 case IP_VERSION(1, 0, 0): 209 case IP_VERSION(1, 0, 1): 210 if (encode) 211 *codecs = &vega_video_codecs_encode; 212 else 213 *codecs = &rv_video_codecs_decode; 214 return 0; 215 case IP_VERSION(2, 5, 0): 216 case IP_VERSION(2, 6, 0): 217 case IP_VERSION(2, 2, 0): 218 if (encode) 219 *codecs = &vega_video_codecs_encode; 220 else 221 *codecs = &rn_video_codecs_decode; 222 return 0; 223 case IP_VERSION(4, 0, 3): 224 if (encode) 225 *codecs = &vcn_4_0_3_video_codecs_encode; 226 else 227 *codecs = &vcn_4_0_3_video_codecs_decode; 228 return 0; 229 case IP_VERSION(5, 0, 1): 230 if (encode) 231 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0; 232 else 233 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0; 234 return 0; 235 default: 236 return -EINVAL; 237 } 238 } 239 } 240 241 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 242 { 243 unsigned long flags, address, data; 244 u32 r; 245 246 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 247 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 248 249 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 250 WREG32(address, ((reg) & 0x1ff)); 251 r = RREG32(data); 252 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 253 return r; 254 } 255 256 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 257 { 258 unsigned long flags, address, data; 259 260 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 261 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 262 263 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 264 WREG32(address, ((reg) & 0x1ff)); 265 WREG32(data, (v)); 266 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 267 } 268 269 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 270 { 271 unsigned long flags, address, data; 272 u32 r; 273 274 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 275 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 276 277 spin_lock_irqsave(&adev->didt_idx_lock, flags); 278 WREG32(address, (reg)); 279 r = RREG32(data); 280 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 281 return r; 282 } 283 284 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 285 { 286 unsigned long flags, address, data; 287 288 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 289 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 290 291 spin_lock_irqsave(&adev->didt_idx_lock, flags); 292 WREG32(address, (reg)); 293 WREG32(data, (v)); 294 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 295 } 296 297 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 298 { 299 unsigned long flags; 300 u32 r; 301 302 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 303 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 304 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 305 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 306 return r; 307 } 308 309 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 310 { 311 unsigned long flags; 312 313 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 314 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 315 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 316 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 317 } 318 319 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 320 { 321 unsigned long flags; 322 u32 r; 323 324 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 325 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 326 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 327 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 328 return r; 329 } 330 331 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 332 { 333 unsigned long flags; 334 335 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 336 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 337 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 338 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 339 } 340 341 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 342 { 343 return adev->nbio.funcs->get_memsize(adev); 344 } 345 346 static u32 soc15_get_xclk(struct amdgpu_device *adev) 347 { 348 u32 reference_clock = adev->clock.spll.reference_freq; 349 350 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || 351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || 352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || 353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || 354 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) 355 return 10000; 356 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || 357 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) 358 return reference_clock / 4; 359 360 return reference_clock; 361 } 362 363 364 void soc15_grbm_select(struct amdgpu_device *adev, 365 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 366 { 367 u32 grbm_gfx_cntl = 0; 368 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 371 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 372 373 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 374 } 375 376 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 377 { 378 /* todo */ 379 return false; 380 } 381 382 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 383 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 389 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 390 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 391 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 392 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 393 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 394 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 400 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 401 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 402 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 403 }; 404 405 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 406 u32 sh_num, u32 reg_offset) 407 { 408 uint32_t val; 409 410 mutex_lock(&adev->grbm_idx_mutex); 411 if (se_num != 0xffffffff || sh_num != 0xffffffff) 412 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 413 414 val = RREG32(reg_offset); 415 416 if (se_num != 0xffffffff || sh_num != 0xffffffff) 417 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 418 mutex_unlock(&adev->grbm_idx_mutex); 419 return val; 420 } 421 422 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 423 bool indexed, u32 se_num, 424 u32 sh_num, u32 reg_offset) 425 { 426 if (indexed) { 427 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 428 } else { 429 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 430 return adev->gfx.config.gb_addr_config; 431 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 432 return adev->gfx.config.db_debug2; 433 return RREG32(reg_offset); 434 } 435 } 436 437 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 438 u32 sh_num, u32 reg_offset, u32 *value) 439 { 440 uint32_t i; 441 struct soc15_allowed_register_entry *en; 442 443 *value = 0; 444 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 445 en = &soc15_allowed_read_registers[i]; 446 if (!adev->reg_offset[en->hwip][en->inst]) 447 continue; 448 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 449 + en->reg_offset)) 450 continue; 451 452 *value = soc15_get_register_value(adev, 453 soc15_allowed_read_registers[i].grbm_indexed, 454 se_num, sh_num, reg_offset); 455 return 0; 456 } 457 return -EINVAL; 458 } 459 460 461 /** 462 * soc15_program_register_sequence - program an array of registers. 463 * 464 * @adev: amdgpu_device pointer 465 * @regs: pointer to the register array 466 * @array_size: size of the register array 467 * 468 * Programs an array or registers with and and or masks. 469 * This is a helper for setting golden registers. 470 */ 471 472 void soc15_program_register_sequence(struct amdgpu_device *adev, 473 const struct soc15_reg_golden *regs, 474 const u32 array_size) 475 { 476 const struct soc15_reg_golden *entry; 477 u32 tmp, reg; 478 int i; 479 480 for (i = 0; i < array_size; ++i) { 481 entry = ®s[i]; 482 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 483 484 if (entry->and_mask == 0xffffffff) { 485 tmp = entry->or_mask; 486 } else { 487 tmp = (entry->hwip == GC_HWIP) ? 488 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 489 490 tmp &= ~(entry->and_mask); 491 tmp |= (entry->or_mask & entry->and_mask); 492 } 493 494 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 495 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 496 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 497 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 498 WREG32_RLC(reg, tmp); 499 else 500 (entry->hwip == GC_HWIP) ? 501 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 502 503 } 504 505 } 506 507 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 508 { 509 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 510 int ret = 0; 511 512 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 513 if (ras && adev->ras_enabled) 514 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 515 516 ret = amdgpu_dpm_baco_reset(adev); 517 if (ret) 518 return ret; 519 520 /* re-enable doorbell interrupt after BACO exit */ 521 if (ras && adev->ras_enabled) 522 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 523 524 return 0; 525 } 526 527 static enum amd_reset_method 528 soc15_asic_reset_method(struct amdgpu_device *adev) 529 { 530 int baco_reset = 0; 531 bool connected_to_cpu = false; 532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 533 534 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 535 connected_to_cpu = true; 536 537 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 538 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 539 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 540 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 541 /* If connected to cpu, driver only support mode2 */ 542 if (connected_to_cpu) 543 return AMD_RESET_METHOD_MODE2; 544 return amdgpu_reset_method; 545 } 546 547 if (amdgpu_reset_method != -1) 548 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 549 amdgpu_reset_method); 550 551 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 552 case IP_VERSION(10, 0, 0): 553 case IP_VERSION(10, 0, 1): 554 case IP_VERSION(12, 0, 0): 555 case IP_VERSION(12, 0, 1): 556 return AMD_RESET_METHOD_MODE2; 557 case IP_VERSION(9, 0, 0): 558 case IP_VERSION(11, 0, 2): 559 if (adev->asic_type == CHIP_VEGA20) { 560 if (adev->psp.sos.fw_version >= 0x80067) 561 baco_reset = amdgpu_dpm_is_baco_supported(adev); 562 /* 563 * 1. PMFW version > 0x284300: all cases use baco 564 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 565 */ 566 if (ras && adev->ras_enabled && 567 adev->pm.fw_version <= 0x283400) 568 baco_reset = 0; 569 } else { 570 baco_reset = amdgpu_dpm_is_baco_supported(adev); 571 } 572 break; 573 case IP_VERSION(13, 0, 2): 574 /* 575 * 1.connected to cpu: driver issue mode2 reset 576 * 2.discret gpu: driver issue mode1 reset 577 */ 578 if (connected_to_cpu) 579 return AMD_RESET_METHOD_MODE2; 580 break; 581 case IP_VERSION(13, 0, 6): 582 case IP_VERSION(13, 0, 14): 583 case IP_VERSION(13, 0, 12): 584 /* Use gpu_recovery param to target a reset method. 585 * Enable triggering of GPU reset only if specified 586 * by module parameter. 587 */ 588 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 589 return AMD_RESET_METHOD_MODE2; 590 else if (!(adev->flags & AMD_IS_APU)) 591 return AMD_RESET_METHOD_MODE1; 592 else 593 return AMD_RESET_METHOD_MODE2; 594 default: 595 break; 596 } 597 598 if (baco_reset) 599 return AMD_RESET_METHOD_BACO; 600 else 601 return AMD_RESET_METHOD_MODE1; 602 } 603 604 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 605 { 606 /* Will reset for the following suspend abort cases. 607 * 1) Only reset on APU side, dGPU hasn't checked yet. 608 * 2) S3 suspend aborted in the normal S3 suspend or 609 * performing pm core test. 610 */ 611 if (adev->flags & AMD_IS_APU && adev->in_s3 && 612 !pm_resume_via_firmware()) 613 return true; 614 else 615 return false; 616 } 617 618 static int soc15_asic_reset(struct amdgpu_device *adev) 619 { 620 /* original raven doesn't have full asic reset */ 621 /* On the latest Raven, the GPU reset can be performed 622 * successfully. So now, temporarily enable it for the 623 * S3 suspend abort case. 624 */ 625 626 if ((adev->apu_flags & AMD_APU_IS_PICASSO || 627 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 628 soc15_need_reset_on_resume(adev)) 629 goto asic_reset; 630 631 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 632 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 633 return 0; 634 635 asic_reset: 636 switch (soc15_asic_reset_method(adev)) { 637 case AMD_RESET_METHOD_PCI: 638 dev_info(adev->dev, "PCI reset\n"); 639 return amdgpu_device_pci_reset(adev); 640 case AMD_RESET_METHOD_BACO: 641 dev_info(adev->dev, "BACO reset\n"); 642 return soc15_asic_baco_reset(adev); 643 case AMD_RESET_METHOD_MODE2: 644 dev_info(adev->dev, "MODE2 reset\n"); 645 return amdgpu_dpm_mode2_reset(adev); 646 default: 647 dev_info(adev->dev, "MODE1 reset\n"); 648 return amdgpu_device_mode1_reset(adev); 649 } 650 } 651 652 static int soc15_supports_baco(struct amdgpu_device *adev) 653 { 654 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 655 case IP_VERSION(9, 0, 0): 656 case IP_VERSION(11, 0, 2): 657 if (adev->asic_type == CHIP_VEGA20) { 658 if (adev->psp.sos.fw_version >= 0x80067) 659 return amdgpu_dpm_is_baco_supported(adev); 660 return 0; 661 } else { 662 return amdgpu_dpm_is_baco_supported(adev); 663 } 664 break; 665 default: 666 return 0; 667 } 668 } 669 670 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 671 u32 cntl_reg, u32 status_reg) 672 { 673 return 0; 674 }*/ 675 676 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 677 { 678 /*int r; 679 680 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 681 if (r) 682 return r; 683 684 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 685 */ 686 return 0; 687 } 688 689 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 690 { 691 /* todo */ 692 693 return 0; 694 } 695 696 static void soc15_program_aspm(struct amdgpu_device *adev) 697 { 698 if (!amdgpu_device_should_use_aspm(adev)) 699 return; 700 701 if (adev->nbio.funcs->program_aspm) 702 adev->nbio.funcs->program_aspm(adev); 703 } 704 705 const struct amdgpu_ip_block_version vega10_common_ip_block = 706 { 707 .type = AMD_IP_BLOCK_TYPE_COMMON, 708 .major = 2, 709 .minor = 0, 710 .rev = 0, 711 .funcs = &soc15_common_ip_funcs, 712 }; 713 714 static void soc15_reg_base_init(struct amdgpu_device *adev) 715 { 716 /* Set IP register base before any HW register access */ 717 switch (adev->asic_type) { 718 case CHIP_VEGA10: 719 case CHIP_VEGA12: 720 case CHIP_RAVEN: 721 case CHIP_RENOIR: 722 vega10_reg_base_init(adev); 723 break; 724 case CHIP_VEGA20: 725 vega20_reg_base_init(adev); 726 break; 727 case CHIP_ARCTURUS: 728 arct_reg_base_init(adev); 729 break; 730 case CHIP_ALDEBARAN: 731 aldebaran_reg_base_init(adev); 732 break; 733 default: 734 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 735 break; 736 } 737 } 738 739 void soc15_set_virt_ops(struct amdgpu_device *adev) 740 { 741 adev->virt.ops = &xgpu_ai_virt_ops; 742 743 /* init soc15 reg base early enough so we can 744 * request request full access for sriov before 745 * set_ip_blocks. */ 746 soc15_reg_base_init(adev); 747 } 748 749 static bool soc15_need_full_reset(struct amdgpu_device *adev) 750 { 751 /* change this when we implement soft reset */ 752 return true; 753 } 754 755 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 756 uint64_t *count1) 757 { 758 uint32_t perfctr = 0; 759 uint64_t cnt0_of, cnt1_of; 760 int tmp; 761 762 /* This reports 0 on APUs, so return to avoid writing/reading registers 763 * that may or may not be different from their GPU counterparts 764 */ 765 if (adev->flags & AMD_IS_APU) 766 return; 767 768 /* Set the 2 events that we wish to watch, defined above */ 769 /* Reg 40 is # received msgs */ 770 /* Reg 104 is # of posted requests sent */ 771 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 772 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 773 774 /* Write to enable desired perf counters */ 775 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 776 /* Zero out and enable the perf counters 777 * Write 0x5: 778 * Bit 0 = Start all counters(1) 779 * Bit 2 = Global counter reset enable(1) 780 */ 781 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 782 783 msleep(1000); 784 785 /* Load the shadow and disable the perf counters 786 * Write 0x2: 787 * Bit 0 = Stop counters(0) 788 * Bit 1 = Load the shadow counters(1) 789 */ 790 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 791 792 /* Read register values to get any >32bit overflow */ 793 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 794 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 795 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 796 797 /* Get the values and add the overflow */ 798 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 799 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 800 } 801 802 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 803 uint64_t *count1) 804 { 805 uint32_t perfctr = 0; 806 uint64_t cnt0_of, cnt1_of; 807 int tmp; 808 809 /* This reports 0 on APUs, so return to avoid writing/reading registers 810 * that may or may not be different from their GPU counterparts 811 */ 812 if (adev->flags & AMD_IS_APU) 813 return; 814 815 /* Set the 2 events that we wish to watch, defined above */ 816 /* Reg 40 is # received msgs */ 817 /* Reg 108 is # of posted requests sent on VG20 */ 818 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 819 EVENT0_SEL, 40); 820 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 821 EVENT1_SEL, 108); 822 823 /* Write to enable desired perf counters */ 824 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 825 /* Zero out and enable the perf counters 826 * Write 0x5: 827 * Bit 0 = Start all counters(1) 828 * Bit 2 = Global counter reset enable(1) 829 */ 830 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 831 832 msleep(1000); 833 834 /* Load the shadow and disable the perf counters 835 * Write 0x2: 836 * Bit 0 = Stop counters(0) 837 * Bit 1 = Load the shadow counters(1) 838 */ 839 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 840 841 /* Read register values to get any >32bit overflow */ 842 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 843 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 844 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 845 846 /* Get the values and add the overflow */ 847 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 848 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 849 } 850 851 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 852 { 853 u32 sol_reg; 854 855 /* CP hangs in IGT reloading test on RN, reset to WA */ 856 if (adev->asic_type == CHIP_RENOIR) 857 return true; 858 859 if (amdgpu_gmc_need_reset_on_init(adev)) 860 return true; 861 if (amdgpu_psp_tos_reload_needed(adev)) 862 return true; 863 /* Just return false for soc15 GPUs. Reset does not seem to 864 * be necessary. 865 */ 866 if (!amdgpu_passthrough(adev)) 867 return false; 868 869 if (adev->flags & AMD_IS_APU) 870 return false; 871 872 /* Check sOS sign of life register to confirm sys driver and sOS 873 * are already been loaded. 874 */ 875 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 876 if (sol_reg) 877 return true; 878 879 return false; 880 } 881 882 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 883 { 884 uint64_t nak_r, nak_g; 885 886 /* Get the number of NAKs received and generated */ 887 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 888 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 889 890 /* Add the total number of NAKs, i.e the number of replays */ 891 return (nak_r + nak_g); 892 } 893 894 static void soc15_pre_asic_init(struct amdgpu_device *adev) 895 { 896 gmc_v9_0_restore_registers(adev); 897 } 898 899 static const struct amdgpu_asic_funcs soc15_asic_funcs = 900 { 901 .read_disabled_bios = &soc15_read_disabled_bios, 902 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 903 .read_register = &soc15_read_register, 904 .reset = &soc15_asic_reset, 905 .reset_method = &soc15_asic_reset_method, 906 .get_xclk = &soc15_get_xclk, 907 .set_uvd_clocks = &soc15_set_uvd_clocks, 908 .set_vce_clocks = &soc15_set_vce_clocks, 909 .get_config_memsize = &soc15_get_config_memsize, 910 .need_full_reset = &soc15_need_full_reset, 911 .init_doorbell_index = &vega10_doorbell_index_init, 912 .get_pcie_usage = &soc15_get_pcie_usage, 913 .need_reset_on_init = &soc15_need_reset_on_init, 914 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 915 .supports_baco = &soc15_supports_baco, 916 .pre_asic_init = &soc15_pre_asic_init, 917 .query_video_codecs = &soc15_query_video_codecs, 918 }; 919 920 static const struct amdgpu_asic_funcs vega20_asic_funcs = 921 { 922 .read_disabled_bios = &soc15_read_disabled_bios, 923 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 924 .read_register = &soc15_read_register, 925 .reset = &soc15_asic_reset, 926 .reset_method = &soc15_asic_reset_method, 927 .get_xclk = &soc15_get_xclk, 928 .set_uvd_clocks = &soc15_set_uvd_clocks, 929 .set_vce_clocks = &soc15_set_vce_clocks, 930 .get_config_memsize = &soc15_get_config_memsize, 931 .need_full_reset = &soc15_need_full_reset, 932 .init_doorbell_index = &vega20_doorbell_index_init, 933 .get_pcie_usage = &vega20_get_pcie_usage, 934 .need_reset_on_init = &soc15_need_reset_on_init, 935 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 936 .supports_baco = &soc15_supports_baco, 937 .pre_asic_init = &soc15_pre_asic_init, 938 .query_video_codecs = &soc15_query_video_codecs, 939 }; 940 941 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 942 { 943 .read_disabled_bios = &soc15_read_disabled_bios, 944 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 945 .read_register = &soc15_read_register, 946 .reset = &soc15_asic_reset, 947 .reset_method = &soc15_asic_reset_method, 948 .get_xclk = &soc15_get_xclk, 949 .set_uvd_clocks = &soc15_set_uvd_clocks, 950 .set_vce_clocks = &soc15_set_vce_clocks, 951 .get_config_memsize = &soc15_get_config_memsize, 952 .need_full_reset = &soc15_need_full_reset, 953 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 954 .need_reset_on_init = &soc15_need_reset_on_init, 955 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 956 .supports_baco = &soc15_supports_baco, 957 .pre_asic_init = &soc15_pre_asic_init, 958 .query_video_codecs = &soc15_query_video_codecs, 959 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, 960 .get_reg_state = &aqua_vanjaram_get_reg_state, 961 }; 962 963 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) 964 { 965 struct amdgpu_device *adev = ip_block->adev; 966 967 adev->nbio.funcs->set_reg_remap(adev); 968 adev->smc_rreg = NULL; 969 adev->smc_wreg = NULL; 970 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 971 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 972 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 973 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 974 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 975 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 976 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 977 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 978 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 979 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 980 adev->didt_rreg = &soc15_didt_rreg; 981 adev->didt_wreg = &soc15_didt_wreg; 982 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 983 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 984 adev->se_cac_rreg = &soc15_se_cac_rreg; 985 adev->se_cac_wreg = &soc15_se_cac_wreg; 986 987 adev->rev_id = amdgpu_device_get_rev_id(adev); 988 adev->external_rev_id = 0xFF; 989 /* TODO: split the GC and PG flags based on the relevant IP version for which 990 * they are relevant. 991 */ 992 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 993 case IP_VERSION(9, 0, 1): 994 adev->asic_funcs = &soc15_asic_funcs; 995 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 996 AMD_CG_SUPPORT_GFX_MGLS | 997 AMD_CG_SUPPORT_GFX_RLC_LS | 998 AMD_CG_SUPPORT_GFX_CP_LS | 999 AMD_CG_SUPPORT_GFX_3D_CGCG | 1000 AMD_CG_SUPPORT_GFX_3D_CGLS | 1001 AMD_CG_SUPPORT_GFX_CGCG | 1002 AMD_CG_SUPPORT_GFX_CGLS | 1003 AMD_CG_SUPPORT_BIF_MGCG | 1004 AMD_CG_SUPPORT_BIF_LS | 1005 AMD_CG_SUPPORT_HDP_LS | 1006 AMD_CG_SUPPORT_DRM_MGCG | 1007 AMD_CG_SUPPORT_DRM_LS | 1008 AMD_CG_SUPPORT_ROM_MGCG | 1009 AMD_CG_SUPPORT_DF_MGCG | 1010 AMD_CG_SUPPORT_SDMA_MGCG | 1011 AMD_CG_SUPPORT_SDMA_LS | 1012 AMD_CG_SUPPORT_MC_MGCG | 1013 AMD_CG_SUPPORT_MC_LS; 1014 adev->pg_flags = 0; 1015 adev->external_rev_id = 0x1; 1016 break; 1017 case IP_VERSION(9, 2, 1): 1018 adev->asic_funcs = &soc15_asic_funcs; 1019 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1020 AMD_CG_SUPPORT_GFX_MGLS | 1021 AMD_CG_SUPPORT_GFX_CGCG | 1022 AMD_CG_SUPPORT_GFX_CGLS | 1023 AMD_CG_SUPPORT_GFX_3D_CGCG | 1024 AMD_CG_SUPPORT_GFX_3D_CGLS | 1025 AMD_CG_SUPPORT_GFX_CP_LS | 1026 AMD_CG_SUPPORT_MC_LS | 1027 AMD_CG_SUPPORT_MC_MGCG | 1028 AMD_CG_SUPPORT_SDMA_MGCG | 1029 AMD_CG_SUPPORT_SDMA_LS | 1030 AMD_CG_SUPPORT_BIF_MGCG | 1031 AMD_CG_SUPPORT_BIF_LS | 1032 AMD_CG_SUPPORT_HDP_MGCG | 1033 AMD_CG_SUPPORT_HDP_LS | 1034 AMD_CG_SUPPORT_ROM_MGCG | 1035 AMD_CG_SUPPORT_VCE_MGCG | 1036 AMD_CG_SUPPORT_UVD_MGCG; 1037 adev->pg_flags = 0; 1038 adev->external_rev_id = adev->rev_id + 0x14; 1039 break; 1040 case IP_VERSION(9, 4, 0): 1041 adev->asic_funcs = &vega20_asic_funcs; 1042 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1043 AMD_CG_SUPPORT_GFX_MGLS | 1044 AMD_CG_SUPPORT_GFX_CGCG | 1045 AMD_CG_SUPPORT_GFX_CGLS | 1046 AMD_CG_SUPPORT_GFX_3D_CGCG | 1047 AMD_CG_SUPPORT_GFX_3D_CGLS | 1048 AMD_CG_SUPPORT_GFX_CP_LS | 1049 AMD_CG_SUPPORT_MC_LS | 1050 AMD_CG_SUPPORT_MC_MGCG | 1051 AMD_CG_SUPPORT_SDMA_MGCG | 1052 AMD_CG_SUPPORT_SDMA_LS | 1053 AMD_CG_SUPPORT_BIF_MGCG | 1054 AMD_CG_SUPPORT_BIF_LS | 1055 AMD_CG_SUPPORT_HDP_MGCG | 1056 AMD_CG_SUPPORT_HDP_LS | 1057 AMD_CG_SUPPORT_ROM_MGCG | 1058 AMD_CG_SUPPORT_VCE_MGCG | 1059 AMD_CG_SUPPORT_UVD_MGCG; 1060 adev->pg_flags = 0; 1061 adev->external_rev_id = adev->rev_id + 0x28; 1062 break; 1063 case IP_VERSION(9, 1, 0): 1064 case IP_VERSION(9, 2, 2): 1065 adev->asic_funcs = &soc15_asic_funcs; 1066 1067 if (adev->rev_id >= 0x8) 1068 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1069 1070 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1071 adev->external_rev_id = adev->rev_id + 0x79; 1072 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1073 adev->external_rev_id = adev->rev_id + 0x41; 1074 else if (adev->rev_id == 1) 1075 adev->external_rev_id = adev->rev_id + 0x20; 1076 else 1077 adev->external_rev_id = adev->rev_id + 0x01; 1078 1079 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1080 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1081 AMD_CG_SUPPORT_GFX_MGLS | 1082 AMD_CG_SUPPORT_GFX_CP_LS | 1083 AMD_CG_SUPPORT_GFX_3D_CGCG | 1084 AMD_CG_SUPPORT_GFX_3D_CGLS | 1085 AMD_CG_SUPPORT_GFX_CGCG | 1086 AMD_CG_SUPPORT_GFX_CGLS | 1087 AMD_CG_SUPPORT_BIF_LS | 1088 AMD_CG_SUPPORT_HDP_LS | 1089 AMD_CG_SUPPORT_MC_MGCG | 1090 AMD_CG_SUPPORT_MC_LS | 1091 AMD_CG_SUPPORT_SDMA_MGCG | 1092 AMD_CG_SUPPORT_SDMA_LS | 1093 AMD_CG_SUPPORT_VCN_MGCG; 1094 1095 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1096 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1097 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1098 AMD_CG_SUPPORT_GFX_MGLS | 1099 AMD_CG_SUPPORT_GFX_CP_LS | 1100 AMD_CG_SUPPORT_GFX_3D_CGLS | 1101 AMD_CG_SUPPORT_GFX_CGCG | 1102 AMD_CG_SUPPORT_GFX_CGLS | 1103 AMD_CG_SUPPORT_BIF_LS | 1104 AMD_CG_SUPPORT_HDP_LS | 1105 AMD_CG_SUPPORT_MC_MGCG | 1106 AMD_CG_SUPPORT_MC_LS | 1107 AMD_CG_SUPPORT_SDMA_MGCG | 1108 AMD_CG_SUPPORT_SDMA_LS | 1109 AMD_CG_SUPPORT_VCN_MGCG; 1110 1111 /* 1112 * MMHUB PG needs to be disabled for Picasso for 1113 * stability reasons. 1114 */ 1115 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1116 AMD_PG_SUPPORT_VCN; 1117 } else { 1118 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1119 AMD_CG_SUPPORT_GFX_MGLS | 1120 AMD_CG_SUPPORT_GFX_RLC_LS | 1121 AMD_CG_SUPPORT_GFX_CP_LS | 1122 AMD_CG_SUPPORT_GFX_3D_CGLS | 1123 AMD_CG_SUPPORT_GFX_CGCG | 1124 AMD_CG_SUPPORT_GFX_CGLS | 1125 AMD_CG_SUPPORT_BIF_MGCG | 1126 AMD_CG_SUPPORT_BIF_LS | 1127 AMD_CG_SUPPORT_HDP_MGCG | 1128 AMD_CG_SUPPORT_HDP_LS | 1129 AMD_CG_SUPPORT_DRM_MGCG | 1130 AMD_CG_SUPPORT_DRM_LS | 1131 AMD_CG_SUPPORT_MC_MGCG | 1132 AMD_CG_SUPPORT_MC_LS | 1133 AMD_CG_SUPPORT_SDMA_MGCG | 1134 AMD_CG_SUPPORT_SDMA_LS | 1135 AMD_CG_SUPPORT_VCN_MGCG; 1136 1137 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1138 } 1139 break; 1140 case IP_VERSION(9, 4, 1): 1141 adev->asic_funcs = &vega20_asic_funcs; 1142 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1143 AMD_CG_SUPPORT_GFX_MGLS | 1144 AMD_CG_SUPPORT_GFX_CGCG | 1145 AMD_CG_SUPPORT_GFX_CGLS | 1146 AMD_CG_SUPPORT_GFX_CP_LS | 1147 AMD_CG_SUPPORT_HDP_MGCG | 1148 AMD_CG_SUPPORT_HDP_LS | 1149 AMD_CG_SUPPORT_SDMA_MGCG | 1150 AMD_CG_SUPPORT_SDMA_LS | 1151 AMD_CG_SUPPORT_MC_MGCG | 1152 AMD_CG_SUPPORT_MC_LS | 1153 AMD_CG_SUPPORT_IH_CG | 1154 AMD_CG_SUPPORT_VCN_MGCG | 1155 AMD_CG_SUPPORT_JPEG_MGCG; 1156 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1157 adev->external_rev_id = adev->rev_id + 0x32; 1158 break; 1159 case IP_VERSION(9, 3, 0): 1160 adev->asic_funcs = &soc15_asic_funcs; 1161 1162 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1163 adev->external_rev_id = adev->rev_id + 0x91; 1164 else 1165 adev->external_rev_id = adev->rev_id + 0xa1; 1166 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1167 AMD_CG_SUPPORT_GFX_MGLS | 1168 AMD_CG_SUPPORT_GFX_3D_CGCG | 1169 AMD_CG_SUPPORT_GFX_3D_CGLS | 1170 AMD_CG_SUPPORT_GFX_CGCG | 1171 AMD_CG_SUPPORT_GFX_CGLS | 1172 AMD_CG_SUPPORT_GFX_CP_LS | 1173 AMD_CG_SUPPORT_MC_MGCG | 1174 AMD_CG_SUPPORT_MC_LS | 1175 AMD_CG_SUPPORT_SDMA_MGCG | 1176 AMD_CG_SUPPORT_SDMA_LS | 1177 AMD_CG_SUPPORT_BIF_LS | 1178 AMD_CG_SUPPORT_HDP_LS | 1179 AMD_CG_SUPPORT_VCN_MGCG | 1180 AMD_CG_SUPPORT_JPEG_MGCG | 1181 AMD_CG_SUPPORT_IH_CG | 1182 AMD_CG_SUPPORT_ATHUB_LS | 1183 AMD_CG_SUPPORT_ATHUB_MGCG | 1184 AMD_CG_SUPPORT_DF_MGCG; 1185 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1186 AMD_PG_SUPPORT_VCN | 1187 AMD_PG_SUPPORT_JPEG | 1188 AMD_PG_SUPPORT_VCN_DPG; 1189 break; 1190 case IP_VERSION(9, 4, 2): 1191 adev->asic_funcs = &vega20_asic_funcs; 1192 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1193 AMD_CG_SUPPORT_GFX_MGLS | 1194 AMD_CG_SUPPORT_GFX_CP_LS | 1195 AMD_CG_SUPPORT_HDP_LS | 1196 AMD_CG_SUPPORT_SDMA_MGCG | 1197 AMD_CG_SUPPORT_SDMA_LS | 1198 AMD_CG_SUPPORT_IH_CG | 1199 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1200 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1201 adev->external_rev_id = adev->rev_id + 0x3c; 1202 break; 1203 case IP_VERSION(9, 4, 3): 1204 case IP_VERSION(9, 4, 4): 1205 case IP_VERSION(9, 5, 0): 1206 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1207 adev->cg_flags = 1208 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1209 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1210 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1211 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1212 AMD_CG_SUPPORT_IH_CG; 1213 adev->pg_flags = 1214 AMD_PG_SUPPORT_VCN | 1215 AMD_PG_SUPPORT_VCN_DPG | 1216 AMD_PG_SUPPORT_JPEG; 1217 /*TODO: need a new external_rev_id for GC 9.4.4? */ 1218 adev->external_rev_id = adev->rev_id + 0x46; 1219 break; 1220 default: 1221 /* FIXME: not supported yet */ 1222 return -EINVAL; 1223 } 1224 1225 if (amdgpu_sriov_vf(adev)) { 1226 amdgpu_virt_init_setting(adev); 1227 xgpu_ai_mailbox_set_irq_funcs(adev); 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) 1234 { 1235 struct amdgpu_device *adev = ip_block->adev; 1236 1237 if (amdgpu_sriov_vf(adev)) 1238 xgpu_ai_mailbox_get_irq(adev); 1239 1240 /* Enable selfring doorbell aperture late because doorbell BAR 1241 * aperture will change if resize BAR successfully in gmc sw_init. 1242 */ 1243 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1244 1245 return 0; 1246 } 1247 1248 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) 1249 { 1250 struct amdgpu_device *adev = ip_block->adev; 1251 1252 if (amdgpu_sriov_vf(adev)) 1253 xgpu_ai_mailbox_add_irq_id(adev); 1254 1255 if (adev->df.funcs && 1256 adev->df.funcs->sw_init) 1257 adev->df.funcs->sw_init(adev); 1258 1259 return 0; 1260 } 1261 1262 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) 1263 { 1264 struct amdgpu_device *adev = ip_block->adev; 1265 1266 if (adev->df.funcs && 1267 adev->df.funcs->sw_fini) 1268 adev->df.funcs->sw_fini(adev); 1269 return 0; 1270 } 1271 1272 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1273 { 1274 int i; 1275 1276 /* sdma doorbell range is programed by hypervisor */ 1277 if (!amdgpu_sriov_vf(adev)) { 1278 for (i = 0; i < adev->sdma.num_instances; i++) { 1279 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1280 true, adev->doorbell_index.sdma_engine[i] << 1, 1281 adev->doorbell_index.sdma_doorbell_range); 1282 } 1283 } 1284 } 1285 1286 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) 1287 { 1288 struct amdgpu_device *adev = ip_block->adev; 1289 1290 /* enable aspm */ 1291 soc15_program_aspm(adev); 1292 /* setup nbio registers */ 1293 adev->nbio.funcs->init_registers(adev); 1294 /* remap HDP registers to a hole in mmio space, 1295 * for the purpose of expose those registers 1296 * to process space 1297 */ 1298 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1299 adev->nbio.funcs->remap_hdp_registers(adev); 1300 1301 /* enable the doorbell aperture */ 1302 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1303 1304 /* HW doorbell routing policy: doorbell writing not 1305 * in SDMA/IH/MM/ACV range will be routed to CP. So 1306 * we need to init SDMA doorbell range prior 1307 * to CP ip block init and ring test. IH already 1308 * happens before CP. 1309 */ 1310 soc15_sdma_doorbell_range_init(adev); 1311 1312 return 0; 1313 } 1314 1315 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) 1316 { 1317 struct amdgpu_device *adev = ip_block->adev; 1318 1319 /* Disable the doorbell aperture and selfring doorbell aperture 1320 * separately in hw_fini because soc15_enable_doorbell_aperture 1321 * has been removed and there is no need to delay disabling 1322 * selfring doorbell. 1323 */ 1324 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1325 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1326 1327 if (amdgpu_sriov_vf(adev)) 1328 xgpu_ai_mailbox_put_irq(adev); 1329 1330 /* 1331 * For minimal init, late_init is not called, hence RAS irqs are not 1332 * enabled. 1333 */ 1334 if ((!amdgpu_sriov_vf(adev)) && 1335 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1336 adev->nbio.ras_if && 1337 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1338 if (adev->nbio.ras && 1339 adev->nbio.ras->init_ras_controller_interrupt) 1340 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1341 if (adev->nbio.ras && 1342 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1343 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) 1350 { 1351 return soc15_common_hw_fini(ip_block); 1352 } 1353 1354 static int soc15_common_resume(struct amdgpu_ip_block *ip_block) 1355 { 1356 struct amdgpu_device *adev = ip_block->adev; 1357 1358 if (soc15_need_reset_on_resume(adev)) { 1359 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); 1360 soc15_asic_reset(adev); 1361 } 1362 return soc15_common_hw_init(ip_block); 1363 } 1364 1365 static bool soc15_common_is_idle(void *handle) 1366 { 1367 return true; 1368 } 1369 1370 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1371 { 1372 uint32_t def, data; 1373 1374 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1375 1376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1377 data &= ~(0x01000000 | 1378 0x02000000 | 1379 0x04000000 | 1380 0x08000000 | 1381 0x10000000 | 1382 0x20000000 | 1383 0x40000000 | 1384 0x80000000); 1385 else 1386 data |= (0x01000000 | 1387 0x02000000 | 1388 0x04000000 | 1389 0x08000000 | 1390 0x10000000 | 1391 0x20000000 | 1392 0x40000000 | 1393 0x80000000); 1394 1395 if (def != data) 1396 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1397 } 1398 1399 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1400 { 1401 uint32_t def, data; 1402 1403 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1404 1405 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1406 data |= 1; 1407 else 1408 data &= ~1; 1409 1410 if (def != data) 1411 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1412 } 1413 1414 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1415 enum amd_clockgating_state state) 1416 { 1417 struct amdgpu_device *adev = ip_block->adev; 1418 1419 if (amdgpu_sriov_vf(adev)) 1420 return 0; 1421 1422 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1423 case IP_VERSION(6, 1, 0): 1424 case IP_VERSION(6, 2, 0): 1425 case IP_VERSION(7, 4, 0): 1426 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1427 state == AMD_CG_STATE_GATE); 1428 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1429 state == AMD_CG_STATE_GATE); 1430 adev->hdp.funcs->update_clock_gating(adev, 1431 state == AMD_CG_STATE_GATE); 1432 soc15_update_drm_clock_gating(adev, 1433 state == AMD_CG_STATE_GATE); 1434 soc15_update_drm_light_sleep(adev, 1435 state == AMD_CG_STATE_GATE); 1436 adev->smuio.funcs->update_rom_clock_gating(adev, 1437 state == AMD_CG_STATE_GATE); 1438 adev->df.funcs->update_medium_grain_clock_gating(adev, 1439 state == AMD_CG_STATE_GATE); 1440 break; 1441 case IP_VERSION(7, 0, 0): 1442 case IP_VERSION(7, 0, 1): 1443 case IP_VERSION(2, 5, 0): 1444 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1445 state == AMD_CG_STATE_GATE); 1446 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1447 state == AMD_CG_STATE_GATE); 1448 adev->hdp.funcs->update_clock_gating(adev, 1449 state == AMD_CG_STATE_GATE); 1450 soc15_update_drm_clock_gating(adev, 1451 state == AMD_CG_STATE_GATE); 1452 soc15_update_drm_light_sleep(adev, 1453 state == AMD_CG_STATE_GATE); 1454 break; 1455 case IP_VERSION(7, 4, 1): 1456 case IP_VERSION(7, 4, 4): 1457 adev->hdp.funcs->update_clock_gating(adev, 1458 state == AMD_CG_STATE_GATE); 1459 break; 1460 default: 1461 break; 1462 } 1463 return 0; 1464 } 1465 1466 static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1467 { 1468 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1469 int data; 1470 1471 if (amdgpu_sriov_vf(adev)) 1472 *flags = 0; 1473 1474 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1475 adev->nbio.funcs->get_clockgating_state(adev, flags); 1476 1477 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1478 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1479 1480 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1481 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && 1482 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && 1483 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { 1484 /* AMD_CG_SUPPORT_DRM_MGCG */ 1485 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1486 if (!(data & 0x01000000)) 1487 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1488 1489 /* AMD_CG_SUPPORT_DRM_LS */ 1490 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1491 if (data & 0x1) 1492 *flags |= AMD_CG_SUPPORT_DRM_LS; 1493 } 1494 1495 /* AMD_CG_SUPPORT_ROM_MGCG */ 1496 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1497 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1498 1499 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1500 adev->df.funcs->get_clockgating_state(adev, flags); 1501 } 1502 1503 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1504 enum amd_powergating_state state) 1505 { 1506 /* todo */ 1507 return 0; 1508 } 1509 1510 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1511 .name = "soc15_common", 1512 .early_init = soc15_common_early_init, 1513 .late_init = soc15_common_late_init, 1514 .sw_init = soc15_common_sw_init, 1515 .sw_fini = soc15_common_sw_fini, 1516 .hw_init = soc15_common_hw_init, 1517 .hw_fini = soc15_common_hw_fini, 1518 .suspend = soc15_common_suspend, 1519 .resume = soc15_common_resume, 1520 .is_idle = soc15_common_is_idle, 1521 .set_clockgating_state = soc15_common_set_clockgating_state, 1522 .set_powergating_state = soc15_common_set_powergating_state, 1523 .get_clockgating_state= soc15_common_get_clockgating_state, 1524 }; 1525