1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "amdgpu_ucode.h" 35 #include "amdgpu_psp.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "uvd/uvd_7_0_offset.h" 40 #include "gc/gc_9_0_offset.h" 41 #include "gc/gc_9_0_sh_mask.h" 42 #include "sdma0/sdma0_4_0_offset.h" 43 #include "sdma1/sdma1_4_0_offset.h" 44 #include "nbio/nbio_7_0_default.h" 45 #include "nbio/nbio_7_0_offset.h" 46 #include "nbio/nbio_7_0_sh_mask.h" 47 #include "nbio/nbio_7_0_smn.h" 48 #include "mp/mp_9_0_offset.h" 49 50 #include "soc15.h" 51 #include "soc15_common.h" 52 #include "gfx_v9_0.h" 53 #include "gmc_v9_0.h" 54 #include "gfxhub_v1_0.h" 55 #include "mmhub_v1_0.h" 56 #include "df_v1_7.h" 57 #include "df_v3_6.h" 58 #include "nbio_v6_1.h" 59 #include "nbio_v7_0.h" 60 #include "nbio_v7_4.h" 61 #include "hdp_v4_0.h" 62 #include "vega10_ih.h" 63 #include "vega20_ih.h" 64 #include "navi10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "smuio_v9_0.h" 74 #include "smuio_v11_0.h" 75 #include "smuio_v13_0.h" 76 #include "amdgpu_vkms.h" 77 #include "mxgpu_ai.h" 78 #include "amdgpu_ras.h" 79 #include "amdgpu_xgmi.h" 80 #include <uapi/linux/kfd_ioctl.h> 81 82 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 83 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 84 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 86 87 static const struct amd_ip_funcs soc15_common_ip_funcs; 88 89 /* Vega, Raven, Arcturus */ 90 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 91 { 92 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 94 }; 95 96 static const struct amdgpu_video_codecs vega_video_codecs_encode = 97 { 98 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 99 .codec_array = vega_video_codecs_encode_array, 100 }; 101 102 /* Vega */ 103 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 104 { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 110 }; 111 112 static const struct amdgpu_video_codecs vega_video_codecs_decode = 113 { 114 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 115 .codec_array = vega_video_codecs_decode_array, 116 }; 117 118 /* Raven */ 119 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 120 { 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 128 }; 129 130 static const struct amdgpu_video_codecs rv_video_codecs_decode = 131 { 132 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 133 .codec_array = rv_video_codecs_decode_array, 134 }; 135 136 /* Renoir, Arcturus */ 137 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 138 { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 146 }; 147 148 static const struct amdgpu_video_codecs rn_video_codecs_decode = 149 { 150 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 151 .codec_array = rn_video_codecs_decode_array, 152 }; 153 154 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 160 }; 161 162 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 163 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 164 .codec_array = vcn_4_0_3_video_codecs_decode_array, 165 }; 166 167 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 168 .codec_count = 0, 169 .codec_array = NULL, 170 }; 171 172 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = { 173 .codec_count = 0, 174 .codec_array = NULL, 175 }; 176 177 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = { 178 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 179 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 180 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 183 }; 184 185 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = { 186 .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0), 187 .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0, 188 }; 189 190 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 191 const struct amdgpu_video_codecs **codecs) 192 { 193 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 194 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 195 case IP_VERSION(4, 0, 0): 196 case IP_VERSION(4, 1, 0): 197 if (encode) 198 *codecs = &vega_video_codecs_encode; 199 else 200 *codecs = &vega_video_codecs_decode; 201 return 0; 202 default: 203 return -EINVAL; 204 } 205 } else { 206 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 207 case IP_VERSION(1, 0, 0): 208 case IP_VERSION(1, 0, 1): 209 if (encode) 210 *codecs = &vega_video_codecs_encode; 211 else 212 *codecs = &rv_video_codecs_decode; 213 return 0; 214 case IP_VERSION(2, 5, 0): 215 case IP_VERSION(2, 6, 0): 216 case IP_VERSION(2, 2, 0): 217 if (encode) 218 *codecs = &vega_video_codecs_encode; 219 else 220 *codecs = &rn_video_codecs_decode; 221 return 0; 222 case IP_VERSION(4, 0, 3): 223 if (encode) 224 *codecs = &vcn_4_0_3_video_codecs_encode; 225 else 226 *codecs = &vcn_4_0_3_video_codecs_decode; 227 return 0; 228 case IP_VERSION(5, 0, 1): 229 if (encode) 230 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0; 231 else 232 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0; 233 return 0; 234 default: 235 return -EINVAL; 236 } 237 } 238 } 239 240 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 241 { 242 unsigned long flags, address, data; 243 u32 r; 244 245 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 246 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 247 248 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 249 WREG32(address, ((reg) & 0x1ff)); 250 r = RREG32(data); 251 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 252 return r; 253 } 254 255 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 256 { 257 unsigned long flags, address, data; 258 259 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 260 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 261 262 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 263 WREG32(address, ((reg) & 0x1ff)); 264 WREG32(data, (v)); 265 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 266 } 267 268 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 269 { 270 unsigned long flags, address, data; 271 u32 r; 272 273 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 274 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 275 276 spin_lock_irqsave(&adev->reg.didt.lock, flags); 277 WREG32(address, (reg)); 278 r = RREG32(data); 279 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 280 return r; 281 } 282 283 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 284 { 285 unsigned long flags, address, data; 286 287 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 288 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 289 290 spin_lock_irqsave(&adev->reg.didt.lock, flags); 291 WREG32(address, (reg)); 292 WREG32(data, (v)); 293 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 294 } 295 296 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 297 { 298 unsigned long flags; 299 u32 r; 300 301 spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 302 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 303 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 304 spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 305 return r; 306 } 307 308 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 309 { 310 unsigned long flags; 311 312 spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 313 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 314 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 315 spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 316 } 317 318 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 319 { 320 unsigned long flags; 321 u32 r; 322 323 spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 324 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 325 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 326 spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 327 return r; 328 } 329 330 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 331 { 332 unsigned long flags; 333 334 spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 335 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 336 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 337 spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 338 } 339 340 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 341 { 342 return adev->nbio.funcs->get_memsize(adev); 343 } 344 345 static u32 soc15_get_xclk(struct amdgpu_device *adev) 346 { 347 u32 reference_clock = adev->clock.spll.reference_freq; 348 349 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || 350 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || 351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || 352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || 353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) 354 return 10000; 355 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || 356 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) 357 return reference_clock / 4; 358 359 return reference_clock; 360 } 361 362 363 void soc15_grbm_select(struct amdgpu_device *adev, 364 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 365 { 366 u32 grbm_gfx_cntl = 0; 367 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 368 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 371 372 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 373 } 374 375 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 376 { 377 /* todo */ 378 return false; 379 } 380 381 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 382 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 383 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 388 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 389 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 390 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 391 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 392 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 393 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 394 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 400 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 401 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 402 }; 403 404 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 405 bool indexed, u32 se_num, 406 u32 sh_num, u32 reg_offset) 407 { 408 if (indexed) { 409 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 410 } else { 411 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 412 return adev->gfx.config.gb_addr_config; 413 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 414 return adev->gfx.config.db_debug2; 415 return RREG32(reg_offset); 416 } 417 } 418 419 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 420 u32 sh_num, u32 reg_offset, u32 *value) 421 { 422 uint32_t i; 423 struct soc15_allowed_register_entry *en; 424 425 *value = 0; 426 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 427 en = &soc15_allowed_read_registers[i]; 428 if (!adev->reg_offset[en->hwip][en->inst]) 429 continue; 430 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 431 + en->reg_offset)) 432 continue; 433 434 *value = soc15_get_register_value(adev, 435 soc15_allowed_read_registers[i].grbm_indexed, 436 se_num, sh_num, reg_offset); 437 return 0; 438 } 439 return -EINVAL; 440 } 441 442 443 /** 444 * soc15_program_register_sequence - program an array of registers. 445 * 446 * @adev: amdgpu_device pointer 447 * @regs: pointer to the register array 448 * @array_size: size of the register array 449 * 450 * Programs an array or registers with and and or masks. 451 * This is a helper for setting golden registers. 452 */ 453 454 void soc15_program_register_sequence(struct amdgpu_device *adev, 455 const struct soc15_reg_golden *regs, 456 const u32 array_size) 457 { 458 const struct soc15_reg_golden *entry; 459 u32 tmp, reg; 460 int i; 461 462 for (i = 0; i < array_size; ++i) { 463 entry = ®s[i]; 464 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 465 466 if (entry->and_mask == 0xffffffff) { 467 tmp = entry->or_mask; 468 } else { 469 tmp = (entry->hwip == GC_HWIP) ? 470 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 471 472 tmp &= ~(entry->and_mask); 473 tmp |= (entry->or_mask & entry->and_mask); 474 } 475 476 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 477 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 478 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 479 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 480 WREG32_RLC(reg, tmp); 481 else 482 (entry->hwip == GC_HWIP) ? 483 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 484 485 } 486 487 } 488 489 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 490 { 491 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 492 int ret = 0; 493 494 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 495 if (ras && adev->ras_enabled) 496 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 497 498 ret = amdgpu_dpm_baco_reset(adev); 499 if (ret) 500 return ret; 501 502 /* re-enable doorbell interrupt after BACO exit */ 503 if (ras && adev->ras_enabled) 504 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 505 506 return 0; 507 } 508 509 static enum amd_reset_method 510 soc15_asic_reset_method(struct amdgpu_device *adev) 511 { 512 int baco_reset = 0; 513 bool connected_to_cpu = false; 514 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 515 516 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 517 connected_to_cpu = true; 518 519 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 520 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 521 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 522 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 523 /* If connected to cpu, driver only support mode2 */ 524 if (connected_to_cpu) 525 return AMD_RESET_METHOD_MODE2; 526 return amdgpu_reset_method; 527 } 528 529 if (amdgpu_reset_method != -1) 530 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 531 amdgpu_reset_method); 532 533 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 534 case IP_VERSION(10, 0, 0): 535 case IP_VERSION(10, 0, 1): 536 case IP_VERSION(12, 0, 0): 537 case IP_VERSION(12, 0, 1): 538 return AMD_RESET_METHOD_MODE2; 539 case IP_VERSION(9, 0, 0): 540 case IP_VERSION(11, 0, 2): 541 if (adev->asic_type == CHIP_VEGA20) { 542 if (adev->psp.sos.fw_version >= 0x80067) 543 baco_reset = amdgpu_dpm_is_baco_supported(adev); 544 /* 545 * 1. PMFW version > 0x284300: all cases use baco 546 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 547 */ 548 if (ras && adev->ras_enabled && 549 adev->pm.fw_version <= 0x283400) 550 baco_reset = 0; 551 } else { 552 baco_reset = amdgpu_dpm_is_baco_supported(adev); 553 } 554 break; 555 case IP_VERSION(13, 0, 2): 556 /* 557 * 1.connected to cpu: driver issue mode2 reset 558 * 2.discret gpu: driver issue mode1 reset 559 */ 560 if (connected_to_cpu) 561 return AMD_RESET_METHOD_MODE2; 562 break; 563 case IP_VERSION(13, 0, 6): 564 case IP_VERSION(13, 0, 14): 565 case IP_VERSION(13, 0, 12): 566 /* Use gpu_recovery param to target a reset method. 567 * Enable triggering of GPU reset only if specified 568 * by module parameter. 569 */ 570 if (adev->pcie_reset_ctx.in_link_reset) 571 return AMD_RESET_METHOD_LINK; 572 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 573 return AMD_RESET_METHOD_MODE2; 574 else if (!(adev->flags & AMD_IS_APU)) 575 return AMD_RESET_METHOD_MODE1; 576 else 577 return AMD_RESET_METHOD_MODE2; 578 default: 579 break; 580 } 581 582 if (baco_reset) 583 return AMD_RESET_METHOD_BACO; 584 else 585 return AMD_RESET_METHOD_MODE1; 586 } 587 588 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 589 { 590 /* Will reset for the following suspend abort cases. 591 * 1) S3 suspend aborted in the normal S3 suspend 592 * 2) S3 suspend aborted in performing pm core test. 593 */ 594 if (adev->in_s3 && !pm_resume_via_firmware()) 595 return true; 596 else 597 return false; 598 } 599 600 static int soc15_asic_reset(struct amdgpu_device *adev) 601 { 602 /* original raven doesn't have full asic reset */ 603 /* On the latest Raven, the GPU reset can be performed 604 * successfully. So now, temporarily enable it for the 605 * S3 suspend abort case. 606 */ 607 608 if ((adev->apu_flags & AMD_APU_IS_PICASSO || 609 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 610 soc15_need_reset_on_resume(adev)) 611 goto asic_reset; 612 613 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 614 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 615 return 0; 616 617 asic_reset: 618 switch (soc15_asic_reset_method(adev)) { 619 case AMD_RESET_METHOD_PCI: 620 dev_info(adev->dev, "PCI reset\n"); 621 return amdgpu_device_pci_reset(adev); 622 case AMD_RESET_METHOD_BACO: 623 dev_info(adev->dev, "BACO reset\n"); 624 return soc15_asic_baco_reset(adev); 625 case AMD_RESET_METHOD_MODE2: 626 dev_info(adev->dev, "MODE2 reset\n"); 627 return amdgpu_dpm_mode2_reset(adev); 628 case AMD_RESET_METHOD_LINK: 629 dev_info(adev->dev, "Link reset\n"); 630 return amdgpu_device_link_reset(adev); 631 default: 632 dev_info(adev->dev, "MODE1 reset\n"); 633 return amdgpu_device_mode1_reset(adev); 634 } 635 } 636 637 static int soc15_supports_baco(struct amdgpu_device *adev) 638 { 639 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 640 case IP_VERSION(9, 0, 0): 641 case IP_VERSION(11, 0, 2): 642 if (adev->asic_type == CHIP_VEGA20) { 643 if (adev->psp.sos.fw_version >= 0x80067) 644 return amdgpu_dpm_is_baco_supported(adev); 645 return 0; 646 } else { 647 return amdgpu_dpm_is_baco_supported(adev); 648 } 649 break; 650 default: 651 return 0; 652 } 653 } 654 655 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 656 u32 cntl_reg, u32 status_reg) 657 { 658 return 0; 659 }*/ 660 661 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 662 { 663 /*int r; 664 665 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 666 if (r) 667 return r; 668 669 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 670 */ 671 return 0; 672 } 673 674 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 675 { 676 /* todo */ 677 678 return 0; 679 } 680 681 const struct amdgpu_ip_block_version vega10_common_ip_block = 682 { 683 .type = AMD_IP_BLOCK_TYPE_COMMON, 684 .major = 2, 685 .minor = 0, 686 .rev = 0, 687 .funcs = &soc15_common_ip_funcs, 688 }; 689 690 static void soc15_reg_base_init(struct amdgpu_device *adev) 691 { 692 /* Set IP register base before any HW register access */ 693 switch (adev->asic_type) { 694 case CHIP_VEGA10: 695 case CHIP_VEGA12: 696 case CHIP_RAVEN: 697 case CHIP_RENOIR: 698 vega10_reg_base_init(adev); 699 break; 700 case CHIP_VEGA20: 701 vega20_reg_base_init(adev); 702 break; 703 case CHIP_ARCTURUS: 704 arct_reg_base_init(adev); 705 break; 706 case CHIP_ALDEBARAN: 707 aldebaran_reg_base_init(adev); 708 break; 709 default: 710 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 711 break; 712 } 713 } 714 715 void soc15_set_virt_ops(struct amdgpu_device *adev) 716 { 717 adev->virt.ops = &xgpu_ai_virt_ops; 718 /* init soc15 reg base early enough so we can 719 * request request full access for sriov before 720 * set_ip_blocks. */ 721 soc15_reg_base_init(adev); 722 } 723 724 static bool soc15_need_full_reset(struct amdgpu_device *adev) 725 { 726 /* change this when we implement soft reset */ 727 return true; 728 } 729 730 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 731 uint64_t *count1) 732 { 733 uint32_t perfctr = 0; 734 uint64_t cnt0_of, cnt1_of; 735 int tmp; 736 737 /* This reports 0 on APUs, so return to avoid writing/reading registers 738 * that may or may not be different from their GPU counterparts 739 */ 740 if (adev->flags & AMD_IS_APU) 741 return; 742 743 /* Set the 2 events that we wish to watch, defined above */ 744 /* Reg 40 is # received msgs */ 745 /* Reg 104 is # of posted requests sent */ 746 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 747 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 748 749 /* Write to enable desired perf counters */ 750 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 751 /* Zero out and enable the perf counters 752 * Write 0x5: 753 * Bit 0 = Start all counters(1) 754 * Bit 2 = Global counter reset enable(1) 755 */ 756 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 757 758 msleep(1000); 759 760 /* Load the shadow and disable the perf counters 761 * Write 0x2: 762 * Bit 0 = Stop counters(0) 763 * Bit 1 = Load the shadow counters(1) 764 */ 765 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 766 767 /* Read register values to get any >32bit overflow */ 768 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 769 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 770 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 771 772 /* Get the values and add the overflow */ 773 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 774 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 775 } 776 777 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 778 uint64_t *count1) 779 { 780 uint32_t perfctr = 0; 781 uint64_t cnt0_of, cnt1_of; 782 int tmp; 783 784 /* This reports 0 on APUs, so return to avoid writing/reading registers 785 * that may or may not be different from their GPU counterparts 786 */ 787 if (adev->flags & AMD_IS_APU) 788 return; 789 790 /* Set the 2 events that we wish to watch, defined above */ 791 /* Reg 40 is # received msgs */ 792 /* Reg 108 is # of posted requests sent on VG20 */ 793 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 794 EVENT0_SEL, 40); 795 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 796 EVENT1_SEL, 108); 797 798 /* Write to enable desired perf counters */ 799 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 800 /* Zero out and enable the perf counters 801 * Write 0x5: 802 * Bit 0 = Start all counters(1) 803 * Bit 2 = Global counter reset enable(1) 804 */ 805 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 806 807 msleep(1000); 808 809 /* Load the shadow and disable the perf counters 810 * Write 0x2: 811 * Bit 0 = Stop counters(0) 812 * Bit 1 = Load the shadow counters(1) 813 */ 814 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 815 816 /* Read register values to get any >32bit overflow */ 817 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 818 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 819 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 820 821 /* Get the values and add the overflow */ 822 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 823 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 824 } 825 826 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 827 { 828 u32 sol_reg; 829 830 if (amdgpu_gmc_need_reset_on_init(adev)) 831 return true; 832 if (amdgpu_psp_tos_reload_needed(adev)) 833 return true; 834 /* Just return false for soc15 GPUs. Reset does not seem to 835 * be necessary. 836 */ 837 if (!amdgpu_passthrough(adev)) 838 return false; 839 840 if (adev->flags & AMD_IS_APU) 841 return false; 842 843 /* Check sOS sign of life register to confirm sys driver and sOS 844 * are already been loaded. 845 */ 846 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 847 if (sol_reg) 848 return true; 849 850 return false; 851 } 852 853 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 854 { 855 uint64_t nak_r, nak_g; 856 857 /* Get the number of NAKs received and generated */ 858 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 859 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 860 861 /* Add the total number of NAKs, i.e the number of replays */ 862 return (nak_r + nak_g); 863 } 864 865 static void soc15_pre_asic_init(struct amdgpu_device *adev) 866 { 867 gmc_v9_0_restore_registers(adev); 868 } 869 870 static const struct amdgpu_asic_funcs soc15_asic_funcs = 871 { 872 .read_disabled_bios = &soc15_read_disabled_bios, 873 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 874 .read_register = &soc15_read_register, 875 .reset = &soc15_asic_reset, 876 .reset_method = &soc15_asic_reset_method, 877 .get_xclk = &soc15_get_xclk, 878 .set_uvd_clocks = &soc15_set_uvd_clocks, 879 .set_vce_clocks = &soc15_set_vce_clocks, 880 .get_config_memsize = &soc15_get_config_memsize, 881 .need_full_reset = &soc15_need_full_reset, 882 .init_doorbell_index = &vega10_doorbell_index_init, 883 .get_pcie_usage = &soc15_get_pcie_usage, 884 .need_reset_on_init = &soc15_need_reset_on_init, 885 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 886 .supports_baco = &soc15_supports_baco, 887 .pre_asic_init = &soc15_pre_asic_init, 888 .query_video_codecs = &soc15_query_video_codecs, 889 }; 890 891 static const struct amdgpu_asic_funcs vega20_asic_funcs = 892 { 893 .read_disabled_bios = &soc15_read_disabled_bios, 894 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 895 .read_register = &soc15_read_register, 896 .reset = &soc15_asic_reset, 897 .reset_method = &soc15_asic_reset_method, 898 .get_xclk = &soc15_get_xclk, 899 .set_uvd_clocks = &soc15_set_uvd_clocks, 900 .set_vce_clocks = &soc15_set_vce_clocks, 901 .get_config_memsize = &soc15_get_config_memsize, 902 .need_full_reset = &soc15_need_full_reset, 903 .init_doorbell_index = &vega20_doorbell_index_init, 904 .get_pcie_usage = &vega20_get_pcie_usage, 905 .need_reset_on_init = &soc15_need_reset_on_init, 906 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 907 .supports_baco = &soc15_supports_baco, 908 .pre_asic_init = &soc15_pre_asic_init, 909 .query_video_codecs = &soc15_query_video_codecs, 910 }; 911 912 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 913 { 914 .read_disabled_bios = &soc15_read_disabled_bios, 915 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 916 .read_register = &soc15_read_register, 917 .reset = &soc15_asic_reset, 918 .reset_method = &soc15_asic_reset_method, 919 .get_xclk = &soc15_get_xclk, 920 .set_uvd_clocks = &soc15_set_uvd_clocks, 921 .set_vce_clocks = &soc15_set_vce_clocks, 922 .get_config_memsize = &soc15_get_config_memsize, 923 .need_full_reset = &soc15_need_full_reset, 924 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 925 .need_reset_on_init = &soc15_need_reset_on_init, 926 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 927 .supports_baco = &soc15_supports_baco, 928 .query_video_codecs = &soc15_query_video_codecs, 929 .get_reg_state = &aqua_vanjaram_get_reg_state, 930 }; 931 932 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) 933 { 934 struct amdgpu_device *adev = ip_block->adev; 935 936 adev->nbio.funcs->set_reg_remap(adev); 937 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 938 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 939 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 940 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 941 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 942 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 943 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 944 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 945 adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; 946 adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 947 adev->reg.didt.rreg = &soc15_didt_rreg; 948 adev->reg.didt.wreg = &soc15_didt_wreg; 949 adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; 950 adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; 951 adev->reg.se_cac.rreg = &soc15_se_cac_rreg; 952 adev->reg.se_cac.wreg = &soc15_se_cac_wreg; 953 954 adev->rev_id = amdgpu_device_get_rev_id(adev); 955 adev->external_rev_id = 0xFF; 956 /* TODO: split the GC and PG flags based on the relevant IP version for which 957 * they are relevant. 958 */ 959 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 960 case IP_VERSION(9, 0, 1): 961 adev->asic_funcs = &soc15_asic_funcs; 962 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 963 AMD_CG_SUPPORT_GFX_MGLS | 964 AMD_CG_SUPPORT_GFX_RLC_LS | 965 AMD_CG_SUPPORT_GFX_CP_LS | 966 AMD_CG_SUPPORT_GFX_3D_CGCG | 967 AMD_CG_SUPPORT_GFX_3D_CGLS | 968 AMD_CG_SUPPORT_GFX_CGCG | 969 AMD_CG_SUPPORT_GFX_CGLS | 970 AMD_CG_SUPPORT_BIF_MGCG | 971 AMD_CG_SUPPORT_BIF_LS | 972 AMD_CG_SUPPORT_HDP_LS | 973 AMD_CG_SUPPORT_DRM_MGCG | 974 AMD_CG_SUPPORT_DRM_LS | 975 AMD_CG_SUPPORT_ROM_MGCG | 976 AMD_CG_SUPPORT_DF_MGCG | 977 AMD_CG_SUPPORT_SDMA_MGCG | 978 AMD_CG_SUPPORT_SDMA_LS | 979 AMD_CG_SUPPORT_MC_MGCG | 980 AMD_CG_SUPPORT_MC_LS; 981 adev->pg_flags = 0; 982 adev->external_rev_id = 0x1; 983 break; 984 case IP_VERSION(9, 2, 1): 985 adev->asic_funcs = &soc15_asic_funcs; 986 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 987 AMD_CG_SUPPORT_GFX_MGLS | 988 AMD_CG_SUPPORT_GFX_CGCG | 989 AMD_CG_SUPPORT_GFX_CGLS | 990 AMD_CG_SUPPORT_GFX_3D_CGCG | 991 AMD_CG_SUPPORT_GFX_3D_CGLS | 992 AMD_CG_SUPPORT_GFX_CP_LS | 993 AMD_CG_SUPPORT_MC_LS | 994 AMD_CG_SUPPORT_MC_MGCG | 995 AMD_CG_SUPPORT_SDMA_MGCG | 996 AMD_CG_SUPPORT_SDMA_LS | 997 AMD_CG_SUPPORT_BIF_MGCG | 998 AMD_CG_SUPPORT_BIF_LS | 999 AMD_CG_SUPPORT_HDP_MGCG | 1000 AMD_CG_SUPPORT_HDP_LS | 1001 AMD_CG_SUPPORT_ROM_MGCG | 1002 AMD_CG_SUPPORT_VCE_MGCG | 1003 AMD_CG_SUPPORT_UVD_MGCG; 1004 adev->pg_flags = 0; 1005 adev->external_rev_id = adev->rev_id + 0x14; 1006 break; 1007 case IP_VERSION(9, 4, 0): 1008 adev->asic_funcs = &vega20_asic_funcs; 1009 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1010 AMD_CG_SUPPORT_GFX_MGLS | 1011 AMD_CG_SUPPORT_GFX_CGCG | 1012 AMD_CG_SUPPORT_GFX_CGLS | 1013 AMD_CG_SUPPORT_GFX_3D_CGCG | 1014 AMD_CG_SUPPORT_GFX_3D_CGLS | 1015 AMD_CG_SUPPORT_GFX_CP_LS | 1016 AMD_CG_SUPPORT_MC_LS | 1017 AMD_CG_SUPPORT_MC_MGCG | 1018 AMD_CG_SUPPORT_SDMA_MGCG | 1019 AMD_CG_SUPPORT_SDMA_LS | 1020 AMD_CG_SUPPORT_BIF_MGCG | 1021 AMD_CG_SUPPORT_BIF_LS | 1022 AMD_CG_SUPPORT_HDP_MGCG | 1023 AMD_CG_SUPPORT_HDP_LS | 1024 AMD_CG_SUPPORT_ROM_MGCG | 1025 AMD_CG_SUPPORT_VCE_MGCG | 1026 AMD_CG_SUPPORT_UVD_MGCG; 1027 adev->pg_flags = 0; 1028 adev->external_rev_id = adev->rev_id + 0x28; 1029 break; 1030 case IP_VERSION(9, 1, 0): 1031 case IP_VERSION(9, 2, 2): 1032 adev->asic_funcs = &soc15_asic_funcs; 1033 1034 if (adev->rev_id >= 0x8) 1035 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1036 1037 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1038 adev->external_rev_id = adev->rev_id + 0x79; 1039 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1040 adev->external_rev_id = adev->rev_id + 0x41; 1041 else if (adev->rev_id == 1) 1042 adev->external_rev_id = adev->rev_id + 0x20; 1043 else 1044 adev->external_rev_id = adev->rev_id + 0x01; 1045 1046 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1047 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1048 AMD_CG_SUPPORT_GFX_MGLS | 1049 AMD_CG_SUPPORT_GFX_CP_LS | 1050 AMD_CG_SUPPORT_GFX_3D_CGCG | 1051 AMD_CG_SUPPORT_GFX_3D_CGLS | 1052 AMD_CG_SUPPORT_GFX_CGCG | 1053 AMD_CG_SUPPORT_GFX_CGLS | 1054 AMD_CG_SUPPORT_BIF_LS | 1055 AMD_CG_SUPPORT_HDP_LS | 1056 AMD_CG_SUPPORT_MC_MGCG | 1057 AMD_CG_SUPPORT_MC_LS | 1058 AMD_CG_SUPPORT_SDMA_MGCG | 1059 AMD_CG_SUPPORT_SDMA_LS | 1060 AMD_CG_SUPPORT_VCN_MGCG; 1061 1062 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1063 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1064 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1065 AMD_CG_SUPPORT_GFX_MGLS | 1066 AMD_CG_SUPPORT_GFX_CP_LS | 1067 AMD_CG_SUPPORT_GFX_3D_CGLS | 1068 AMD_CG_SUPPORT_GFX_CGCG | 1069 AMD_CG_SUPPORT_GFX_CGLS | 1070 AMD_CG_SUPPORT_BIF_LS | 1071 AMD_CG_SUPPORT_HDP_LS | 1072 AMD_CG_SUPPORT_MC_MGCG | 1073 AMD_CG_SUPPORT_MC_LS | 1074 AMD_CG_SUPPORT_SDMA_MGCG | 1075 AMD_CG_SUPPORT_SDMA_LS | 1076 AMD_CG_SUPPORT_VCN_MGCG; 1077 1078 /* 1079 * MMHUB PG needs to be disabled for Picasso for 1080 * stability reasons. 1081 */ 1082 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1083 AMD_PG_SUPPORT_VCN; 1084 } else { 1085 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1086 AMD_CG_SUPPORT_GFX_MGLS | 1087 AMD_CG_SUPPORT_GFX_RLC_LS | 1088 AMD_CG_SUPPORT_GFX_CP_LS | 1089 AMD_CG_SUPPORT_GFX_3D_CGLS | 1090 AMD_CG_SUPPORT_GFX_CGCG | 1091 AMD_CG_SUPPORT_GFX_CGLS | 1092 AMD_CG_SUPPORT_BIF_MGCG | 1093 AMD_CG_SUPPORT_BIF_LS | 1094 AMD_CG_SUPPORT_HDP_MGCG | 1095 AMD_CG_SUPPORT_HDP_LS | 1096 AMD_CG_SUPPORT_DRM_MGCG | 1097 AMD_CG_SUPPORT_DRM_LS | 1098 AMD_CG_SUPPORT_MC_MGCG | 1099 AMD_CG_SUPPORT_MC_LS | 1100 AMD_CG_SUPPORT_SDMA_MGCG | 1101 AMD_CG_SUPPORT_SDMA_LS | 1102 AMD_CG_SUPPORT_VCN_MGCG; 1103 1104 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1105 } 1106 break; 1107 case IP_VERSION(9, 4, 1): 1108 adev->asic_funcs = &vega20_asic_funcs; 1109 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1110 AMD_CG_SUPPORT_GFX_MGLS | 1111 AMD_CG_SUPPORT_GFX_CGCG | 1112 AMD_CG_SUPPORT_GFX_CGLS | 1113 AMD_CG_SUPPORT_GFX_CP_LS | 1114 AMD_CG_SUPPORT_HDP_MGCG | 1115 AMD_CG_SUPPORT_HDP_LS | 1116 AMD_CG_SUPPORT_SDMA_MGCG | 1117 AMD_CG_SUPPORT_SDMA_LS | 1118 AMD_CG_SUPPORT_MC_MGCG | 1119 AMD_CG_SUPPORT_MC_LS | 1120 AMD_CG_SUPPORT_IH_CG | 1121 AMD_CG_SUPPORT_VCN_MGCG | 1122 AMD_CG_SUPPORT_JPEG_MGCG; 1123 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1124 adev->external_rev_id = adev->rev_id + 0x32; 1125 break; 1126 case IP_VERSION(9, 3, 0): 1127 adev->asic_funcs = &soc15_asic_funcs; 1128 1129 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1130 adev->external_rev_id = adev->rev_id + 0x91; 1131 else 1132 adev->external_rev_id = adev->rev_id + 0xa1; 1133 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1134 AMD_CG_SUPPORT_GFX_MGLS | 1135 AMD_CG_SUPPORT_GFX_3D_CGCG | 1136 AMD_CG_SUPPORT_GFX_3D_CGLS | 1137 AMD_CG_SUPPORT_GFX_CGCG | 1138 AMD_CG_SUPPORT_GFX_CGLS | 1139 AMD_CG_SUPPORT_GFX_CP_LS | 1140 AMD_CG_SUPPORT_MC_MGCG | 1141 AMD_CG_SUPPORT_MC_LS | 1142 AMD_CG_SUPPORT_SDMA_MGCG | 1143 AMD_CG_SUPPORT_SDMA_LS | 1144 AMD_CG_SUPPORT_BIF_LS | 1145 AMD_CG_SUPPORT_HDP_LS | 1146 AMD_CG_SUPPORT_VCN_MGCG | 1147 AMD_CG_SUPPORT_JPEG_MGCG | 1148 AMD_CG_SUPPORT_IH_CG | 1149 AMD_CG_SUPPORT_ATHUB_LS | 1150 AMD_CG_SUPPORT_ATHUB_MGCG | 1151 AMD_CG_SUPPORT_DF_MGCG; 1152 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1153 AMD_PG_SUPPORT_VCN | 1154 AMD_PG_SUPPORT_JPEG | 1155 AMD_PG_SUPPORT_VCN_DPG; 1156 break; 1157 case IP_VERSION(9, 4, 2): 1158 adev->asic_funcs = &vega20_asic_funcs; 1159 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1160 AMD_CG_SUPPORT_GFX_MGLS | 1161 AMD_CG_SUPPORT_GFX_CP_LS | 1162 AMD_CG_SUPPORT_HDP_LS | 1163 AMD_CG_SUPPORT_SDMA_MGCG | 1164 AMD_CG_SUPPORT_SDMA_LS | 1165 AMD_CG_SUPPORT_IH_CG | 1166 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1167 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1168 adev->external_rev_id = adev->rev_id + 0x3c; 1169 break; 1170 case IP_VERSION(9, 4, 3): 1171 case IP_VERSION(9, 4, 4): 1172 case IP_VERSION(9, 5, 0): 1173 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1174 adev->reg.smn.get_smn_base = &amdgpu_reg_smn_v1_0_get_base; 1175 adev->cg_flags = 1176 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1177 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1178 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1179 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1180 AMD_CG_SUPPORT_IH_CG; 1181 adev->pg_flags = 1182 AMD_PG_SUPPORT_VCN | 1183 AMD_PG_SUPPORT_VCN_DPG | 1184 AMD_PG_SUPPORT_JPEG; 1185 /*TODO: need a new external_rev_id for GC 9.4.4? */ 1186 adev->external_rev_id = adev->rev_id + 0x46; 1187 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1188 adev->external_rev_id = adev->rev_id + 0x50; 1189 break; 1190 default: 1191 /* FIXME: not supported yet */ 1192 return -EINVAL; 1193 } 1194 1195 if (amdgpu_sriov_vf(adev)) { 1196 amdgpu_virt_init_setting(adev); 1197 xgpu_ai_mailbox_set_irq_funcs(adev); 1198 } 1199 1200 return 0; 1201 } 1202 1203 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) 1204 { 1205 struct amdgpu_device *adev = ip_block->adev; 1206 1207 if (amdgpu_sriov_vf(adev)) 1208 xgpu_ai_mailbox_get_irq(adev); 1209 1210 /* Enable selfring doorbell aperture late because doorbell BAR 1211 * aperture will change if resize BAR successfully in gmc sw_init. 1212 */ 1213 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1214 1215 return 0; 1216 } 1217 1218 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) 1219 { 1220 struct amdgpu_device *adev = ip_block->adev; 1221 1222 if (amdgpu_sriov_vf(adev)) 1223 xgpu_ai_mailbox_add_irq_id(adev); 1224 1225 if (adev->df.funcs && 1226 adev->df.funcs->sw_init) 1227 adev->df.funcs->sw_init(adev); 1228 1229 return 0; 1230 } 1231 1232 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) 1233 { 1234 struct amdgpu_device *adev = ip_block->adev; 1235 1236 if (adev->df.funcs && 1237 adev->df.funcs->sw_fini) 1238 adev->df.funcs->sw_fini(adev); 1239 return 0; 1240 } 1241 1242 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1243 { 1244 int i; 1245 1246 /* sdma doorbell range is programed by hypervisor */ 1247 if (!amdgpu_sriov_vf(adev)) { 1248 for (i = 0; i < adev->sdma.num_instances; i++) { 1249 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1250 true, adev->doorbell_index.sdma_engine[i] << 1, 1251 adev->doorbell_index.sdma_doorbell_range); 1252 } 1253 } 1254 } 1255 1256 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) 1257 { 1258 struct amdgpu_device *adev = ip_block->adev; 1259 1260 /* enable aspm */ 1261 amdgpu_nbio_program_aspm(adev); 1262 /* setup nbio registers */ 1263 adev->nbio.funcs->init_registers(adev); 1264 /* remap HDP registers to a hole in mmio space, 1265 * for the purpose of expose those registers 1266 * to process space 1267 */ 1268 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1269 adev->nbio.funcs->remap_hdp_registers(adev); 1270 1271 /* enable the doorbell aperture */ 1272 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1273 1274 /* HW doorbell routing policy: doorbell writing not 1275 * in SDMA/IH/MM/ACV range will be routed to CP. So 1276 * we need to init SDMA doorbell range prior 1277 * to CP ip block init and ring test. IH already 1278 * happens before CP. 1279 */ 1280 soc15_sdma_doorbell_range_init(adev); 1281 1282 return 0; 1283 } 1284 1285 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) 1286 { 1287 struct amdgpu_device *adev = ip_block->adev; 1288 1289 /* Disable the doorbell aperture and selfring doorbell aperture 1290 * separately in hw_fini because soc15_enable_doorbell_aperture 1291 * has been removed and there is no need to delay disabling 1292 * selfring doorbell. 1293 */ 1294 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1295 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1296 1297 if (amdgpu_sriov_vf(adev)) 1298 xgpu_ai_mailbox_put_irq(adev); 1299 1300 /* 1301 * For minimal init, late_init is not called, hence RAS irqs are not 1302 * enabled. 1303 */ 1304 if ((!amdgpu_sriov_vf(adev)) && 1305 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1306 adev->nbio.ras_if && 1307 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1308 if (adev->nbio.ras && 1309 adev->nbio.ras->init_ras_controller_interrupt) 1310 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1311 if (adev->nbio.ras && 1312 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1313 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1314 } 1315 1316 return 0; 1317 } 1318 1319 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) 1320 { 1321 return soc15_common_hw_fini(ip_block); 1322 } 1323 1324 static int soc15_common_resume(struct amdgpu_ip_block *ip_block) 1325 { 1326 struct amdgpu_device *adev = ip_block->adev; 1327 1328 if (soc15_need_reset_on_resume(adev)) { 1329 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); 1330 soc15_asic_reset(adev); 1331 } 1332 return soc15_common_hw_init(ip_block); 1333 } 1334 1335 static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block) 1336 { 1337 return true; 1338 } 1339 1340 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1341 { 1342 uint32_t def, data; 1343 1344 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1345 1346 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1347 data &= ~(0x01000000 | 1348 0x02000000 | 1349 0x04000000 | 1350 0x08000000 | 1351 0x10000000 | 1352 0x20000000 | 1353 0x40000000 | 1354 0x80000000); 1355 else 1356 data |= (0x01000000 | 1357 0x02000000 | 1358 0x04000000 | 1359 0x08000000 | 1360 0x10000000 | 1361 0x20000000 | 1362 0x40000000 | 1363 0x80000000); 1364 1365 if (def != data) 1366 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1367 } 1368 1369 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1370 { 1371 uint32_t def, data; 1372 1373 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1374 1375 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1376 data |= 1; 1377 else 1378 data &= ~1; 1379 1380 if (def != data) 1381 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1382 } 1383 1384 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1385 enum amd_clockgating_state state) 1386 { 1387 struct amdgpu_device *adev = ip_block->adev; 1388 1389 if (amdgpu_sriov_vf(adev)) 1390 return 0; 1391 1392 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1393 case IP_VERSION(6, 1, 0): 1394 case IP_VERSION(6, 2, 0): 1395 case IP_VERSION(7, 4, 0): 1396 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1397 state == AMD_CG_STATE_GATE); 1398 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1399 state == AMD_CG_STATE_GATE); 1400 adev->hdp.funcs->update_clock_gating(adev, 1401 state == AMD_CG_STATE_GATE); 1402 soc15_update_drm_clock_gating(adev, 1403 state == AMD_CG_STATE_GATE); 1404 soc15_update_drm_light_sleep(adev, 1405 state == AMD_CG_STATE_GATE); 1406 adev->smuio.funcs->update_rom_clock_gating(adev, 1407 state == AMD_CG_STATE_GATE); 1408 adev->df.funcs->update_medium_grain_clock_gating(adev, 1409 state == AMD_CG_STATE_GATE); 1410 break; 1411 case IP_VERSION(7, 0, 0): 1412 case IP_VERSION(7, 0, 1): 1413 case IP_VERSION(2, 5, 0): 1414 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1415 state == AMD_CG_STATE_GATE); 1416 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1417 state == AMD_CG_STATE_GATE); 1418 adev->hdp.funcs->update_clock_gating(adev, 1419 state == AMD_CG_STATE_GATE); 1420 soc15_update_drm_clock_gating(adev, 1421 state == AMD_CG_STATE_GATE); 1422 soc15_update_drm_light_sleep(adev, 1423 state == AMD_CG_STATE_GATE); 1424 break; 1425 case IP_VERSION(7, 4, 1): 1426 case IP_VERSION(7, 4, 4): 1427 adev->hdp.funcs->update_clock_gating(adev, 1428 state == AMD_CG_STATE_GATE); 1429 break; 1430 default: 1431 break; 1432 } 1433 return 0; 1434 } 1435 1436 static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1437 { 1438 struct amdgpu_device *adev = ip_block->adev; 1439 int data; 1440 1441 if (amdgpu_sriov_vf(adev)) 1442 *flags = 0; 1443 1444 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1445 adev->nbio.funcs->get_clockgating_state(adev, flags); 1446 1447 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1448 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1449 1450 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1451 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && 1452 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && 1453 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) && 1454 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 15))) { 1455 /* AMD_CG_SUPPORT_DRM_MGCG */ 1456 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1457 if (!(data & 0x01000000)) 1458 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1459 1460 /* AMD_CG_SUPPORT_DRM_LS */ 1461 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1462 if (data & 0x1) 1463 *flags |= AMD_CG_SUPPORT_DRM_LS; 1464 } 1465 1466 /* AMD_CG_SUPPORT_ROM_MGCG */ 1467 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1468 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1469 1470 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1471 adev->df.funcs->get_clockgating_state(adev, flags); 1472 } 1473 1474 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1475 enum amd_powergating_state state) 1476 { 1477 /* todo */ 1478 return 0; 1479 } 1480 1481 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1482 .name = "soc15_common", 1483 .early_init = soc15_common_early_init, 1484 .late_init = soc15_common_late_init, 1485 .sw_init = soc15_common_sw_init, 1486 .sw_fini = soc15_common_sw_fini, 1487 .hw_init = soc15_common_hw_init, 1488 .hw_fini = soc15_common_hw_fini, 1489 .suspend = soc15_common_suspend, 1490 .resume = soc15_common_resume, 1491 .is_idle = soc15_common_is_idle, 1492 .set_clockgating_state = soc15_common_set_clockgating_state, 1493 .set_powergating_state = soc15_common_set_powergating_state, 1494 .get_clockgating_state= soc15_common_get_clockgating_state, 1495 }; 1496