1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "amdgpu_ucode.h" 35 #include "amdgpu_psp.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "uvd/uvd_7_0_offset.h" 40 #include "gc/gc_9_0_offset.h" 41 #include "gc/gc_9_0_sh_mask.h" 42 #include "sdma0/sdma0_4_0_offset.h" 43 #include "sdma1/sdma1_4_0_offset.h" 44 #include "nbio/nbio_7_0_default.h" 45 #include "nbio/nbio_7_0_offset.h" 46 #include "nbio/nbio_7_0_sh_mask.h" 47 #include "nbio/nbio_7_0_smn.h" 48 #include "mp/mp_9_0_offset.h" 49 50 #include "soc15.h" 51 #include "soc15_common.h" 52 #include "gfx_v9_0.h" 53 #include "gmc_v9_0.h" 54 #include "gfxhub_v1_0.h" 55 #include "mmhub_v1_0.h" 56 #include "df_v1_7.h" 57 #include "df_v3_6.h" 58 #include "nbio_v6_1.h" 59 #include "nbio_v7_0.h" 60 #include "nbio_v7_4.h" 61 #include "hdp_v4_0.h" 62 #include "vega10_ih.h" 63 #include "vega20_ih.h" 64 #include "navi10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "smuio_v9_0.h" 74 #include "smuio_v11_0.h" 75 #include "smuio_v13_0.h" 76 #include "amdgpu_vkms.h" 77 #include "mxgpu_ai.h" 78 #include "amdgpu_ras.h" 79 #include "amdgpu_xgmi.h" 80 #include <uapi/linux/kfd_ioctl.h> 81 82 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 83 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 84 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 86 87 static const struct amd_ip_funcs soc15_common_ip_funcs; 88 89 /* Vega, Raven, Arcturus */ 90 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 91 { 92 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 94 }; 95 96 static const struct amdgpu_video_codecs vega_video_codecs_encode = 97 { 98 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 99 .codec_array = vega_video_codecs_encode_array, 100 }; 101 102 /* Vega */ 103 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 104 { 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs vega_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 116 .codec_array = vega_video_codecs_decode_array, 117 }; 118 119 /* Raven */ 120 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 129 }; 130 131 static const struct amdgpu_video_codecs rv_video_codecs_decode = 132 { 133 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 134 .codec_array = rv_video_codecs_decode_array, 135 }; 136 137 /* Renoir, Arcturus */ 138 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 139 { 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 147 }; 148 149 static const struct amdgpu_video_codecs rn_video_codecs_decode = 150 { 151 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 152 .codec_array = rn_video_codecs_decode_array, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 164 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 165 .codec_array = vcn_4_0_3_video_codecs_decode_array, 166 }; 167 168 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 169 .codec_count = 0, 170 .codec_array = NULL, 171 }; 172 173 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = { 174 .codec_count = 0, 175 .codec_array = NULL, 176 }; 177 178 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = { 179 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 180 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 184 }; 185 186 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = { 187 .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0), 188 .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0, 189 }; 190 191 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 192 const struct amdgpu_video_codecs **codecs) 193 { 194 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 195 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 196 case IP_VERSION(4, 0, 0): 197 case IP_VERSION(4, 1, 0): 198 if (encode) 199 *codecs = &vega_video_codecs_encode; 200 else 201 *codecs = &vega_video_codecs_decode; 202 return 0; 203 default: 204 return -EINVAL; 205 } 206 } else { 207 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 208 case IP_VERSION(1, 0, 0): 209 case IP_VERSION(1, 0, 1): 210 if (encode) 211 *codecs = &vega_video_codecs_encode; 212 else 213 *codecs = &rv_video_codecs_decode; 214 return 0; 215 case IP_VERSION(2, 5, 0): 216 case IP_VERSION(2, 6, 0): 217 case IP_VERSION(2, 2, 0): 218 if (encode) 219 *codecs = &vega_video_codecs_encode; 220 else 221 *codecs = &rn_video_codecs_decode; 222 return 0; 223 case IP_VERSION(4, 0, 3): 224 if (encode) 225 *codecs = &vcn_4_0_3_video_codecs_encode; 226 else 227 *codecs = &vcn_4_0_3_video_codecs_decode; 228 return 0; 229 case IP_VERSION(5, 0, 1): 230 if (encode) 231 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0; 232 else 233 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0; 234 return 0; 235 default: 236 return -EINVAL; 237 } 238 } 239 } 240 241 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 242 { 243 unsigned long flags, address, data; 244 u32 r; 245 246 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 247 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 248 249 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 250 WREG32(address, ((reg) & 0x1ff)); 251 r = RREG32(data); 252 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 253 return r; 254 } 255 256 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 257 { 258 unsigned long flags, address, data; 259 260 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 261 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 262 263 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 264 WREG32(address, ((reg) & 0x1ff)); 265 WREG32(data, (v)); 266 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 267 } 268 269 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 270 { 271 unsigned long flags, address, data; 272 u32 r; 273 274 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 275 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 276 277 spin_lock_irqsave(&adev->didt_idx_lock, flags); 278 WREG32(address, (reg)); 279 r = RREG32(data); 280 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 281 return r; 282 } 283 284 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 285 { 286 unsigned long flags, address, data; 287 288 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 289 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 290 291 spin_lock_irqsave(&adev->didt_idx_lock, flags); 292 WREG32(address, (reg)); 293 WREG32(data, (v)); 294 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 295 } 296 297 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 298 { 299 unsigned long flags; 300 u32 r; 301 302 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 303 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 304 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 305 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 306 return r; 307 } 308 309 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 310 { 311 unsigned long flags; 312 313 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 314 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 315 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 316 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 317 } 318 319 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 320 { 321 unsigned long flags; 322 u32 r; 323 324 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 325 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 326 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 327 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 328 return r; 329 } 330 331 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 332 { 333 unsigned long flags; 334 335 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 336 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 337 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 338 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 339 } 340 341 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 342 { 343 return adev->nbio.funcs->get_memsize(adev); 344 } 345 346 static u32 soc15_get_xclk(struct amdgpu_device *adev) 347 { 348 u32 reference_clock = adev->clock.spll.reference_freq; 349 350 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || 351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || 352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || 353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || 354 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) 355 return 10000; 356 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || 357 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) 358 return reference_clock / 4; 359 360 return reference_clock; 361 } 362 363 364 void soc15_grbm_select(struct amdgpu_device *adev, 365 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 366 { 367 u32 grbm_gfx_cntl = 0; 368 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 371 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 372 373 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 374 } 375 376 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 377 { 378 /* todo */ 379 return false; 380 } 381 382 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 383 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 389 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 390 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 391 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 392 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 393 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 394 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 400 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 401 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 402 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 403 }; 404 405 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 406 u32 sh_num, u32 reg_offset) 407 { 408 uint32_t val; 409 410 mutex_lock(&adev->grbm_idx_mutex); 411 if (se_num != 0xffffffff || sh_num != 0xffffffff) 412 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 413 414 val = RREG32(reg_offset); 415 416 if (se_num != 0xffffffff || sh_num != 0xffffffff) 417 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 418 mutex_unlock(&adev->grbm_idx_mutex); 419 return val; 420 } 421 422 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 423 bool indexed, u32 se_num, 424 u32 sh_num, u32 reg_offset) 425 { 426 if (indexed) { 427 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 428 } else { 429 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 430 return adev->gfx.config.gb_addr_config; 431 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 432 return adev->gfx.config.db_debug2; 433 return RREG32(reg_offset); 434 } 435 } 436 437 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 438 u32 sh_num, u32 reg_offset, u32 *value) 439 { 440 uint32_t i; 441 struct soc15_allowed_register_entry *en; 442 443 *value = 0; 444 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 445 en = &soc15_allowed_read_registers[i]; 446 if (!adev->reg_offset[en->hwip][en->inst]) 447 continue; 448 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 449 + en->reg_offset)) 450 continue; 451 452 *value = soc15_get_register_value(adev, 453 soc15_allowed_read_registers[i].grbm_indexed, 454 se_num, sh_num, reg_offset); 455 return 0; 456 } 457 return -EINVAL; 458 } 459 460 461 /** 462 * soc15_program_register_sequence - program an array of registers. 463 * 464 * @adev: amdgpu_device pointer 465 * @regs: pointer to the register array 466 * @array_size: size of the register array 467 * 468 * Programs an array or registers with and and or masks. 469 * This is a helper for setting golden registers. 470 */ 471 472 void soc15_program_register_sequence(struct amdgpu_device *adev, 473 const struct soc15_reg_golden *regs, 474 const u32 array_size) 475 { 476 const struct soc15_reg_golden *entry; 477 u32 tmp, reg; 478 int i; 479 480 for (i = 0; i < array_size; ++i) { 481 entry = ®s[i]; 482 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 483 484 if (entry->and_mask == 0xffffffff) { 485 tmp = entry->or_mask; 486 } else { 487 tmp = (entry->hwip == GC_HWIP) ? 488 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 489 490 tmp &= ~(entry->and_mask); 491 tmp |= (entry->or_mask & entry->and_mask); 492 } 493 494 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 495 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 496 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 497 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 498 WREG32_RLC(reg, tmp); 499 else 500 (entry->hwip == GC_HWIP) ? 501 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 502 503 } 504 505 } 506 507 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 508 { 509 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 510 int ret = 0; 511 512 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 513 if (ras && adev->ras_enabled) 514 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 515 516 ret = amdgpu_dpm_baco_reset(adev); 517 if (ret) 518 return ret; 519 520 /* re-enable doorbell interrupt after BACO exit */ 521 if (ras && adev->ras_enabled) 522 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 523 524 return 0; 525 } 526 527 static enum amd_reset_method 528 soc15_asic_reset_method(struct amdgpu_device *adev) 529 { 530 int baco_reset = 0; 531 bool connected_to_cpu = false; 532 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 533 534 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 535 connected_to_cpu = true; 536 537 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 538 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 539 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 540 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 541 /* If connected to cpu, driver only support mode2 */ 542 if (connected_to_cpu) 543 return AMD_RESET_METHOD_MODE2; 544 return amdgpu_reset_method; 545 } 546 547 if (amdgpu_reset_method != -1) 548 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 549 amdgpu_reset_method); 550 551 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 552 case IP_VERSION(10, 0, 0): 553 case IP_VERSION(10, 0, 1): 554 case IP_VERSION(12, 0, 0): 555 case IP_VERSION(12, 0, 1): 556 return AMD_RESET_METHOD_MODE2; 557 case IP_VERSION(9, 0, 0): 558 case IP_VERSION(11, 0, 2): 559 if (adev->asic_type == CHIP_VEGA20) { 560 if (adev->psp.sos.fw_version >= 0x80067) 561 baco_reset = amdgpu_dpm_is_baco_supported(adev); 562 /* 563 * 1. PMFW version > 0x284300: all cases use baco 564 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 565 */ 566 if (ras && adev->ras_enabled && 567 adev->pm.fw_version <= 0x283400) 568 baco_reset = 0; 569 } else { 570 baco_reset = amdgpu_dpm_is_baco_supported(adev); 571 } 572 break; 573 case IP_VERSION(13, 0, 2): 574 /* 575 * 1.connected to cpu: driver issue mode2 reset 576 * 2.discret gpu: driver issue mode1 reset 577 */ 578 if (connected_to_cpu) 579 return AMD_RESET_METHOD_MODE2; 580 break; 581 case IP_VERSION(13, 0, 6): 582 case IP_VERSION(13, 0, 14): 583 case IP_VERSION(13, 0, 12): 584 /* Use gpu_recovery param to target a reset method. 585 * Enable triggering of GPU reset only if specified 586 * by module parameter. 587 */ 588 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 589 return AMD_RESET_METHOD_MODE2; 590 else if (!(adev->flags & AMD_IS_APU)) 591 return AMD_RESET_METHOD_MODE1; 592 else 593 return AMD_RESET_METHOD_MODE2; 594 default: 595 break; 596 } 597 598 if (baco_reset) 599 return AMD_RESET_METHOD_BACO; 600 else 601 return AMD_RESET_METHOD_MODE1; 602 } 603 604 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 605 { 606 /* Will reset for the following suspend abort cases. 607 * 1) S3 suspend aborted in the normal S3 suspend 608 * 2) S3 suspend aborted in performing pm core test. 609 */ 610 if (adev->in_s3 && !pm_resume_via_firmware()) 611 return true; 612 else 613 return false; 614 } 615 616 static int soc15_asic_reset(struct amdgpu_device *adev) 617 { 618 /* original raven doesn't have full asic reset */ 619 /* On the latest Raven, the GPU reset can be performed 620 * successfully. So now, temporarily enable it for the 621 * S3 suspend abort case. 622 */ 623 624 if ((adev->apu_flags & AMD_APU_IS_PICASSO || 625 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 626 soc15_need_reset_on_resume(adev)) 627 goto asic_reset; 628 629 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 630 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 631 return 0; 632 633 asic_reset: 634 switch (soc15_asic_reset_method(adev)) { 635 case AMD_RESET_METHOD_PCI: 636 dev_info(adev->dev, "PCI reset\n"); 637 return amdgpu_device_pci_reset(adev); 638 case AMD_RESET_METHOD_BACO: 639 dev_info(adev->dev, "BACO reset\n"); 640 return soc15_asic_baco_reset(adev); 641 case AMD_RESET_METHOD_MODE2: 642 dev_info(adev->dev, "MODE2 reset\n"); 643 return amdgpu_dpm_mode2_reset(adev); 644 default: 645 dev_info(adev->dev, "MODE1 reset\n"); 646 return amdgpu_device_mode1_reset(adev); 647 } 648 } 649 650 static int soc15_supports_baco(struct amdgpu_device *adev) 651 { 652 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 653 case IP_VERSION(9, 0, 0): 654 case IP_VERSION(11, 0, 2): 655 if (adev->asic_type == CHIP_VEGA20) { 656 if (adev->psp.sos.fw_version >= 0x80067) 657 return amdgpu_dpm_is_baco_supported(adev); 658 return 0; 659 } else { 660 return amdgpu_dpm_is_baco_supported(adev); 661 } 662 break; 663 default: 664 return 0; 665 } 666 } 667 668 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 669 u32 cntl_reg, u32 status_reg) 670 { 671 return 0; 672 }*/ 673 674 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 675 { 676 /*int r; 677 678 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 679 if (r) 680 return r; 681 682 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 683 */ 684 return 0; 685 } 686 687 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 688 { 689 /* todo */ 690 691 return 0; 692 } 693 694 static void soc15_program_aspm(struct amdgpu_device *adev) 695 { 696 if (!amdgpu_device_should_use_aspm(adev)) 697 return; 698 699 if (adev->nbio.funcs->program_aspm) 700 adev->nbio.funcs->program_aspm(adev); 701 } 702 703 const struct amdgpu_ip_block_version vega10_common_ip_block = 704 { 705 .type = AMD_IP_BLOCK_TYPE_COMMON, 706 .major = 2, 707 .minor = 0, 708 .rev = 0, 709 .funcs = &soc15_common_ip_funcs, 710 }; 711 712 static void soc15_reg_base_init(struct amdgpu_device *adev) 713 { 714 /* Set IP register base before any HW register access */ 715 switch (adev->asic_type) { 716 case CHIP_VEGA10: 717 case CHIP_VEGA12: 718 case CHIP_RAVEN: 719 case CHIP_RENOIR: 720 vega10_reg_base_init(adev); 721 break; 722 case CHIP_VEGA20: 723 vega20_reg_base_init(adev); 724 break; 725 case CHIP_ARCTURUS: 726 arct_reg_base_init(adev); 727 break; 728 case CHIP_ALDEBARAN: 729 aldebaran_reg_base_init(adev); 730 break; 731 default: 732 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 733 break; 734 } 735 } 736 737 void soc15_set_virt_ops(struct amdgpu_device *adev) 738 { 739 adev->virt.ops = &xgpu_ai_virt_ops; 740 741 /* init soc15 reg base early enough so we can 742 * request request full access for sriov before 743 * set_ip_blocks. */ 744 soc15_reg_base_init(adev); 745 } 746 747 static bool soc15_need_full_reset(struct amdgpu_device *adev) 748 { 749 /* change this when we implement soft reset */ 750 return true; 751 } 752 753 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 754 uint64_t *count1) 755 { 756 uint32_t perfctr = 0; 757 uint64_t cnt0_of, cnt1_of; 758 int tmp; 759 760 /* This reports 0 on APUs, so return to avoid writing/reading registers 761 * that may or may not be different from their GPU counterparts 762 */ 763 if (adev->flags & AMD_IS_APU) 764 return; 765 766 /* Set the 2 events that we wish to watch, defined above */ 767 /* Reg 40 is # received msgs */ 768 /* Reg 104 is # of posted requests sent */ 769 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 770 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 771 772 /* Write to enable desired perf counters */ 773 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 774 /* Zero out and enable the perf counters 775 * Write 0x5: 776 * Bit 0 = Start all counters(1) 777 * Bit 2 = Global counter reset enable(1) 778 */ 779 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 780 781 msleep(1000); 782 783 /* Load the shadow and disable the perf counters 784 * Write 0x2: 785 * Bit 0 = Stop counters(0) 786 * Bit 1 = Load the shadow counters(1) 787 */ 788 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 789 790 /* Read register values to get any >32bit overflow */ 791 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 792 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 793 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 794 795 /* Get the values and add the overflow */ 796 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 797 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 798 } 799 800 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 801 uint64_t *count1) 802 { 803 uint32_t perfctr = 0; 804 uint64_t cnt0_of, cnt1_of; 805 int tmp; 806 807 /* This reports 0 on APUs, so return to avoid writing/reading registers 808 * that may or may not be different from their GPU counterparts 809 */ 810 if (adev->flags & AMD_IS_APU) 811 return; 812 813 /* Set the 2 events that we wish to watch, defined above */ 814 /* Reg 40 is # received msgs */ 815 /* Reg 108 is # of posted requests sent on VG20 */ 816 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 817 EVENT0_SEL, 40); 818 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 819 EVENT1_SEL, 108); 820 821 /* Write to enable desired perf counters */ 822 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 823 /* Zero out and enable the perf counters 824 * Write 0x5: 825 * Bit 0 = Start all counters(1) 826 * Bit 2 = Global counter reset enable(1) 827 */ 828 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 829 830 msleep(1000); 831 832 /* Load the shadow and disable the perf counters 833 * Write 0x2: 834 * Bit 0 = Stop counters(0) 835 * Bit 1 = Load the shadow counters(1) 836 */ 837 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 838 839 /* Read register values to get any >32bit overflow */ 840 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 841 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 842 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 843 844 /* Get the values and add the overflow */ 845 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 846 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 847 } 848 849 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 850 { 851 u32 sol_reg; 852 853 /* CP hangs in IGT reloading test on RN, reset to WA */ 854 if (adev->asic_type == CHIP_RENOIR) 855 return true; 856 857 if (amdgpu_gmc_need_reset_on_init(adev)) 858 return true; 859 if (amdgpu_psp_tos_reload_needed(adev)) 860 return true; 861 /* Just return false for soc15 GPUs. Reset does not seem to 862 * be necessary. 863 */ 864 if (!amdgpu_passthrough(adev)) 865 return false; 866 867 if (adev->flags & AMD_IS_APU) 868 return false; 869 870 /* Check sOS sign of life register to confirm sys driver and sOS 871 * are already been loaded. 872 */ 873 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 874 if (sol_reg) 875 return true; 876 877 return false; 878 } 879 880 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 881 { 882 uint64_t nak_r, nak_g; 883 884 /* Get the number of NAKs received and generated */ 885 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 886 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 887 888 /* Add the total number of NAKs, i.e the number of replays */ 889 return (nak_r + nak_g); 890 } 891 892 static void soc15_pre_asic_init(struct amdgpu_device *adev) 893 { 894 gmc_v9_0_restore_registers(adev); 895 } 896 897 static const struct amdgpu_asic_funcs soc15_asic_funcs = 898 { 899 .read_disabled_bios = &soc15_read_disabled_bios, 900 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 901 .read_register = &soc15_read_register, 902 .reset = &soc15_asic_reset, 903 .reset_method = &soc15_asic_reset_method, 904 .get_xclk = &soc15_get_xclk, 905 .set_uvd_clocks = &soc15_set_uvd_clocks, 906 .set_vce_clocks = &soc15_set_vce_clocks, 907 .get_config_memsize = &soc15_get_config_memsize, 908 .need_full_reset = &soc15_need_full_reset, 909 .init_doorbell_index = &vega10_doorbell_index_init, 910 .get_pcie_usage = &soc15_get_pcie_usage, 911 .need_reset_on_init = &soc15_need_reset_on_init, 912 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 913 .supports_baco = &soc15_supports_baco, 914 .pre_asic_init = &soc15_pre_asic_init, 915 .query_video_codecs = &soc15_query_video_codecs, 916 }; 917 918 static const struct amdgpu_asic_funcs vega20_asic_funcs = 919 { 920 .read_disabled_bios = &soc15_read_disabled_bios, 921 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 922 .read_register = &soc15_read_register, 923 .reset = &soc15_asic_reset, 924 .reset_method = &soc15_asic_reset_method, 925 .get_xclk = &soc15_get_xclk, 926 .set_uvd_clocks = &soc15_set_uvd_clocks, 927 .set_vce_clocks = &soc15_set_vce_clocks, 928 .get_config_memsize = &soc15_get_config_memsize, 929 .need_full_reset = &soc15_need_full_reset, 930 .init_doorbell_index = &vega20_doorbell_index_init, 931 .get_pcie_usage = &vega20_get_pcie_usage, 932 .need_reset_on_init = &soc15_need_reset_on_init, 933 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 934 .supports_baco = &soc15_supports_baco, 935 .pre_asic_init = &soc15_pre_asic_init, 936 .query_video_codecs = &soc15_query_video_codecs, 937 }; 938 939 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 940 { 941 .read_disabled_bios = &soc15_read_disabled_bios, 942 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 943 .read_register = &soc15_read_register, 944 .reset = &soc15_asic_reset, 945 .reset_method = &soc15_asic_reset_method, 946 .get_xclk = &soc15_get_xclk, 947 .set_uvd_clocks = &soc15_set_uvd_clocks, 948 .set_vce_clocks = &soc15_set_vce_clocks, 949 .get_config_memsize = &soc15_get_config_memsize, 950 .need_full_reset = &soc15_need_full_reset, 951 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 952 .need_reset_on_init = &soc15_need_reset_on_init, 953 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 954 .supports_baco = &soc15_supports_baco, 955 .pre_asic_init = &soc15_pre_asic_init, 956 .query_video_codecs = &soc15_query_video_codecs, 957 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, 958 .get_reg_state = &aqua_vanjaram_get_reg_state, 959 }; 960 961 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) 962 { 963 struct amdgpu_device *adev = ip_block->adev; 964 965 adev->nbio.funcs->set_reg_remap(adev); 966 adev->smc_rreg = NULL; 967 adev->smc_wreg = NULL; 968 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 969 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 970 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 971 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 972 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 973 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 974 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 975 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 976 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 977 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 978 adev->didt_rreg = &soc15_didt_rreg; 979 adev->didt_wreg = &soc15_didt_wreg; 980 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 981 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 982 adev->se_cac_rreg = &soc15_se_cac_rreg; 983 adev->se_cac_wreg = &soc15_se_cac_wreg; 984 985 adev->rev_id = amdgpu_device_get_rev_id(adev); 986 adev->external_rev_id = 0xFF; 987 /* TODO: split the GC and PG flags based on the relevant IP version for which 988 * they are relevant. 989 */ 990 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 991 case IP_VERSION(9, 0, 1): 992 adev->asic_funcs = &soc15_asic_funcs; 993 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 994 AMD_CG_SUPPORT_GFX_MGLS | 995 AMD_CG_SUPPORT_GFX_RLC_LS | 996 AMD_CG_SUPPORT_GFX_CP_LS | 997 AMD_CG_SUPPORT_GFX_3D_CGCG | 998 AMD_CG_SUPPORT_GFX_3D_CGLS | 999 AMD_CG_SUPPORT_GFX_CGCG | 1000 AMD_CG_SUPPORT_GFX_CGLS | 1001 AMD_CG_SUPPORT_BIF_MGCG | 1002 AMD_CG_SUPPORT_BIF_LS | 1003 AMD_CG_SUPPORT_HDP_LS | 1004 AMD_CG_SUPPORT_DRM_MGCG | 1005 AMD_CG_SUPPORT_DRM_LS | 1006 AMD_CG_SUPPORT_ROM_MGCG | 1007 AMD_CG_SUPPORT_DF_MGCG | 1008 AMD_CG_SUPPORT_SDMA_MGCG | 1009 AMD_CG_SUPPORT_SDMA_LS | 1010 AMD_CG_SUPPORT_MC_MGCG | 1011 AMD_CG_SUPPORT_MC_LS; 1012 adev->pg_flags = 0; 1013 adev->external_rev_id = 0x1; 1014 break; 1015 case IP_VERSION(9, 2, 1): 1016 adev->asic_funcs = &soc15_asic_funcs; 1017 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1018 AMD_CG_SUPPORT_GFX_MGLS | 1019 AMD_CG_SUPPORT_GFX_CGCG | 1020 AMD_CG_SUPPORT_GFX_CGLS | 1021 AMD_CG_SUPPORT_GFX_3D_CGCG | 1022 AMD_CG_SUPPORT_GFX_3D_CGLS | 1023 AMD_CG_SUPPORT_GFX_CP_LS | 1024 AMD_CG_SUPPORT_MC_LS | 1025 AMD_CG_SUPPORT_MC_MGCG | 1026 AMD_CG_SUPPORT_SDMA_MGCG | 1027 AMD_CG_SUPPORT_SDMA_LS | 1028 AMD_CG_SUPPORT_BIF_MGCG | 1029 AMD_CG_SUPPORT_BIF_LS | 1030 AMD_CG_SUPPORT_HDP_MGCG | 1031 AMD_CG_SUPPORT_HDP_LS | 1032 AMD_CG_SUPPORT_ROM_MGCG | 1033 AMD_CG_SUPPORT_VCE_MGCG | 1034 AMD_CG_SUPPORT_UVD_MGCG; 1035 adev->pg_flags = 0; 1036 adev->external_rev_id = adev->rev_id + 0x14; 1037 break; 1038 case IP_VERSION(9, 4, 0): 1039 adev->asic_funcs = &vega20_asic_funcs; 1040 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1041 AMD_CG_SUPPORT_GFX_MGLS | 1042 AMD_CG_SUPPORT_GFX_CGCG | 1043 AMD_CG_SUPPORT_GFX_CGLS | 1044 AMD_CG_SUPPORT_GFX_3D_CGCG | 1045 AMD_CG_SUPPORT_GFX_3D_CGLS | 1046 AMD_CG_SUPPORT_GFX_CP_LS | 1047 AMD_CG_SUPPORT_MC_LS | 1048 AMD_CG_SUPPORT_MC_MGCG | 1049 AMD_CG_SUPPORT_SDMA_MGCG | 1050 AMD_CG_SUPPORT_SDMA_LS | 1051 AMD_CG_SUPPORT_BIF_MGCG | 1052 AMD_CG_SUPPORT_BIF_LS | 1053 AMD_CG_SUPPORT_HDP_MGCG | 1054 AMD_CG_SUPPORT_HDP_LS | 1055 AMD_CG_SUPPORT_ROM_MGCG | 1056 AMD_CG_SUPPORT_VCE_MGCG | 1057 AMD_CG_SUPPORT_UVD_MGCG; 1058 adev->pg_flags = 0; 1059 adev->external_rev_id = adev->rev_id + 0x28; 1060 break; 1061 case IP_VERSION(9, 1, 0): 1062 case IP_VERSION(9, 2, 2): 1063 adev->asic_funcs = &soc15_asic_funcs; 1064 1065 if (adev->rev_id >= 0x8) 1066 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1067 1068 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1069 adev->external_rev_id = adev->rev_id + 0x79; 1070 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1071 adev->external_rev_id = adev->rev_id + 0x41; 1072 else if (adev->rev_id == 1) 1073 adev->external_rev_id = adev->rev_id + 0x20; 1074 else 1075 adev->external_rev_id = adev->rev_id + 0x01; 1076 1077 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1078 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1079 AMD_CG_SUPPORT_GFX_MGLS | 1080 AMD_CG_SUPPORT_GFX_CP_LS | 1081 AMD_CG_SUPPORT_GFX_3D_CGCG | 1082 AMD_CG_SUPPORT_GFX_3D_CGLS | 1083 AMD_CG_SUPPORT_GFX_CGCG | 1084 AMD_CG_SUPPORT_GFX_CGLS | 1085 AMD_CG_SUPPORT_BIF_LS | 1086 AMD_CG_SUPPORT_HDP_LS | 1087 AMD_CG_SUPPORT_MC_MGCG | 1088 AMD_CG_SUPPORT_MC_LS | 1089 AMD_CG_SUPPORT_SDMA_MGCG | 1090 AMD_CG_SUPPORT_SDMA_LS | 1091 AMD_CG_SUPPORT_VCN_MGCG; 1092 1093 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1094 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1095 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1096 AMD_CG_SUPPORT_GFX_MGLS | 1097 AMD_CG_SUPPORT_GFX_CP_LS | 1098 AMD_CG_SUPPORT_GFX_3D_CGLS | 1099 AMD_CG_SUPPORT_GFX_CGCG | 1100 AMD_CG_SUPPORT_GFX_CGLS | 1101 AMD_CG_SUPPORT_BIF_LS | 1102 AMD_CG_SUPPORT_HDP_LS | 1103 AMD_CG_SUPPORT_MC_MGCG | 1104 AMD_CG_SUPPORT_MC_LS | 1105 AMD_CG_SUPPORT_SDMA_MGCG | 1106 AMD_CG_SUPPORT_SDMA_LS | 1107 AMD_CG_SUPPORT_VCN_MGCG; 1108 1109 /* 1110 * MMHUB PG needs to be disabled for Picasso for 1111 * stability reasons. 1112 */ 1113 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1114 AMD_PG_SUPPORT_VCN; 1115 } else { 1116 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1117 AMD_CG_SUPPORT_GFX_MGLS | 1118 AMD_CG_SUPPORT_GFX_RLC_LS | 1119 AMD_CG_SUPPORT_GFX_CP_LS | 1120 AMD_CG_SUPPORT_GFX_3D_CGLS | 1121 AMD_CG_SUPPORT_GFX_CGCG | 1122 AMD_CG_SUPPORT_GFX_CGLS | 1123 AMD_CG_SUPPORT_BIF_MGCG | 1124 AMD_CG_SUPPORT_BIF_LS | 1125 AMD_CG_SUPPORT_HDP_MGCG | 1126 AMD_CG_SUPPORT_HDP_LS | 1127 AMD_CG_SUPPORT_DRM_MGCG | 1128 AMD_CG_SUPPORT_DRM_LS | 1129 AMD_CG_SUPPORT_MC_MGCG | 1130 AMD_CG_SUPPORT_MC_LS | 1131 AMD_CG_SUPPORT_SDMA_MGCG | 1132 AMD_CG_SUPPORT_SDMA_LS | 1133 AMD_CG_SUPPORT_VCN_MGCG; 1134 1135 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1136 } 1137 break; 1138 case IP_VERSION(9, 4, 1): 1139 adev->asic_funcs = &vega20_asic_funcs; 1140 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1141 AMD_CG_SUPPORT_GFX_MGLS | 1142 AMD_CG_SUPPORT_GFX_CGCG | 1143 AMD_CG_SUPPORT_GFX_CGLS | 1144 AMD_CG_SUPPORT_GFX_CP_LS | 1145 AMD_CG_SUPPORT_HDP_MGCG | 1146 AMD_CG_SUPPORT_HDP_LS | 1147 AMD_CG_SUPPORT_SDMA_MGCG | 1148 AMD_CG_SUPPORT_SDMA_LS | 1149 AMD_CG_SUPPORT_MC_MGCG | 1150 AMD_CG_SUPPORT_MC_LS | 1151 AMD_CG_SUPPORT_IH_CG | 1152 AMD_CG_SUPPORT_VCN_MGCG | 1153 AMD_CG_SUPPORT_JPEG_MGCG; 1154 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1155 adev->external_rev_id = adev->rev_id + 0x32; 1156 break; 1157 case IP_VERSION(9, 3, 0): 1158 adev->asic_funcs = &soc15_asic_funcs; 1159 1160 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1161 adev->external_rev_id = adev->rev_id + 0x91; 1162 else 1163 adev->external_rev_id = adev->rev_id + 0xa1; 1164 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1165 AMD_CG_SUPPORT_GFX_MGLS | 1166 AMD_CG_SUPPORT_GFX_3D_CGCG | 1167 AMD_CG_SUPPORT_GFX_3D_CGLS | 1168 AMD_CG_SUPPORT_GFX_CGCG | 1169 AMD_CG_SUPPORT_GFX_CGLS | 1170 AMD_CG_SUPPORT_GFX_CP_LS | 1171 AMD_CG_SUPPORT_MC_MGCG | 1172 AMD_CG_SUPPORT_MC_LS | 1173 AMD_CG_SUPPORT_SDMA_MGCG | 1174 AMD_CG_SUPPORT_SDMA_LS | 1175 AMD_CG_SUPPORT_BIF_LS | 1176 AMD_CG_SUPPORT_HDP_LS | 1177 AMD_CG_SUPPORT_VCN_MGCG | 1178 AMD_CG_SUPPORT_JPEG_MGCG | 1179 AMD_CG_SUPPORT_IH_CG | 1180 AMD_CG_SUPPORT_ATHUB_LS | 1181 AMD_CG_SUPPORT_ATHUB_MGCG | 1182 AMD_CG_SUPPORT_DF_MGCG; 1183 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1184 AMD_PG_SUPPORT_VCN | 1185 AMD_PG_SUPPORT_JPEG | 1186 AMD_PG_SUPPORT_VCN_DPG; 1187 break; 1188 case IP_VERSION(9, 4, 2): 1189 adev->asic_funcs = &vega20_asic_funcs; 1190 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1191 AMD_CG_SUPPORT_GFX_MGLS | 1192 AMD_CG_SUPPORT_GFX_CP_LS | 1193 AMD_CG_SUPPORT_HDP_LS | 1194 AMD_CG_SUPPORT_SDMA_MGCG | 1195 AMD_CG_SUPPORT_SDMA_LS | 1196 AMD_CG_SUPPORT_IH_CG | 1197 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1198 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1199 adev->external_rev_id = adev->rev_id + 0x3c; 1200 break; 1201 case IP_VERSION(9, 4, 3): 1202 case IP_VERSION(9, 4, 4): 1203 case IP_VERSION(9, 5, 0): 1204 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1205 adev->cg_flags = 1206 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1207 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1208 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1209 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1210 AMD_CG_SUPPORT_IH_CG; 1211 adev->pg_flags = 1212 AMD_PG_SUPPORT_VCN | 1213 AMD_PG_SUPPORT_VCN_DPG | 1214 AMD_PG_SUPPORT_JPEG; 1215 /*TODO: need a new external_rev_id for GC 9.4.4? */ 1216 adev->external_rev_id = adev->rev_id + 0x46; 1217 break; 1218 default: 1219 /* FIXME: not supported yet */ 1220 return -EINVAL; 1221 } 1222 1223 if (amdgpu_sriov_vf(adev)) { 1224 amdgpu_virt_init_setting(adev); 1225 xgpu_ai_mailbox_set_irq_funcs(adev); 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) 1232 { 1233 struct amdgpu_device *adev = ip_block->adev; 1234 1235 if (amdgpu_sriov_vf(adev)) 1236 xgpu_ai_mailbox_get_irq(adev); 1237 1238 /* Enable selfring doorbell aperture late because doorbell BAR 1239 * aperture will change if resize BAR successfully in gmc sw_init. 1240 */ 1241 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1242 1243 return 0; 1244 } 1245 1246 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) 1247 { 1248 struct amdgpu_device *adev = ip_block->adev; 1249 1250 if (amdgpu_sriov_vf(adev)) 1251 xgpu_ai_mailbox_add_irq_id(adev); 1252 1253 if (adev->df.funcs && 1254 adev->df.funcs->sw_init) 1255 adev->df.funcs->sw_init(adev); 1256 1257 return 0; 1258 } 1259 1260 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) 1261 { 1262 struct amdgpu_device *adev = ip_block->adev; 1263 1264 if (adev->df.funcs && 1265 adev->df.funcs->sw_fini) 1266 adev->df.funcs->sw_fini(adev); 1267 return 0; 1268 } 1269 1270 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1271 { 1272 int i; 1273 1274 /* sdma doorbell range is programed by hypervisor */ 1275 if (!amdgpu_sriov_vf(adev)) { 1276 for (i = 0; i < adev->sdma.num_instances; i++) { 1277 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1278 true, adev->doorbell_index.sdma_engine[i] << 1, 1279 adev->doorbell_index.sdma_doorbell_range); 1280 } 1281 } 1282 } 1283 1284 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) 1285 { 1286 struct amdgpu_device *adev = ip_block->adev; 1287 1288 /* enable aspm */ 1289 soc15_program_aspm(adev); 1290 /* setup nbio registers */ 1291 adev->nbio.funcs->init_registers(adev); 1292 /* remap HDP registers to a hole in mmio space, 1293 * for the purpose of expose those registers 1294 * to process space 1295 */ 1296 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1297 adev->nbio.funcs->remap_hdp_registers(adev); 1298 1299 /* enable the doorbell aperture */ 1300 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1301 1302 /* HW doorbell routing policy: doorbell writing not 1303 * in SDMA/IH/MM/ACV range will be routed to CP. So 1304 * we need to init SDMA doorbell range prior 1305 * to CP ip block init and ring test. IH already 1306 * happens before CP. 1307 */ 1308 soc15_sdma_doorbell_range_init(adev); 1309 1310 return 0; 1311 } 1312 1313 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) 1314 { 1315 struct amdgpu_device *adev = ip_block->adev; 1316 1317 /* Disable the doorbell aperture and selfring doorbell aperture 1318 * separately in hw_fini because soc15_enable_doorbell_aperture 1319 * has been removed and there is no need to delay disabling 1320 * selfring doorbell. 1321 */ 1322 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1323 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1324 1325 if (amdgpu_sriov_vf(adev)) 1326 xgpu_ai_mailbox_put_irq(adev); 1327 1328 /* 1329 * For minimal init, late_init is not called, hence RAS irqs are not 1330 * enabled. 1331 */ 1332 if ((!amdgpu_sriov_vf(adev)) && 1333 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1334 adev->nbio.ras_if && 1335 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1336 if (adev->nbio.ras && 1337 adev->nbio.ras->init_ras_controller_interrupt) 1338 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1339 if (adev->nbio.ras && 1340 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1341 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) 1348 { 1349 return soc15_common_hw_fini(ip_block); 1350 } 1351 1352 static int soc15_common_resume(struct amdgpu_ip_block *ip_block) 1353 { 1354 struct amdgpu_device *adev = ip_block->adev; 1355 1356 if (soc15_need_reset_on_resume(adev)) { 1357 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); 1358 soc15_asic_reset(adev); 1359 } 1360 return soc15_common_hw_init(ip_block); 1361 } 1362 1363 static bool soc15_common_is_idle(void *handle) 1364 { 1365 return true; 1366 } 1367 1368 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1369 { 1370 uint32_t def, data; 1371 1372 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1373 1374 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1375 data &= ~(0x01000000 | 1376 0x02000000 | 1377 0x04000000 | 1378 0x08000000 | 1379 0x10000000 | 1380 0x20000000 | 1381 0x40000000 | 1382 0x80000000); 1383 else 1384 data |= (0x01000000 | 1385 0x02000000 | 1386 0x04000000 | 1387 0x08000000 | 1388 0x10000000 | 1389 0x20000000 | 1390 0x40000000 | 1391 0x80000000); 1392 1393 if (def != data) 1394 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1395 } 1396 1397 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1398 { 1399 uint32_t def, data; 1400 1401 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1402 1403 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1404 data |= 1; 1405 else 1406 data &= ~1; 1407 1408 if (def != data) 1409 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1410 } 1411 1412 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1413 enum amd_clockgating_state state) 1414 { 1415 struct amdgpu_device *adev = ip_block->adev; 1416 1417 if (amdgpu_sriov_vf(adev)) 1418 return 0; 1419 1420 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1421 case IP_VERSION(6, 1, 0): 1422 case IP_VERSION(6, 2, 0): 1423 case IP_VERSION(7, 4, 0): 1424 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1425 state == AMD_CG_STATE_GATE); 1426 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1427 state == AMD_CG_STATE_GATE); 1428 adev->hdp.funcs->update_clock_gating(adev, 1429 state == AMD_CG_STATE_GATE); 1430 soc15_update_drm_clock_gating(adev, 1431 state == AMD_CG_STATE_GATE); 1432 soc15_update_drm_light_sleep(adev, 1433 state == AMD_CG_STATE_GATE); 1434 adev->smuio.funcs->update_rom_clock_gating(adev, 1435 state == AMD_CG_STATE_GATE); 1436 adev->df.funcs->update_medium_grain_clock_gating(adev, 1437 state == AMD_CG_STATE_GATE); 1438 break; 1439 case IP_VERSION(7, 0, 0): 1440 case IP_VERSION(7, 0, 1): 1441 case IP_VERSION(2, 5, 0): 1442 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1443 state == AMD_CG_STATE_GATE); 1444 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1445 state == AMD_CG_STATE_GATE); 1446 adev->hdp.funcs->update_clock_gating(adev, 1447 state == AMD_CG_STATE_GATE); 1448 soc15_update_drm_clock_gating(adev, 1449 state == AMD_CG_STATE_GATE); 1450 soc15_update_drm_light_sleep(adev, 1451 state == AMD_CG_STATE_GATE); 1452 break; 1453 case IP_VERSION(7, 4, 1): 1454 case IP_VERSION(7, 4, 4): 1455 adev->hdp.funcs->update_clock_gating(adev, 1456 state == AMD_CG_STATE_GATE); 1457 break; 1458 default: 1459 break; 1460 } 1461 return 0; 1462 } 1463 1464 static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1465 { 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 int data; 1468 1469 if (amdgpu_sriov_vf(adev)) 1470 *flags = 0; 1471 1472 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1473 adev->nbio.funcs->get_clockgating_state(adev, flags); 1474 1475 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1476 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1477 1478 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1479 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && 1480 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && 1481 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { 1482 /* AMD_CG_SUPPORT_DRM_MGCG */ 1483 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1484 if (!(data & 0x01000000)) 1485 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1486 1487 /* AMD_CG_SUPPORT_DRM_LS */ 1488 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1489 if (data & 0x1) 1490 *flags |= AMD_CG_SUPPORT_DRM_LS; 1491 } 1492 1493 /* AMD_CG_SUPPORT_ROM_MGCG */ 1494 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1495 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1496 1497 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1498 adev->df.funcs->get_clockgating_state(adev, flags); 1499 } 1500 1501 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1502 enum amd_powergating_state state) 1503 { 1504 /* todo */ 1505 return 0; 1506 } 1507 1508 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1509 .name = "soc15_common", 1510 .early_init = soc15_common_early_init, 1511 .late_init = soc15_common_late_init, 1512 .sw_init = soc15_common_sw_init, 1513 .sw_fini = soc15_common_sw_fini, 1514 .hw_init = soc15_common_hw_init, 1515 .hw_fini = soc15_common_hw_fini, 1516 .suspend = soc15_common_suspend, 1517 .resume = soc15_common_resume, 1518 .is_idle = soc15_common_is_idle, 1519 .set_clockgating_state = soc15_common_set_clockgating_state, 1520 .set_powergating_state = soc15_common_set_powergating_state, 1521 .get_clockgating_state= soc15_common_get_clockgating_state, 1522 }; 1523