1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_ih.h" 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "amdgpu_ucode.h" 35 #include "amdgpu_psp.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "uvd/uvd_7_0_offset.h" 40 #include "gc/gc_9_0_offset.h" 41 #include "gc/gc_9_0_sh_mask.h" 42 #include "sdma0/sdma0_4_0_offset.h" 43 #include "sdma1/sdma1_4_0_offset.h" 44 #include "nbio/nbio_7_0_default.h" 45 #include "nbio/nbio_7_0_offset.h" 46 #include "nbio/nbio_7_0_sh_mask.h" 47 #include "nbio/nbio_7_0_smn.h" 48 #include "mp/mp_9_0_offset.h" 49 50 #include "soc15.h" 51 #include "soc15_common.h" 52 #include "gfx_v9_0.h" 53 #include "gmc_v9_0.h" 54 #include "gfxhub_v1_0.h" 55 #include "mmhub_v1_0.h" 56 #include "df_v1_7.h" 57 #include "df_v3_6.h" 58 #include "nbio_v6_1.h" 59 #include "nbio_v7_0.h" 60 #include "nbio_v7_4.h" 61 #include "hdp_v4_0.h" 62 #include "vega10_ih.h" 63 #include "vega20_ih.h" 64 #include "navi10_ih.h" 65 #include "sdma_v4_0.h" 66 #include "uvd_v7_0.h" 67 #include "vce_v4_0.h" 68 #include "vcn_v1_0.h" 69 #include "vcn_v2_0.h" 70 #include "jpeg_v2_0.h" 71 #include "vcn_v2_5.h" 72 #include "jpeg_v2_5.h" 73 #include "smuio_v9_0.h" 74 #include "smuio_v11_0.h" 75 #include "smuio_v13_0.h" 76 #include "amdgpu_vkms.h" 77 #include "mxgpu_ai.h" 78 #include "amdgpu_ras.h" 79 #include "amdgpu_xgmi.h" 80 #include "amdgpu_video_codecs.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 }; 112 113 static const struct amdgpu_video_codecs vega_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 116 .codec_array = vega_video_codecs_decode_array, 117 }; 118 119 /* Raven */ 120 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 129 }; 130 131 static const struct amdgpu_video_codecs rv_video_codecs_decode = 132 { 133 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 134 .codec_array = rv_video_codecs_decode_array, 135 }; 136 137 /* Renoir, Arcturus */ 138 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 139 { 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 147 }; 148 149 static const struct amdgpu_video_codecs rn_video_codecs_decode = 150 { 151 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 152 .codec_array = rn_video_codecs_decode_array, 153 }; 154 155 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 161 }; 162 163 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 164 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 165 .codec_array = vcn_4_0_3_video_codecs_decode_array, 166 }; 167 168 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 169 .codec_count = 0, 170 .codec_array = NULL, 171 }; 172 173 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = { 174 .codec_count = 0, 175 .codec_array = NULL, 176 }; 177 178 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = { 179 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 180 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 184 }; 185 186 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = { 187 .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0), 188 .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0, 189 }; 190 191 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 192 const struct amdgpu_video_codecs **codecs) 193 { 194 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 195 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 196 case IP_VERSION(4, 0, 0): 197 case IP_VERSION(4, 1, 0): 198 if (encode) 199 *codecs = &vega_video_codecs_encode; 200 else 201 *codecs = &vega_video_codecs_decode; 202 return 0; 203 default: 204 return -EINVAL; 205 } 206 } else { 207 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 208 case IP_VERSION(1, 0, 0): 209 case IP_VERSION(1, 0, 1): 210 if (encode) 211 *codecs = &vega_video_codecs_encode; 212 else 213 *codecs = &rv_video_codecs_decode; 214 return 0; 215 case IP_VERSION(2, 5, 0): 216 case IP_VERSION(2, 6, 0): 217 case IP_VERSION(2, 2, 0): 218 if (encode) 219 *codecs = &vega_video_codecs_encode; 220 else 221 *codecs = &rn_video_codecs_decode; 222 return 0; 223 case IP_VERSION(4, 0, 3): 224 if (encode) 225 *codecs = &vcn_4_0_3_video_codecs_encode; 226 else 227 *codecs = &vcn_4_0_3_video_codecs_decode; 228 return 0; 229 case IP_VERSION(5, 0, 1): 230 if (encode) 231 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0; 232 else 233 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0; 234 return 0; 235 default: 236 return -EINVAL; 237 } 238 } 239 } 240 241 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 242 { 243 unsigned long flags, address, data; 244 u32 r; 245 246 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 247 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 248 249 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 250 WREG32(address, ((reg) & 0x1ff)); 251 r = RREG32(data); 252 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 253 return r; 254 } 255 256 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 257 { 258 unsigned long flags, address, data; 259 260 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 261 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 262 263 spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); 264 WREG32(address, ((reg) & 0x1ff)); 265 WREG32(data, (v)); 266 spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); 267 } 268 269 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 270 { 271 unsigned long flags, address, data; 272 u32 r; 273 274 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 275 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 276 277 spin_lock_irqsave(&adev->reg.didt.lock, flags); 278 WREG32(address, (reg)); 279 r = RREG32(data); 280 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 281 return r; 282 } 283 284 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 285 { 286 unsigned long flags, address, data; 287 288 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 289 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 290 291 spin_lock_irqsave(&adev->reg.didt.lock, flags); 292 WREG32(address, (reg)); 293 WREG32(data, (v)); 294 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 295 } 296 297 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 298 { 299 unsigned long flags; 300 u32 r; 301 302 spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 303 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 304 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 305 spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 306 return r; 307 } 308 309 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 310 { 311 unsigned long flags; 312 313 spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 314 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 315 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 316 spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 317 } 318 319 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 320 { 321 unsigned long flags; 322 u32 r; 323 324 spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 325 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 326 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 327 spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 328 return r; 329 } 330 331 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 332 { 333 unsigned long flags; 334 335 spin_lock_irqsave(&adev->reg.se_cac.lock, flags); 336 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 337 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 338 spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); 339 } 340 341 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 342 { 343 return adev->nbio.funcs->get_memsize(adev); 344 } 345 346 static u32 soc15_get_xclk(struct amdgpu_device *adev) 347 { 348 u32 reference_clock = adev->clock.spll.reference_freq; 349 350 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || 351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || 352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || 353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || 354 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) 355 return 10000; 356 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || 357 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) 358 return reference_clock / 4; 359 360 return reference_clock; 361 } 362 363 364 void soc15_grbm_select(struct amdgpu_device *adev, 365 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 366 { 367 u32 grbm_gfx_cntl = 0; 368 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 371 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 372 373 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 374 } 375 376 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 377 { 378 /* todo */ 379 return false; 380 } 381 382 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 383 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 389 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 390 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 391 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 392 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 393 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 394 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 400 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 401 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 402 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 403 }; 404 405 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 406 bool indexed, u32 se_num, 407 u32 sh_num, u32 reg_offset) 408 { 409 if (indexed) { 410 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 411 } else { 412 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 413 return adev->gfx.config.gb_addr_config; 414 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 415 return adev->gfx.config.db_debug2; 416 return RREG32(reg_offset); 417 } 418 } 419 420 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 421 u32 sh_num, u32 reg_offset, u32 *value) 422 { 423 uint32_t i; 424 struct soc15_allowed_register_entry *en; 425 426 *value = 0; 427 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 428 en = &soc15_allowed_read_registers[i]; 429 if (!adev->reg_offset[en->hwip][en->inst]) 430 continue; 431 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 432 + en->reg_offset)) 433 continue; 434 435 *value = soc15_get_register_value(adev, 436 soc15_allowed_read_registers[i].grbm_indexed, 437 se_num, sh_num, reg_offset); 438 return 0; 439 } 440 return -EINVAL; 441 } 442 443 444 /** 445 * soc15_program_register_sequence - program an array of registers. 446 * 447 * @adev: amdgpu_device pointer 448 * @regs: pointer to the register array 449 * @array_size: size of the register array 450 * 451 * Programs an array or registers with and and or masks. 452 * This is a helper for setting golden registers. 453 */ 454 455 void soc15_program_register_sequence(struct amdgpu_device *adev, 456 const struct soc15_reg_golden *regs, 457 const u32 array_size) 458 { 459 const struct soc15_reg_golden *entry; 460 u32 tmp, reg; 461 int i; 462 463 for (i = 0; i < array_size; ++i) { 464 entry = ®s[i]; 465 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 466 467 if (entry->and_mask == 0xffffffff) { 468 tmp = entry->or_mask; 469 } else { 470 tmp = (entry->hwip == GC_HWIP) ? 471 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 472 473 tmp &= ~(entry->and_mask); 474 tmp |= (entry->or_mask & entry->and_mask); 475 } 476 477 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 478 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 479 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 480 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 481 WREG32_RLC(reg, tmp); 482 else 483 (entry->hwip == GC_HWIP) ? 484 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 485 486 } 487 488 } 489 490 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 491 { 492 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 493 int ret = 0; 494 495 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 496 if (ras && adev->ras_enabled) 497 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 498 499 ret = amdgpu_dpm_baco_reset(adev); 500 if (ret) 501 return ret; 502 503 /* re-enable doorbell interrupt after BACO exit */ 504 if (ras && adev->ras_enabled) 505 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 506 507 return 0; 508 } 509 510 static enum amd_reset_method 511 soc15_asic_reset_method(struct amdgpu_device *adev) 512 { 513 int baco_reset = 0; 514 bool connected_to_cpu = false; 515 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 516 517 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 518 connected_to_cpu = true; 519 520 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 521 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 522 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 523 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 524 /* If connected to cpu, driver only support mode2 */ 525 if (connected_to_cpu) 526 return AMD_RESET_METHOD_MODE2; 527 return amdgpu_reset_method; 528 } 529 530 if (amdgpu_reset_method != -1) 531 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 532 amdgpu_reset_method); 533 534 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 535 case IP_VERSION(10, 0, 0): 536 case IP_VERSION(10, 0, 1): 537 case IP_VERSION(12, 0, 0): 538 case IP_VERSION(12, 0, 1): 539 return AMD_RESET_METHOD_MODE2; 540 case IP_VERSION(9, 0, 0): 541 case IP_VERSION(11, 0, 2): 542 if (adev->asic_type == CHIP_VEGA20) { 543 if (adev->psp.sos.fw_version >= 0x80067) 544 baco_reset = amdgpu_dpm_is_baco_supported(adev); 545 /* 546 * 1. PMFW version > 0x284300: all cases use baco 547 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 548 */ 549 if (ras && adev->ras_enabled && 550 adev->pm.fw_version <= 0x283400) 551 baco_reset = 0; 552 } else { 553 baco_reset = amdgpu_dpm_is_baco_supported(adev); 554 } 555 break; 556 case IP_VERSION(13, 0, 2): 557 /* 558 * 1.connected to cpu: driver issue mode2 reset 559 * 2.discret gpu: driver issue mode1 reset 560 */ 561 if (connected_to_cpu) 562 return AMD_RESET_METHOD_MODE2; 563 break; 564 case IP_VERSION(13, 0, 6): 565 case IP_VERSION(13, 0, 14): 566 case IP_VERSION(13, 0, 12): 567 /* Use gpu_recovery param to target a reset method. 568 * Enable triggering of GPU reset only if specified 569 * by module parameter. 570 */ 571 if (adev->pcie_reset_ctx.in_link_reset) 572 return AMD_RESET_METHOD_LINK; 573 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 574 return AMD_RESET_METHOD_MODE2; 575 else if (!(adev->flags & AMD_IS_APU)) 576 return AMD_RESET_METHOD_MODE1; 577 else 578 return AMD_RESET_METHOD_MODE2; 579 default: 580 break; 581 } 582 583 if (baco_reset) 584 return AMD_RESET_METHOD_BACO; 585 else 586 return AMD_RESET_METHOD_MODE1; 587 } 588 589 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 590 { 591 /* Will reset for the following suspend abort cases. 592 * 1) S3 suspend aborted in the normal S3 suspend 593 * 2) S3 suspend aborted in performing pm core test. 594 */ 595 if (adev->in_s3 && !pm_resume_via_firmware()) 596 return true; 597 else 598 return false; 599 } 600 601 static int soc15_asic_reset(struct amdgpu_device *adev) 602 { 603 /* original raven doesn't have full asic reset */ 604 /* On the latest Raven, the GPU reset can be performed 605 * successfully. So now, temporarily enable it for the 606 * S3 suspend abort case. 607 */ 608 609 if ((adev->apu_flags & AMD_APU_IS_PICASSO || 610 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 611 soc15_need_reset_on_resume(adev)) 612 goto asic_reset; 613 614 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 615 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 616 return 0; 617 618 asic_reset: 619 switch (soc15_asic_reset_method(adev)) { 620 case AMD_RESET_METHOD_PCI: 621 dev_info(adev->dev, "PCI reset\n"); 622 return amdgpu_device_pci_reset(adev); 623 case AMD_RESET_METHOD_BACO: 624 dev_info(adev->dev, "BACO reset\n"); 625 return soc15_asic_baco_reset(adev); 626 case AMD_RESET_METHOD_MODE2: 627 dev_info(adev->dev, "MODE2 reset\n"); 628 return amdgpu_dpm_mode2_reset(adev); 629 case AMD_RESET_METHOD_LINK: 630 dev_info(adev->dev, "Link reset\n"); 631 return amdgpu_device_link_reset(adev); 632 default: 633 dev_info(adev->dev, "MODE1 reset\n"); 634 return amdgpu_device_mode1_reset(adev); 635 } 636 } 637 638 static int soc15_supports_baco(struct amdgpu_device *adev) 639 { 640 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 641 case IP_VERSION(9, 0, 0): 642 case IP_VERSION(11, 0, 2): 643 if (adev->asic_type == CHIP_VEGA20) { 644 if (adev->psp.sos.fw_version >= 0x80067) 645 return amdgpu_dpm_is_baco_supported(adev); 646 return 0; 647 } else { 648 return amdgpu_dpm_is_baco_supported(adev); 649 } 650 break; 651 default: 652 return 0; 653 } 654 } 655 656 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 657 u32 cntl_reg, u32 status_reg) 658 { 659 return 0; 660 }*/ 661 662 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 663 { 664 /*int r; 665 666 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 667 if (r) 668 return r; 669 670 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 671 */ 672 return 0; 673 } 674 675 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 676 { 677 /* todo */ 678 679 return 0; 680 } 681 682 const struct amdgpu_ip_block_version vega10_common_ip_block = 683 { 684 .type = AMD_IP_BLOCK_TYPE_COMMON, 685 .major = 2, 686 .minor = 0, 687 .rev = 0, 688 .funcs = &soc15_common_ip_funcs, 689 }; 690 691 static void soc15_reg_base_init(struct amdgpu_device *adev) 692 { 693 /* Set IP register base before any HW register access */ 694 switch (adev->asic_type) { 695 case CHIP_VEGA10: 696 case CHIP_VEGA12: 697 case CHIP_RAVEN: 698 case CHIP_RENOIR: 699 vega10_reg_base_init(adev); 700 break; 701 case CHIP_VEGA20: 702 vega20_reg_base_init(adev); 703 break; 704 case CHIP_ARCTURUS: 705 arct_reg_base_init(adev); 706 break; 707 case CHIP_ALDEBARAN: 708 aldebaran_reg_base_init(adev); 709 break; 710 default: 711 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 712 break; 713 } 714 } 715 716 void soc15_set_virt_ops(struct amdgpu_device *adev) 717 { 718 adev->virt.ops = &xgpu_ai_virt_ops; 719 /* init soc15 reg base early enough so we can 720 * request request full access for sriov before 721 * set_ip_blocks. */ 722 soc15_reg_base_init(adev); 723 } 724 725 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 726 uint64_t *count1) 727 { 728 uint32_t perfctr = 0; 729 uint64_t cnt0_of, cnt1_of; 730 int tmp; 731 732 /* This reports 0 on APUs, so return to avoid writing/reading registers 733 * that may or may not be different from their GPU counterparts 734 */ 735 if (adev->flags & AMD_IS_APU) 736 return; 737 738 /* Set the 2 events that we wish to watch, defined above */ 739 /* Reg 40 is # received msgs */ 740 /* Reg 104 is # of posted requests sent */ 741 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 742 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 743 744 /* Write to enable desired perf counters */ 745 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 746 /* Zero out and enable the perf counters 747 * Write 0x5: 748 * Bit 0 = Start all counters(1) 749 * Bit 2 = Global counter reset enable(1) 750 */ 751 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 752 753 msleep(1000); 754 755 /* Load the shadow and disable the perf counters 756 * Write 0x2: 757 * Bit 0 = Stop counters(0) 758 * Bit 1 = Load the shadow counters(1) 759 */ 760 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 761 762 /* Read register values to get any >32bit overflow */ 763 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 764 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 765 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 766 767 /* Get the values and add the overflow */ 768 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 769 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 770 } 771 772 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 773 uint64_t *count1) 774 { 775 uint32_t perfctr = 0; 776 uint64_t cnt0_of, cnt1_of; 777 int tmp; 778 779 /* This reports 0 on APUs, so return to avoid writing/reading registers 780 * that may or may not be different from their GPU counterparts 781 */ 782 if (adev->flags & AMD_IS_APU) 783 return; 784 785 /* Set the 2 events that we wish to watch, defined above */ 786 /* Reg 40 is # received msgs */ 787 /* Reg 108 is # of posted requests sent on VG20 */ 788 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 789 EVENT0_SEL, 40); 790 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 791 EVENT1_SEL, 108); 792 793 /* Write to enable desired perf counters */ 794 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 795 /* Zero out and enable the perf counters 796 * Write 0x5: 797 * Bit 0 = Start all counters(1) 798 * Bit 2 = Global counter reset enable(1) 799 */ 800 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 801 802 msleep(1000); 803 804 /* Load the shadow and disable the perf counters 805 * Write 0x2: 806 * Bit 0 = Stop counters(0) 807 * Bit 1 = Load the shadow counters(1) 808 */ 809 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 810 811 /* Read register values to get any >32bit overflow */ 812 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 813 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 814 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 815 816 /* Get the values and add the overflow */ 817 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 818 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 819 } 820 821 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 822 { 823 u32 sol_reg; 824 825 if (amdgpu_gmc_need_reset_on_init(adev)) 826 return true; 827 if (amdgpu_psp_tos_reload_needed(adev)) 828 return true; 829 /* Just return false for soc15 GPUs. Reset does not seem to 830 * be necessary. 831 */ 832 if (!amdgpu_passthrough(adev)) 833 return false; 834 835 if (adev->flags & AMD_IS_APU) 836 return false; 837 838 /* Check sOS sign of life register to confirm sys driver and sOS 839 * are already been loaded. 840 */ 841 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 842 if (sol_reg) 843 return true; 844 845 return false; 846 } 847 848 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 849 { 850 uint64_t nak_r, nak_g; 851 852 /* Get the number of NAKs received and generated */ 853 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 854 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 855 856 /* Add the total number of NAKs, i.e the number of replays */ 857 return (nak_r + nak_g); 858 } 859 860 static void soc15_pre_asic_init(struct amdgpu_device *adev) 861 { 862 gmc_v9_0_restore_registers(adev); 863 } 864 865 static const struct amdgpu_asic_funcs soc15_asic_funcs = 866 { 867 .read_disabled_bios = &soc15_read_disabled_bios, 868 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 869 .read_register = &soc15_read_register, 870 .reset = &soc15_asic_reset, 871 .reset_method = &soc15_asic_reset_method, 872 .get_xclk = &soc15_get_xclk, 873 .set_uvd_clocks = &soc15_set_uvd_clocks, 874 .set_vce_clocks = &soc15_set_vce_clocks, 875 .get_config_memsize = &soc15_get_config_memsize, 876 .init_doorbell_index = &vega10_doorbell_index_init, 877 .get_pcie_usage = &soc15_get_pcie_usage, 878 .need_reset_on_init = &soc15_need_reset_on_init, 879 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 880 .supports_baco = &soc15_supports_baco, 881 .pre_asic_init = &soc15_pre_asic_init, 882 .query_video_codecs = &soc15_query_video_codecs, 883 }; 884 885 static const struct amdgpu_asic_funcs vega20_asic_funcs = 886 { 887 .read_disabled_bios = &soc15_read_disabled_bios, 888 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 889 .read_register = &soc15_read_register, 890 .reset = &soc15_asic_reset, 891 .reset_method = &soc15_asic_reset_method, 892 .get_xclk = &soc15_get_xclk, 893 .set_uvd_clocks = &soc15_set_uvd_clocks, 894 .set_vce_clocks = &soc15_set_vce_clocks, 895 .get_config_memsize = &soc15_get_config_memsize, 896 .init_doorbell_index = &vega20_doorbell_index_init, 897 .get_pcie_usage = &vega20_get_pcie_usage, 898 .need_reset_on_init = &soc15_need_reset_on_init, 899 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 900 .supports_baco = &soc15_supports_baco, 901 .pre_asic_init = &soc15_pre_asic_init, 902 .query_video_codecs = &soc15_query_video_codecs, 903 }; 904 905 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 906 { 907 .read_disabled_bios = &soc15_read_disabled_bios, 908 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 909 .read_register = &soc15_read_register, 910 .reset = &soc15_asic_reset, 911 .reset_method = &soc15_asic_reset_method, 912 .get_xclk = &soc15_get_xclk, 913 .set_uvd_clocks = &soc15_set_uvd_clocks, 914 .set_vce_clocks = &soc15_set_vce_clocks, 915 .get_config_memsize = &soc15_get_config_memsize, 916 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 917 .need_reset_on_init = &soc15_need_reset_on_init, 918 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 919 .supports_baco = &soc15_supports_baco, 920 .query_video_codecs = &soc15_query_video_codecs, 921 .get_reg_state = &aqua_vanjaram_get_reg_state, 922 }; 923 924 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) 925 { 926 struct amdgpu_device *adev = ip_block->adev; 927 928 adev->nbio.funcs->set_reg_remap(adev); 929 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 930 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 931 adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; 932 adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; 933 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 934 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 935 adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 936 adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 937 adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; 938 adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 939 adev->reg.didt.rreg = &soc15_didt_rreg; 940 adev->reg.didt.wreg = &soc15_didt_wreg; 941 adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; 942 adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; 943 adev->reg.se_cac.rreg = &soc15_se_cac_rreg; 944 adev->reg.se_cac.wreg = &soc15_se_cac_wreg; 945 946 adev->rev_id = amdgpu_device_get_rev_id(adev); 947 adev->external_rev_id = 0xFF; 948 /* TODO: split the GC and PG flags based on the relevant IP version for which 949 * they are relevant. 950 */ 951 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 952 case IP_VERSION(9, 0, 1): 953 adev->asic_funcs = &soc15_asic_funcs; 954 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 955 AMD_CG_SUPPORT_GFX_MGLS | 956 AMD_CG_SUPPORT_GFX_RLC_LS | 957 AMD_CG_SUPPORT_GFX_CP_LS | 958 AMD_CG_SUPPORT_GFX_3D_CGCG | 959 AMD_CG_SUPPORT_GFX_3D_CGLS | 960 AMD_CG_SUPPORT_GFX_CGCG | 961 AMD_CG_SUPPORT_GFX_CGLS | 962 AMD_CG_SUPPORT_BIF_MGCG | 963 AMD_CG_SUPPORT_BIF_LS | 964 AMD_CG_SUPPORT_HDP_LS | 965 AMD_CG_SUPPORT_DRM_MGCG | 966 AMD_CG_SUPPORT_DRM_LS | 967 AMD_CG_SUPPORT_ROM_MGCG | 968 AMD_CG_SUPPORT_DF_MGCG | 969 AMD_CG_SUPPORT_SDMA_MGCG | 970 AMD_CG_SUPPORT_SDMA_LS | 971 AMD_CG_SUPPORT_MC_MGCG | 972 AMD_CG_SUPPORT_MC_LS; 973 adev->pg_flags = 0; 974 adev->external_rev_id = 0x1; 975 break; 976 case IP_VERSION(9, 2, 1): 977 adev->asic_funcs = &soc15_asic_funcs; 978 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 979 AMD_CG_SUPPORT_GFX_MGLS | 980 AMD_CG_SUPPORT_GFX_CGCG | 981 AMD_CG_SUPPORT_GFX_CGLS | 982 AMD_CG_SUPPORT_GFX_3D_CGCG | 983 AMD_CG_SUPPORT_GFX_3D_CGLS | 984 AMD_CG_SUPPORT_GFX_CP_LS | 985 AMD_CG_SUPPORT_MC_LS | 986 AMD_CG_SUPPORT_MC_MGCG | 987 AMD_CG_SUPPORT_SDMA_MGCG | 988 AMD_CG_SUPPORT_SDMA_LS | 989 AMD_CG_SUPPORT_BIF_MGCG | 990 AMD_CG_SUPPORT_BIF_LS | 991 AMD_CG_SUPPORT_HDP_MGCG | 992 AMD_CG_SUPPORT_HDP_LS | 993 AMD_CG_SUPPORT_ROM_MGCG | 994 AMD_CG_SUPPORT_VCE_MGCG | 995 AMD_CG_SUPPORT_UVD_MGCG; 996 adev->pg_flags = 0; 997 adev->external_rev_id = adev->rev_id + 0x14; 998 break; 999 case IP_VERSION(9, 4, 0): 1000 adev->asic_funcs = &vega20_asic_funcs; 1001 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1002 AMD_CG_SUPPORT_GFX_MGLS | 1003 AMD_CG_SUPPORT_GFX_CGCG | 1004 AMD_CG_SUPPORT_GFX_CGLS | 1005 AMD_CG_SUPPORT_GFX_3D_CGCG | 1006 AMD_CG_SUPPORT_GFX_3D_CGLS | 1007 AMD_CG_SUPPORT_GFX_CP_LS | 1008 AMD_CG_SUPPORT_MC_LS | 1009 AMD_CG_SUPPORT_MC_MGCG | 1010 AMD_CG_SUPPORT_SDMA_MGCG | 1011 AMD_CG_SUPPORT_SDMA_LS | 1012 AMD_CG_SUPPORT_BIF_MGCG | 1013 AMD_CG_SUPPORT_BIF_LS | 1014 AMD_CG_SUPPORT_HDP_MGCG | 1015 AMD_CG_SUPPORT_HDP_LS | 1016 AMD_CG_SUPPORT_ROM_MGCG | 1017 AMD_CG_SUPPORT_VCE_MGCG | 1018 AMD_CG_SUPPORT_UVD_MGCG; 1019 adev->pg_flags = 0; 1020 adev->external_rev_id = adev->rev_id + 0x28; 1021 break; 1022 case IP_VERSION(9, 1, 0): 1023 case IP_VERSION(9, 2, 2): 1024 adev->asic_funcs = &soc15_asic_funcs; 1025 1026 if (adev->rev_id >= 0x8) 1027 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1028 1029 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1030 adev->external_rev_id = adev->rev_id + 0x79; 1031 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1032 adev->external_rev_id = adev->rev_id + 0x41; 1033 else if (adev->rev_id == 1) 1034 adev->external_rev_id = adev->rev_id + 0x20; 1035 else 1036 adev->external_rev_id = adev->rev_id + 0x01; 1037 1038 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1039 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1040 AMD_CG_SUPPORT_GFX_MGLS | 1041 AMD_CG_SUPPORT_GFX_CP_LS | 1042 AMD_CG_SUPPORT_GFX_3D_CGCG | 1043 AMD_CG_SUPPORT_GFX_3D_CGLS | 1044 AMD_CG_SUPPORT_GFX_CGCG | 1045 AMD_CG_SUPPORT_GFX_CGLS | 1046 AMD_CG_SUPPORT_BIF_LS | 1047 AMD_CG_SUPPORT_HDP_LS | 1048 AMD_CG_SUPPORT_MC_MGCG | 1049 AMD_CG_SUPPORT_MC_LS | 1050 AMD_CG_SUPPORT_SDMA_MGCG | 1051 AMD_CG_SUPPORT_SDMA_LS | 1052 AMD_CG_SUPPORT_VCN_MGCG; 1053 1054 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1055 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1056 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1057 AMD_CG_SUPPORT_GFX_MGLS | 1058 AMD_CG_SUPPORT_GFX_CP_LS | 1059 AMD_CG_SUPPORT_GFX_3D_CGLS | 1060 AMD_CG_SUPPORT_GFX_CGCG | 1061 AMD_CG_SUPPORT_GFX_CGLS | 1062 AMD_CG_SUPPORT_BIF_LS | 1063 AMD_CG_SUPPORT_HDP_LS | 1064 AMD_CG_SUPPORT_MC_MGCG | 1065 AMD_CG_SUPPORT_MC_LS | 1066 AMD_CG_SUPPORT_SDMA_MGCG | 1067 AMD_CG_SUPPORT_SDMA_LS | 1068 AMD_CG_SUPPORT_VCN_MGCG; 1069 1070 /* 1071 * MMHUB PG needs to be disabled for Picasso for 1072 * stability reasons. 1073 */ 1074 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1075 AMD_PG_SUPPORT_VCN; 1076 } else { 1077 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1078 AMD_CG_SUPPORT_GFX_MGLS | 1079 AMD_CG_SUPPORT_GFX_RLC_LS | 1080 AMD_CG_SUPPORT_GFX_CP_LS | 1081 AMD_CG_SUPPORT_GFX_3D_CGLS | 1082 AMD_CG_SUPPORT_GFX_CGCG | 1083 AMD_CG_SUPPORT_GFX_CGLS | 1084 AMD_CG_SUPPORT_BIF_MGCG | 1085 AMD_CG_SUPPORT_BIF_LS | 1086 AMD_CG_SUPPORT_HDP_MGCG | 1087 AMD_CG_SUPPORT_HDP_LS | 1088 AMD_CG_SUPPORT_DRM_MGCG | 1089 AMD_CG_SUPPORT_DRM_LS | 1090 AMD_CG_SUPPORT_MC_MGCG | 1091 AMD_CG_SUPPORT_MC_LS | 1092 AMD_CG_SUPPORT_SDMA_MGCG | 1093 AMD_CG_SUPPORT_SDMA_LS | 1094 AMD_CG_SUPPORT_VCN_MGCG; 1095 1096 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1097 } 1098 break; 1099 case IP_VERSION(9, 4, 1): 1100 adev->asic_funcs = &vega20_asic_funcs; 1101 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1102 AMD_CG_SUPPORT_GFX_MGLS | 1103 AMD_CG_SUPPORT_GFX_CGCG | 1104 AMD_CG_SUPPORT_GFX_CGLS | 1105 AMD_CG_SUPPORT_GFX_CP_LS | 1106 AMD_CG_SUPPORT_HDP_MGCG | 1107 AMD_CG_SUPPORT_HDP_LS | 1108 AMD_CG_SUPPORT_SDMA_MGCG | 1109 AMD_CG_SUPPORT_SDMA_LS | 1110 AMD_CG_SUPPORT_MC_MGCG | 1111 AMD_CG_SUPPORT_MC_LS | 1112 AMD_CG_SUPPORT_IH_CG | 1113 AMD_CG_SUPPORT_VCN_MGCG | 1114 AMD_CG_SUPPORT_JPEG_MGCG; 1115 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1116 adev->external_rev_id = adev->rev_id + 0x32; 1117 break; 1118 case IP_VERSION(9, 3, 0): 1119 adev->asic_funcs = &soc15_asic_funcs; 1120 1121 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1122 adev->external_rev_id = adev->rev_id + 0x91; 1123 else 1124 adev->external_rev_id = adev->rev_id + 0xa1; 1125 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1126 AMD_CG_SUPPORT_GFX_MGLS | 1127 AMD_CG_SUPPORT_GFX_3D_CGCG | 1128 AMD_CG_SUPPORT_GFX_3D_CGLS | 1129 AMD_CG_SUPPORT_GFX_CGCG | 1130 AMD_CG_SUPPORT_GFX_CGLS | 1131 AMD_CG_SUPPORT_GFX_CP_LS | 1132 AMD_CG_SUPPORT_MC_MGCG | 1133 AMD_CG_SUPPORT_MC_LS | 1134 AMD_CG_SUPPORT_SDMA_MGCG | 1135 AMD_CG_SUPPORT_SDMA_LS | 1136 AMD_CG_SUPPORT_BIF_LS | 1137 AMD_CG_SUPPORT_HDP_LS | 1138 AMD_CG_SUPPORT_VCN_MGCG | 1139 AMD_CG_SUPPORT_JPEG_MGCG | 1140 AMD_CG_SUPPORT_IH_CG | 1141 AMD_CG_SUPPORT_ATHUB_LS | 1142 AMD_CG_SUPPORT_ATHUB_MGCG | 1143 AMD_CG_SUPPORT_DF_MGCG; 1144 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1145 AMD_PG_SUPPORT_VCN | 1146 AMD_PG_SUPPORT_JPEG | 1147 AMD_PG_SUPPORT_VCN_DPG; 1148 break; 1149 case IP_VERSION(9, 4, 2): 1150 adev->asic_funcs = &vega20_asic_funcs; 1151 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1152 AMD_CG_SUPPORT_GFX_MGLS | 1153 AMD_CG_SUPPORT_GFX_CP_LS | 1154 AMD_CG_SUPPORT_HDP_LS | 1155 AMD_CG_SUPPORT_SDMA_MGCG | 1156 AMD_CG_SUPPORT_SDMA_LS | 1157 AMD_CG_SUPPORT_IH_CG | 1158 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1159 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1160 adev->external_rev_id = adev->rev_id + 0x3c; 1161 break; 1162 case IP_VERSION(9, 4, 3): 1163 case IP_VERSION(9, 4, 4): 1164 case IP_VERSION(9, 5, 0): 1165 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1166 adev->reg.smn.get_smn_base = &amdgpu_reg_smn_v1_0_get_base; 1167 adev->cg_flags = 1168 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1169 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1170 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1171 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1172 AMD_CG_SUPPORT_IH_CG; 1173 adev->pg_flags = 1174 AMD_PG_SUPPORT_VCN | 1175 AMD_PG_SUPPORT_VCN_DPG | 1176 AMD_PG_SUPPORT_JPEG; 1177 /*TODO: need a new external_rev_id for GC 9.4.4? */ 1178 adev->external_rev_id = adev->rev_id + 0x46; 1179 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) 1180 adev->external_rev_id = adev->rev_id + 0x50; 1181 break; 1182 default: 1183 /* FIXME: not supported yet */ 1184 return -EINVAL; 1185 } 1186 1187 if (amdgpu_sriov_vf(adev)) { 1188 amdgpu_virt_init_setting(adev); 1189 xgpu_ai_mailbox_set_irq_funcs(adev); 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) 1196 { 1197 struct amdgpu_device *adev = ip_block->adev; 1198 1199 if (amdgpu_sriov_vf(adev)) 1200 xgpu_ai_mailbox_get_irq(adev); 1201 1202 /* Enable selfring doorbell aperture late because doorbell BAR 1203 * aperture will change if resize BAR successfully in gmc sw_init. 1204 */ 1205 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1206 1207 return 0; 1208 } 1209 1210 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) 1211 { 1212 struct amdgpu_device *adev = ip_block->adev; 1213 1214 if (amdgpu_sriov_vf(adev)) 1215 xgpu_ai_mailbox_add_irq_id(adev); 1216 1217 if (adev->df.funcs && 1218 adev->df.funcs->sw_init) 1219 adev->df.funcs->sw_init(adev); 1220 1221 return 0; 1222 } 1223 1224 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) 1225 { 1226 struct amdgpu_device *adev = ip_block->adev; 1227 1228 if (adev->df.funcs && 1229 adev->df.funcs->sw_fini) 1230 adev->df.funcs->sw_fini(adev); 1231 return 0; 1232 } 1233 1234 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1235 { 1236 int i; 1237 1238 /* sdma doorbell range is programed by hypervisor */ 1239 if (!amdgpu_sriov_vf(adev)) { 1240 for (i = 0; i < adev->sdma.num_instances; i++) { 1241 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1242 true, adev->doorbell_index.sdma_engine[i] << 1, 1243 adev->doorbell_index.sdma_doorbell_range); 1244 } 1245 } 1246 } 1247 1248 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) 1249 { 1250 struct amdgpu_device *adev = ip_block->adev; 1251 1252 /* enable aspm */ 1253 amdgpu_nbio_program_aspm(adev); 1254 /* setup nbio registers */ 1255 adev->nbio.funcs->init_registers(adev); 1256 /* remap HDP registers to a hole in mmio space, 1257 * for the purpose of expose those registers 1258 * to process space 1259 */ 1260 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1261 adev->nbio.funcs->remap_hdp_registers(adev); 1262 1263 /* enable the doorbell aperture */ 1264 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1265 1266 /* HW doorbell routing policy: doorbell writing not 1267 * in SDMA/IH/MM/ACV range will be routed to CP. So 1268 * we need to init SDMA doorbell range prior 1269 * to CP ip block init and ring test. IH already 1270 * happens before CP. 1271 */ 1272 soc15_sdma_doorbell_range_init(adev); 1273 1274 return 0; 1275 } 1276 1277 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) 1278 { 1279 struct amdgpu_device *adev = ip_block->adev; 1280 1281 /* Disable the doorbell aperture and selfring doorbell aperture 1282 * separately in hw_fini because soc15_enable_doorbell_aperture 1283 * has been removed and there is no need to delay disabling 1284 * selfring doorbell. 1285 */ 1286 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1287 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1288 1289 if (amdgpu_sriov_vf(adev)) 1290 xgpu_ai_mailbox_put_irq(adev); 1291 1292 /* 1293 * For minimal init, late_init is not called, hence RAS irqs are not 1294 * enabled. 1295 */ 1296 if ((!amdgpu_sriov_vf(adev)) && 1297 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1298 adev->nbio.ras_if && 1299 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1300 if (adev->nbio.ras && 1301 adev->nbio.ras->init_ras_controller_interrupt) 1302 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1303 if (adev->nbio.ras && 1304 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1305 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1306 } 1307 1308 return 0; 1309 } 1310 1311 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) 1312 { 1313 return soc15_common_hw_fini(ip_block); 1314 } 1315 1316 static int soc15_common_resume(struct amdgpu_ip_block *ip_block) 1317 { 1318 struct amdgpu_device *adev = ip_block->adev; 1319 1320 if (soc15_need_reset_on_resume(adev)) { 1321 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); 1322 soc15_asic_reset(adev); 1323 } 1324 return soc15_common_hw_init(ip_block); 1325 } 1326 1327 static bool soc15_common_is_idle(struct amdgpu_ip_block *ip_block) 1328 { 1329 return true; 1330 } 1331 1332 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1333 { 1334 uint32_t def, data; 1335 1336 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1337 1338 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1339 data &= ~(0x01000000 | 1340 0x02000000 | 1341 0x04000000 | 1342 0x08000000 | 1343 0x10000000 | 1344 0x20000000 | 1345 0x40000000 | 1346 0x80000000); 1347 else 1348 data |= (0x01000000 | 1349 0x02000000 | 1350 0x04000000 | 1351 0x08000000 | 1352 0x10000000 | 1353 0x20000000 | 1354 0x40000000 | 1355 0x80000000); 1356 1357 if (def != data) 1358 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1359 } 1360 1361 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1362 { 1363 uint32_t def, data; 1364 1365 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1366 1367 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1368 data |= 1; 1369 else 1370 data &= ~1; 1371 1372 if (def != data) 1373 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1374 } 1375 1376 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1377 enum amd_clockgating_state state) 1378 { 1379 struct amdgpu_device *adev = ip_block->adev; 1380 1381 if (amdgpu_sriov_vf(adev)) 1382 return 0; 1383 1384 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1385 case IP_VERSION(6, 1, 0): 1386 case IP_VERSION(6, 2, 0): 1387 case IP_VERSION(7, 4, 0): 1388 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1389 state == AMD_CG_STATE_GATE); 1390 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1391 state == AMD_CG_STATE_GATE); 1392 adev->hdp.funcs->update_clock_gating(adev, 1393 state == AMD_CG_STATE_GATE); 1394 soc15_update_drm_clock_gating(adev, 1395 state == AMD_CG_STATE_GATE); 1396 soc15_update_drm_light_sleep(adev, 1397 state == AMD_CG_STATE_GATE); 1398 adev->smuio.funcs->update_rom_clock_gating(adev, 1399 state == AMD_CG_STATE_GATE); 1400 adev->df.funcs->update_medium_grain_clock_gating(adev, 1401 state == AMD_CG_STATE_GATE); 1402 break; 1403 case IP_VERSION(7, 0, 0): 1404 case IP_VERSION(7, 0, 1): 1405 case IP_VERSION(2, 5, 0): 1406 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1407 state == AMD_CG_STATE_GATE); 1408 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1409 state == AMD_CG_STATE_GATE); 1410 adev->hdp.funcs->update_clock_gating(adev, 1411 state == AMD_CG_STATE_GATE); 1412 soc15_update_drm_clock_gating(adev, 1413 state == AMD_CG_STATE_GATE); 1414 soc15_update_drm_light_sleep(adev, 1415 state == AMD_CG_STATE_GATE); 1416 break; 1417 case IP_VERSION(7, 4, 1): 1418 case IP_VERSION(7, 4, 4): 1419 adev->hdp.funcs->update_clock_gating(adev, 1420 state == AMD_CG_STATE_GATE); 1421 break; 1422 default: 1423 break; 1424 } 1425 return 0; 1426 } 1427 1428 static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1429 { 1430 struct amdgpu_device *adev = ip_block->adev; 1431 int data; 1432 1433 if (amdgpu_sriov_vf(adev)) 1434 *flags = 0; 1435 1436 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1437 adev->nbio.funcs->get_clockgating_state(adev, flags); 1438 1439 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1440 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1441 1442 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1443 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && 1444 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && 1445 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) && 1446 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 15))) { 1447 /* AMD_CG_SUPPORT_DRM_MGCG */ 1448 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1449 if (!(data & 0x01000000)) 1450 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1451 1452 /* AMD_CG_SUPPORT_DRM_LS */ 1453 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1454 if (data & 0x1) 1455 *flags |= AMD_CG_SUPPORT_DRM_LS; 1456 } 1457 1458 /* AMD_CG_SUPPORT_ROM_MGCG */ 1459 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1460 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1461 1462 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1463 adev->df.funcs->get_clockgating_state(adev, flags); 1464 } 1465 1466 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1467 enum amd_powergating_state state) 1468 { 1469 /* todo */ 1470 return 0; 1471 } 1472 1473 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1474 .name = "soc15_common", 1475 .early_init = soc15_common_early_init, 1476 .late_init = soc15_common_late_init, 1477 .sw_init = soc15_common_sw_init, 1478 .sw_fini = soc15_common_sw_fini, 1479 .hw_init = soc15_common_hw_init, 1480 .hw_fini = soc15_common_hw_fini, 1481 .suspend = soc15_common_suspend, 1482 .resume = soc15_common_resume, 1483 .is_idle = soc15_common_is_idle, 1484 .set_clockgating_state = soc15_common_set_clockgating_state, 1485 .set_powergating_state = soc15_common_set_powergating_state, 1486 .get_clockgating_state= soc15_common_get_clockgating_state, 1487 }; 1488