1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "uvd/uvd_7_0_offset.h" 41 #include "gc/gc_9_0_offset.h" 42 #include "gc/gc_9_0_sh_mask.h" 43 #include "sdma0/sdma0_4_0_offset.h" 44 #include "sdma1/sdma1_4_0_offset.h" 45 #include "nbio/nbio_7_0_default.h" 46 #include "nbio/nbio_7_0_offset.h" 47 #include "nbio/nbio_7_0_sh_mask.h" 48 #include "nbio/nbio_7_0_smn.h" 49 #include "mp/mp_9_0_offset.h" 50 51 #include "soc15.h" 52 #include "soc15_common.h" 53 #include "gfx_v9_0.h" 54 #include "gmc_v9_0.h" 55 #include "gfxhub_v1_0.h" 56 #include "mmhub_v1_0.h" 57 #include "df_v1_7.h" 58 #include "df_v3_6.h" 59 #include "nbio_v6_1.h" 60 #include "nbio_v7_0.h" 61 #include "nbio_v7_4.h" 62 #include "hdp_v4_0.h" 63 #include "vega10_ih.h" 64 #include "vega20_ih.h" 65 #include "navi10_ih.h" 66 #include "sdma_v4_0.h" 67 #include "uvd_v7_0.h" 68 #include "vce_v4_0.h" 69 #include "vcn_v1_0.h" 70 #include "vcn_v2_0.h" 71 #include "jpeg_v2_0.h" 72 #include "vcn_v2_5.h" 73 #include "jpeg_v2_5.h" 74 #include "smuio_v9_0.h" 75 #include "smuio_v11_0.h" 76 #include "smuio_v13_0.h" 77 #include "amdgpu_vkms.h" 78 #include "mxgpu_ai.h" 79 #include "amdgpu_ras.h" 80 #include "amdgpu_xgmi.h" 81 #include <uapi/linux/kfd_ioctl.h> 82 83 #define mmMP0_MISC_CGTT_CTRL0 0x01b9 84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX 0 85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba 86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0 87 88 static const struct amd_ip_funcs soc15_common_ip_funcs; 89 90 /* Vega, Raven, Arcturus */ 91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] = 92 { 93 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 94 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 95 }; 96 97 static const struct amdgpu_video_codecs vega_video_codecs_encode = 98 { 99 .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array), 100 .codec_array = vega_video_codecs_encode_array, 101 }; 102 103 /* Vega */ 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] = 105 { 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 112 }; 113 114 static const struct amdgpu_video_codecs vega_video_codecs_decode = 115 { 116 .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array), 117 .codec_array = vega_video_codecs_decode_array, 118 }; 119 120 /* Raven */ 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] = 122 { 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 126 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 127 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)}, 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)}, 130 }; 131 132 static const struct amdgpu_video_codecs rv_video_codecs_decode = 133 { 134 .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array), 135 .codec_array = rv_video_codecs_decode_array, 136 }; 137 138 /* Renoir, Arcturus */ 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] = 140 { 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 142 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 143 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 148 }; 149 150 static const struct amdgpu_video_codecs rn_video_codecs_decode = 151 { 152 .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array), 153 .codec_array = rn_video_codecs_decode_array, 154 }; 155 156 static const struct amdgpu_video_codec_info vcn_4_0_3_video_codecs_decode_array[] = { 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 162 }; 163 164 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_decode = { 165 .codec_count = ARRAY_SIZE(vcn_4_0_3_video_codecs_decode_array), 166 .codec_array = vcn_4_0_3_video_codecs_decode_array, 167 }; 168 169 static const struct amdgpu_video_codecs vcn_4_0_3_video_codecs_encode = { 170 .codec_count = 0, 171 .codec_array = NULL, 172 }; 173 174 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_encode_vcn0 = { 175 .codec_count = 0, 176 .codec_array = NULL, 177 }; 178 179 static const struct amdgpu_video_codec_info vcn_5_0_1_video_codecs_decode_array_vcn0[] = { 180 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 184 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 185 }; 186 187 static const struct amdgpu_video_codecs vcn_5_0_1_video_codecs_decode_vcn0 = { 188 .codec_count = ARRAY_SIZE(vcn_5_0_1_video_codecs_decode_array_vcn0), 189 .codec_array = vcn_5_0_1_video_codecs_decode_array_vcn0, 190 }; 191 192 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, 193 const struct amdgpu_video_codecs **codecs) 194 { 195 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 196 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 197 case IP_VERSION(4, 0, 0): 198 case IP_VERSION(4, 1, 0): 199 if (encode) 200 *codecs = &vega_video_codecs_encode; 201 else 202 *codecs = &vega_video_codecs_decode; 203 return 0; 204 default: 205 return -EINVAL; 206 } 207 } else { 208 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 209 case IP_VERSION(1, 0, 0): 210 case IP_VERSION(1, 0, 1): 211 if (encode) 212 *codecs = &vega_video_codecs_encode; 213 else 214 *codecs = &rv_video_codecs_decode; 215 return 0; 216 case IP_VERSION(2, 5, 0): 217 case IP_VERSION(2, 6, 0): 218 case IP_VERSION(2, 2, 0): 219 if (encode) 220 *codecs = &vega_video_codecs_encode; 221 else 222 *codecs = &rn_video_codecs_decode; 223 return 0; 224 case IP_VERSION(4, 0, 3): 225 if (encode) 226 *codecs = &vcn_4_0_3_video_codecs_encode; 227 else 228 *codecs = &vcn_4_0_3_video_codecs_decode; 229 return 0; 230 case IP_VERSION(5, 0, 1): 231 if (encode) 232 *codecs = &vcn_5_0_1_video_codecs_encode_vcn0; 233 else 234 *codecs = &vcn_5_0_1_video_codecs_decode_vcn0; 235 return 0; 236 default: 237 return -EINVAL; 238 } 239 } 240 } 241 242 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 243 { 244 unsigned long flags, address, data; 245 u32 r; 246 247 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 248 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 249 250 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 251 WREG32(address, ((reg) & 0x1ff)); 252 r = RREG32(data); 253 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 254 return r; 255 } 256 257 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 258 { 259 unsigned long flags, address, data; 260 261 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); 262 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); 263 264 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 265 WREG32(address, ((reg) & 0x1ff)); 266 WREG32(data, (v)); 267 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 268 } 269 270 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) 271 { 272 unsigned long flags, address, data; 273 u32 r; 274 275 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 276 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 277 278 spin_lock_irqsave(&adev->didt_idx_lock, flags); 279 WREG32(address, (reg)); 280 r = RREG32(data); 281 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 282 return r; 283 } 284 285 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 286 { 287 unsigned long flags, address, data; 288 289 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 290 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 291 292 spin_lock_irqsave(&adev->didt_idx_lock, flags); 293 WREG32(address, (reg)); 294 WREG32(data, (v)); 295 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 296 } 297 298 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) 299 { 300 unsigned long flags; 301 u32 r; 302 303 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 304 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 305 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 306 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 307 return r; 308 } 309 310 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 311 { 312 unsigned long flags; 313 314 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 315 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 316 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 317 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 318 } 319 320 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) 321 { 322 unsigned long flags; 323 u32 r; 324 325 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 326 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 327 r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); 328 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 329 return r; 330 } 331 332 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 333 { 334 unsigned long flags; 335 336 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); 337 WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); 338 WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); 339 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); 340 } 341 342 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) 343 { 344 return adev->nbio.funcs->get_memsize(adev); 345 } 346 347 static u32 soc15_get_xclk(struct amdgpu_device *adev) 348 { 349 u32 reference_clock = adev->clock.spll.reference_freq; 350 351 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || 352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || 353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || 354 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || 355 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) 356 return 10000; 357 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || 358 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) 359 return reference_clock / 4; 360 361 return reference_clock; 362 } 363 364 365 void soc15_grbm_select(struct amdgpu_device *adev, 366 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id) 367 { 368 u32 grbm_gfx_cntl = 0; 369 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 370 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 371 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 372 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 373 374 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 375 } 376 377 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) 378 { 379 /* todo */ 380 return false; 381 } 382 383 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = { 384 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 385 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 386 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 387 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 388 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 389 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 390 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 391 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 392 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 393 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 394 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 395 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 396 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 397 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 398 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 399 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 400 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 401 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 402 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 403 { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)}, 404 }; 405 406 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 407 u32 sh_num, u32 reg_offset) 408 { 409 uint32_t val; 410 411 mutex_lock(&adev->grbm_idx_mutex); 412 if (se_num != 0xffffffff || sh_num != 0xffffffff) 413 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 414 415 val = RREG32(reg_offset); 416 417 if (se_num != 0xffffffff || sh_num != 0xffffffff) 418 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 419 mutex_unlock(&adev->grbm_idx_mutex); 420 return val; 421 } 422 423 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, 424 bool indexed, u32 se_num, 425 u32 sh_num, u32 reg_offset) 426 { 427 if (indexed) { 428 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); 429 } else { 430 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 431 return adev->gfx.config.gb_addr_config; 432 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) 433 return adev->gfx.config.db_debug2; 434 return RREG32(reg_offset); 435 } 436 } 437 438 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, 439 u32 sh_num, u32 reg_offset, u32 *value) 440 { 441 uint32_t i; 442 struct soc15_allowed_register_entry *en; 443 444 *value = 0; 445 for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) { 446 en = &soc15_allowed_read_registers[i]; 447 if (!adev->reg_offset[en->hwip][en->inst]) 448 continue; 449 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 450 + en->reg_offset)) 451 continue; 452 453 *value = soc15_get_register_value(adev, 454 soc15_allowed_read_registers[i].grbm_indexed, 455 se_num, sh_num, reg_offset); 456 return 0; 457 } 458 return -EINVAL; 459 } 460 461 462 /** 463 * soc15_program_register_sequence - program an array of registers. 464 * 465 * @adev: amdgpu_device pointer 466 * @regs: pointer to the register array 467 * @array_size: size of the register array 468 * 469 * Programs an array or registers with and and or masks. 470 * This is a helper for setting golden registers. 471 */ 472 473 void soc15_program_register_sequence(struct amdgpu_device *adev, 474 const struct soc15_reg_golden *regs, 475 const u32 array_size) 476 { 477 const struct soc15_reg_golden *entry; 478 u32 tmp, reg; 479 int i; 480 481 for (i = 0; i < array_size; ++i) { 482 entry = ®s[i]; 483 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 484 485 if (entry->and_mask == 0xffffffff) { 486 tmp = entry->or_mask; 487 } else { 488 tmp = (entry->hwip == GC_HWIP) ? 489 RREG32_SOC15_IP(GC, reg) : RREG32(reg); 490 491 tmp &= ~(entry->and_mask); 492 tmp |= (entry->or_mask & entry->and_mask); 493 } 494 495 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) || 496 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) || 497 reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) || 498 reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG)) 499 WREG32_RLC(reg, tmp); 500 else 501 (entry->hwip == GC_HWIP) ? 502 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp); 503 504 } 505 506 } 507 508 static int soc15_asic_baco_reset(struct amdgpu_device *adev) 509 { 510 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 511 int ret = 0; 512 513 /* avoid NBIF got stuck when do RAS recovery in BACO reset */ 514 if (ras && adev->ras_enabled) 515 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); 516 517 ret = amdgpu_dpm_baco_reset(adev); 518 if (ret) 519 return ret; 520 521 /* re-enable doorbell interrupt after BACO exit */ 522 if (ras && adev->ras_enabled) 523 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); 524 525 return 0; 526 } 527 528 static enum amd_reset_method 529 soc15_asic_reset_method(struct amdgpu_device *adev) 530 { 531 int baco_reset = 0; 532 bool connected_to_cpu = false; 533 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 534 535 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) 536 connected_to_cpu = true; 537 538 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 539 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 540 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 541 amdgpu_reset_method == AMD_RESET_METHOD_PCI) { 542 /* If connected to cpu, driver only support mode2 */ 543 if (connected_to_cpu) 544 return AMD_RESET_METHOD_MODE2; 545 return amdgpu_reset_method; 546 } 547 548 if (amdgpu_reset_method != -1) 549 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 550 amdgpu_reset_method); 551 552 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 553 case IP_VERSION(10, 0, 0): 554 case IP_VERSION(10, 0, 1): 555 case IP_VERSION(12, 0, 0): 556 case IP_VERSION(12, 0, 1): 557 return AMD_RESET_METHOD_MODE2; 558 case IP_VERSION(9, 0, 0): 559 case IP_VERSION(11, 0, 2): 560 if (adev->asic_type == CHIP_VEGA20) { 561 if (adev->psp.sos.fw_version >= 0x80067) 562 baco_reset = amdgpu_dpm_is_baco_supported(adev); 563 /* 564 * 1. PMFW version > 0x284300: all cases use baco 565 * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco 566 */ 567 if (ras && adev->ras_enabled && 568 adev->pm.fw_version <= 0x283400) 569 baco_reset = 0; 570 } else { 571 baco_reset = amdgpu_dpm_is_baco_supported(adev); 572 } 573 break; 574 case IP_VERSION(13, 0, 2): 575 /* 576 * 1.connected to cpu: driver issue mode2 reset 577 * 2.discret gpu: driver issue mode1 reset 578 */ 579 if (connected_to_cpu) 580 return AMD_RESET_METHOD_MODE2; 581 break; 582 case IP_VERSION(13, 0, 6): 583 case IP_VERSION(13, 0, 14): 584 case IP_VERSION(13, 0, 12): 585 /* Use gpu_recovery param to target a reset method. 586 * Enable triggering of GPU reset only if specified 587 * by module parameter. 588 */ 589 if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) 590 return AMD_RESET_METHOD_MODE2; 591 else if (!(adev->flags & AMD_IS_APU)) 592 return AMD_RESET_METHOD_MODE1; 593 else 594 return AMD_RESET_METHOD_MODE2; 595 default: 596 break; 597 } 598 599 if (baco_reset) 600 return AMD_RESET_METHOD_BACO; 601 else 602 return AMD_RESET_METHOD_MODE1; 603 } 604 605 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) 606 { 607 /* Will reset for the following suspend abort cases. 608 * 1) S3 suspend aborted in the normal S3 suspend 609 * 2) S3 suspend aborted in performing pm core test. 610 */ 611 if (adev->in_s3 && !pm_resume_via_firmware()) 612 return true; 613 else 614 return false; 615 } 616 617 static int soc15_asic_reset(struct amdgpu_device *adev) 618 { 619 /* original raven doesn't have full asic reset */ 620 /* On the latest Raven, the GPU reset can be performed 621 * successfully. So now, temporarily enable it for the 622 * S3 suspend abort case. 623 */ 624 625 if ((adev->apu_flags & AMD_APU_IS_PICASSO || 626 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && 627 soc15_need_reset_on_resume(adev)) 628 goto asic_reset; 629 630 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || 631 (adev->apu_flags & AMD_APU_IS_RAVEN2)) 632 return 0; 633 634 asic_reset: 635 switch (soc15_asic_reset_method(adev)) { 636 case AMD_RESET_METHOD_PCI: 637 dev_info(adev->dev, "PCI reset\n"); 638 return amdgpu_device_pci_reset(adev); 639 case AMD_RESET_METHOD_BACO: 640 dev_info(adev->dev, "BACO reset\n"); 641 return soc15_asic_baco_reset(adev); 642 case AMD_RESET_METHOD_MODE2: 643 dev_info(adev->dev, "MODE2 reset\n"); 644 return amdgpu_dpm_mode2_reset(adev); 645 default: 646 dev_info(adev->dev, "MODE1 reset\n"); 647 return amdgpu_device_mode1_reset(adev); 648 } 649 } 650 651 static int soc15_supports_baco(struct amdgpu_device *adev) 652 { 653 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 654 case IP_VERSION(9, 0, 0): 655 case IP_VERSION(11, 0, 2): 656 if (adev->asic_type == CHIP_VEGA20) { 657 if (adev->psp.sos.fw_version >= 0x80067) 658 return amdgpu_dpm_is_baco_supported(adev); 659 return 0; 660 } else { 661 return amdgpu_dpm_is_baco_supported(adev); 662 } 663 break; 664 default: 665 return 0; 666 } 667 } 668 669 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 670 u32 cntl_reg, u32 status_reg) 671 { 672 return 0; 673 }*/ 674 675 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 676 { 677 /*int r; 678 679 r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 680 if (r) 681 return r; 682 683 r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 684 */ 685 return 0; 686 } 687 688 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 689 { 690 /* todo */ 691 692 return 0; 693 } 694 695 static void soc15_program_aspm(struct amdgpu_device *adev) 696 { 697 if (!amdgpu_device_should_use_aspm(adev)) 698 return; 699 700 if (adev->nbio.funcs->program_aspm) 701 adev->nbio.funcs->program_aspm(adev); 702 } 703 704 const struct amdgpu_ip_block_version vega10_common_ip_block = 705 { 706 .type = AMD_IP_BLOCK_TYPE_COMMON, 707 .major = 2, 708 .minor = 0, 709 .rev = 0, 710 .funcs = &soc15_common_ip_funcs, 711 }; 712 713 static void soc15_reg_base_init(struct amdgpu_device *adev) 714 { 715 /* Set IP register base before any HW register access */ 716 switch (adev->asic_type) { 717 case CHIP_VEGA10: 718 case CHIP_VEGA12: 719 case CHIP_RAVEN: 720 case CHIP_RENOIR: 721 vega10_reg_base_init(adev); 722 break; 723 case CHIP_VEGA20: 724 vega20_reg_base_init(adev); 725 break; 726 case CHIP_ARCTURUS: 727 arct_reg_base_init(adev); 728 break; 729 case CHIP_ALDEBARAN: 730 aldebaran_reg_base_init(adev); 731 break; 732 default: 733 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); 734 break; 735 } 736 } 737 738 void soc15_set_virt_ops(struct amdgpu_device *adev) 739 { 740 adev->virt.ops = &xgpu_ai_virt_ops; 741 742 /* init soc15 reg base early enough so we can 743 * request request full access for sriov before 744 * set_ip_blocks. */ 745 soc15_reg_base_init(adev); 746 } 747 748 static bool soc15_need_full_reset(struct amdgpu_device *adev) 749 { 750 /* change this when we implement soft reset */ 751 return true; 752 } 753 754 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 755 uint64_t *count1) 756 { 757 uint32_t perfctr = 0; 758 uint64_t cnt0_of, cnt1_of; 759 int tmp; 760 761 /* This reports 0 on APUs, so return to avoid writing/reading registers 762 * that may or may not be different from their GPU counterparts 763 */ 764 if (adev->flags & AMD_IS_APU) 765 return; 766 767 /* Set the 2 events that we wish to watch, defined above */ 768 /* Reg 40 is # received msgs */ 769 /* Reg 104 is # of posted requests sent */ 770 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 771 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 772 773 /* Write to enable desired perf counters */ 774 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); 775 /* Zero out and enable the perf counters 776 * Write 0x5: 777 * Bit 0 = Start all counters(1) 778 * Bit 2 = Global counter reset enable(1) 779 */ 780 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 781 782 msleep(1000); 783 784 /* Load the shadow and disable the perf counters 785 * Write 0x2: 786 * Bit 0 = Stop counters(0) 787 * Bit 1 = Load the shadow counters(1) 788 */ 789 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 790 791 /* Read register values to get any >32bit overflow */ 792 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); 793 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 794 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 795 796 /* Get the values and add the overflow */ 797 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 798 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 799 } 800 801 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 802 uint64_t *count1) 803 { 804 uint32_t perfctr = 0; 805 uint64_t cnt0_of, cnt1_of; 806 int tmp; 807 808 /* This reports 0 on APUs, so return to avoid writing/reading registers 809 * that may or may not be different from their GPU counterparts 810 */ 811 if (adev->flags & AMD_IS_APU) 812 return; 813 814 /* Set the 2 events that we wish to watch, defined above */ 815 /* Reg 40 is # received msgs */ 816 /* Reg 108 is # of posted requests sent on VG20 */ 817 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 818 EVENT0_SEL, 40); 819 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3, 820 EVENT1_SEL, 108); 821 822 /* Write to enable desired perf counters */ 823 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); 824 /* Zero out and enable the perf counters 825 * Write 0x5: 826 * Bit 0 = Start all counters(1) 827 * Bit 2 = Global counter reset enable(1) 828 */ 829 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); 830 831 msleep(1000); 832 833 /* Load the shadow and disable the perf counters 834 * Write 0x2: 835 * Bit 0 = Stop counters(0) 836 * Bit 1 = Load the shadow counters(1) 837 */ 838 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); 839 840 /* Read register values to get any >32bit overflow */ 841 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); 842 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER); 843 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER); 844 845 /* Get the values and add the overflow */ 846 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); 847 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); 848 } 849 850 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) 851 { 852 u32 sol_reg; 853 854 /* CP hangs in IGT reloading test on RN, reset to WA */ 855 if (adev->asic_type == CHIP_RENOIR) 856 return true; 857 858 if (amdgpu_gmc_need_reset_on_init(adev)) 859 return true; 860 if (amdgpu_psp_tos_reload_needed(adev)) 861 return true; 862 /* Just return false for soc15 GPUs. Reset does not seem to 863 * be necessary. 864 */ 865 if (!amdgpu_passthrough(adev)) 866 return false; 867 868 if (adev->flags & AMD_IS_APU) 869 return false; 870 871 /* Check sOS sign of life register to confirm sys driver and sOS 872 * are already been loaded. 873 */ 874 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 875 if (sol_reg) 876 return true; 877 878 return false; 879 } 880 881 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) 882 { 883 uint64_t nak_r, nak_g; 884 885 /* Get the number of NAKs received and generated */ 886 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); 887 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); 888 889 /* Add the total number of NAKs, i.e the number of replays */ 890 return (nak_r + nak_g); 891 } 892 893 static void soc15_pre_asic_init(struct amdgpu_device *adev) 894 { 895 gmc_v9_0_restore_registers(adev); 896 } 897 898 static const struct amdgpu_asic_funcs soc15_asic_funcs = 899 { 900 .read_disabled_bios = &soc15_read_disabled_bios, 901 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 902 .read_register = &soc15_read_register, 903 .reset = &soc15_asic_reset, 904 .reset_method = &soc15_asic_reset_method, 905 .get_xclk = &soc15_get_xclk, 906 .set_uvd_clocks = &soc15_set_uvd_clocks, 907 .set_vce_clocks = &soc15_set_vce_clocks, 908 .get_config_memsize = &soc15_get_config_memsize, 909 .need_full_reset = &soc15_need_full_reset, 910 .init_doorbell_index = &vega10_doorbell_index_init, 911 .get_pcie_usage = &soc15_get_pcie_usage, 912 .need_reset_on_init = &soc15_need_reset_on_init, 913 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 914 .supports_baco = &soc15_supports_baco, 915 .pre_asic_init = &soc15_pre_asic_init, 916 .query_video_codecs = &soc15_query_video_codecs, 917 }; 918 919 static const struct amdgpu_asic_funcs vega20_asic_funcs = 920 { 921 .read_disabled_bios = &soc15_read_disabled_bios, 922 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 923 .read_register = &soc15_read_register, 924 .reset = &soc15_asic_reset, 925 .reset_method = &soc15_asic_reset_method, 926 .get_xclk = &soc15_get_xclk, 927 .set_uvd_clocks = &soc15_set_uvd_clocks, 928 .set_vce_clocks = &soc15_set_vce_clocks, 929 .get_config_memsize = &soc15_get_config_memsize, 930 .need_full_reset = &soc15_need_full_reset, 931 .init_doorbell_index = &vega20_doorbell_index_init, 932 .get_pcie_usage = &vega20_get_pcie_usage, 933 .need_reset_on_init = &soc15_need_reset_on_init, 934 .get_pcie_replay_count = &soc15_get_pcie_replay_count, 935 .supports_baco = &soc15_supports_baco, 936 .pre_asic_init = &soc15_pre_asic_init, 937 .query_video_codecs = &soc15_query_video_codecs, 938 }; 939 940 static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = 941 { 942 .read_disabled_bios = &soc15_read_disabled_bios, 943 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 944 .read_register = &soc15_read_register, 945 .reset = &soc15_asic_reset, 946 .reset_method = &soc15_asic_reset_method, 947 .get_xclk = &soc15_get_xclk, 948 .set_uvd_clocks = &soc15_set_uvd_clocks, 949 .set_vce_clocks = &soc15_set_vce_clocks, 950 .get_config_memsize = &soc15_get_config_memsize, 951 .need_full_reset = &soc15_need_full_reset, 952 .init_doorbell_index = &aqua_vanjaram_doorbell_index_init, 953 .need_reset_on_init = &soc15_need_reset_on_init, 954 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 955 .supports_baco = &soc15_supports_baco, 956 .pre_asic_init = &soc15_pre_asic_init, 957 .query_video_codecs = &soc15_query_video_codecs, 958 .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, 959 .get_reg_state = &aqua_vanjaram_get_reg_state, 960 }; 961 962 static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) 963 { 964 struct amdgpu_device *adev = ip_block->adev; 965 966 adev->nbio.funcs->set_reg_remap(adev); 967 adev->smc_rreg = NULL; 968 adev->smc_wreg = NULL; 969 adev->pcie_rreg = &amdgpu_device_indirect_rreg; 970 adev->pcie_wreg = &amdgpu_device_indirect_wreg; 971 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; 972 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; 973 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; 974 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; 975 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; 976 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; 977 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; 978 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; 979 adev->didt_rreg = &soc15_didt_rreg; 980 adev->didt_wreg = &soc15_didt_wreg; 981 adev->gc_cac_rreg = &soc15_gc_cac_rreg; 982 adev->gc_cac_wreg = &soc15_gc_cac_wreg; 983 adev->se_cac_rreg = &soc15_se_cac_rreg; 984 adev->se_cac_wreg = &soc15_se_cac_wreg; 985 986 adev->rev_id = amdgpu_device_get_rev_id(adev); 987 adev->external_rev_id = 0xFF; 988 /* TODO: split the GC and PG flags based on the relevant IP version for which 989 * they are relevant. 990 */ 991 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 992 case IP_VERSION(9, 0, 1): 993 adev->asic_funcs = &soc15_asic_funcs; 994 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 995 AMD_CG_SUPPORT_GFX_MGLS | 996 AMD_CG_SUPPORT_GFX_RLC_LS | 997 AMD_CG_SUPPORT_GFX_CP_LS | 998 AMD_CG_SUPPORT_GFX_3D_CGCG | 999 AMD_CG_SUPPORT_GFX_3D_CGLS | 1000 AMD_CG_SUPPORT_GFX_CGCG | 1001 AMD_CG_SUPPORT_GFX_CGLS | 1002 AMD_CG_SUPPORT_BIF_MGCG | 1003 AMD_CG_SUPPORT_BIF_LS | 1004 AMD_CG_SUPPORT_HDP_LS | 1005 AMD_CG_SUPPORT_DRM_MGCG | 1006 AMD_CG_SUPPORT_DRM_LS | 1007 AMD_CG_SUPPORT_ROM_MGCG | 1008 AMD_CG_SUPPORT_DF_MGCG | 1009 AMD_CG_SUPPORT_SDMA_MGCG | 1010 AMD_CG_SUPPORT_SDMA_LS | 1011 AMD_CG_SUPPORT_MC_MGCG | 1012 AMD_CG_SUPPORT_MC_LS; 1013 adev->pg_flags = 0; 1014 adev->external_rev_id = 0x1; 1015 break; 1016 case IP_VERSION(9, 2, 1): 1017 adev->asic_funcs = &soc15_asic_funcs; 1018 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1019 AMD_CG_SUPPORT_GFX_MGLS | 1020 AMD_CG_SUPPORT_GFX_CGCG | 1021 AMD_CG_SUPPORT_GFX_CGLS | 1022 AMD_CG_SUPPORT_GFX_3D_CGCG | 1023 AMD_CG_SUPPORT_GFX_3D_CGLS | 1024 AMD_CG_SUPPORT_GFX_CP_LS | 1025 AMD_CG_SUPPORT_MC_LS | 1026 AMD_CG_SUPPORT_MC_MGCG | 1027 AMD_CG_SUPPORT_SDMA_MGCG | 1028 AMD_CG_SUPPORT_SDMA_LS | 1029 AMD_CG_SUPPORT_BIF_MGCG | 1030 AMD_CG_SUPPORT_BIF_LS | 1031 AMD_CG_SUPPORT_HDP_MGCG | 1032 AMD_CG_SUPPORT_HDP_LS | 1033 AMD_CG_SUPPORT_ROM_MGCG | 1034 AMD_CG_SUPPORT_VCE_MGCG | 1035 AMD_CG_SUPPORT_UVD_MGCG; 1036 adev->pg_flags = 0; 1037 adev->external_rev_id = adev->rev_id + 0x14; 1038 break; 1039 case IP_VERSION(9, 4, 0): 1040 adev->asic_funcs = &vega20_asic_funcs; 1041 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1042 AMD_CG_SUPPORT_GFX_MGLS | 1043 AMD_CG_SUPPORT_GFX_CGCG | 1044 AMD_CG_SUPPORT_GFX_CGLS | 1045 AMD_CG_SUPPORT_GFX_3D_CGCG | 1046 AMD_CG_SUPPORT_GFX_3D_CGLS | 1047 AMD_CG_SUPPORT_GFX_CP_LS | 1048 AMD_CG_SUPPORT_MC_LS | 1049 AMD_CG_SUPPORT_MC_MGCG | 1050 AMD_CG_SUPPORT_SDMA_MGCG | 1051 AMD_CG_SUPPORT_SDMA_LS | 1052 AMD_CG_SUPPORT_BIF_MGCG | 1053 AMD_CG_SUPPORT_BIF_LS | 1054 AMD_CG_SUPPORT_HDP_MGCG | 1055 AMD_CG_SUPPORT_HDP_LS | 1056 AMD_CG_SUPPORT_ROM_MGCG | 1057 AMD_CG_SUPPORT_VCE_MGCG | 1058 AMD_CG_SUPPORT_UVD_MGCG; 1059 adev->pg_flags = 0; 1060 adev->external_rev_id = adev->rev_id + 0x28; 1061 break; 1062 case IP_VERSION(9, 1, 0): 1063 case IP_VERSION(9, 2, 2): 1064 adev->asic_funcs = &soc15_asic_funcs; 1065 1066 if (adev->rev_id >= 0x8) 1067 adev->apu_flags |= AMD_APU_IS_RAVEN2; 1068 1069 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 1070 adev->external_rev_id = adev->rev_id + 0x79; 1071 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 1072 adev->external_rev_id = adev->rev_id + 0x41; 1073 else if (adev->rev_id == 1) 1074 adev->external_rev_id = adev->rev_id + 0x20; 1075 else 1076 adev->external_rev_id = adev->rev_id + 0x01; 1077 1078 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1079 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1080 AMD_CG_SUPPORT_GFX_MGLS | 1081 AMD_CG_SUPPORT_GFX_CP_LS | 1082 AMD_CG_SUPPORT_GFX_3D_CGCG | 1083 AMD_CG_SUPPORT_GFX_3D_CGLS | 1084 AMD_CG_SUPPORT_GFX_CGCG | 1085 AMD_CG_SUPPORT_GFX_CGLS | 1086 AMD_CG_SUPPORT_BIF_LS | 1087 AMD_CG_SUPPORT_HDP_LS | 1088 AMD_CG_SUPPORT_MC_MGCG | 1089 AMD_CG_SUPPORT_MC_LS | 1090 AMD_CG_SUPPORT_SDMA_MGCG | 1091 AMD_CG_SUPPORT_SDMA_LS | 1092 AMD_CG_SUPPORT_VCN_MGCG; 1093 1094 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1095 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { 1096 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1097 AMD_CG_SUPPORT_GFX_MGLS | 1098 AMD_CG_SUPPORT_GFX_CP_LS | 1099 AMD_CG_SUPPORT_GFX_3D_CGLS | 1100 AMD_CG_SUPPORT_GFX_CGCG | 1101 AMD_CG_SUPPORT_GFX_CGLS | 1102 AMD_CG_SUPPORT_BIF_LS | 1103 AMD_CG_SUPPORT_HDP_LS | 1104 AMD_CG_SUPPORT_MC_MGCG | 1105 AMD_CG_SUPPORT_MC_LS | 1106 AMD_CG_SUPPORT_SDMA_MGCG | 1107 AMD_CG_SUPPORT_SDMA_LS | 1108 AMD_CG_SUPPORT_VCN_MGCG; 1109 1110 /* 1111 * MMHUB PG needs to be disabled for Picasso for 1112 * stability reasons. 1113 */ 1114 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1115 AMD_PG_SUPPORT_VCN; 1116 } else { 1117 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1118 AMD_CG_SUPPORT_GFX_MGLS | 1119 AMD_CG_SUPPORT_GFX_RLC_LS | 1120 AMD_CG_SUPPORT_GFX_CP_LS | 1121 AMD_CG_SUPPORT_GFX_3D_CGLS | 1122 AMD_CG_SUPPORT_GFX_CGCG | 1123 AMD_CG_SUPPORT_GFX_CGLS | 1124 AMD_CG_SUPPORT_BIF_MGCG | 1125 AMD_CG_SUPPORT_BIF_LS | 1126 AMD_CG_SUPPORT_HDP_MGCG | 1127 AMD_CG_SUPPORT_HDP_LS | 1128 AMD_CG_SUPPORT_DRM_MGCG | 1129 AMD_CG_SUPPORT_DRM_LS | 1130 AMD_CG_SUPPORT_MC_MGCG | 1131 AMD_CG_SUPPORT_MC_LS | 1132 AMD_CG_SUPPORT_SDMA_MGCG | 1133 AMD_CG_SUPPORT_SDMA_LS | 1134 AMD_CG_SUPPORT_VCN_MGCG; 1135 1136 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; 1137 } 1138 break; 1139 case IP_VERSION(9, 4, 1): 1140 adev->asic_funcs = &vega20_asic_funcs; 1141 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1142 AMD_CG_SUPPORT_GFX_MGLS | 1143 AMD_CG_SUPPORT_GFX_CGCG | 1144 AMD_CG_SUPPORT_GFX_CGLS | 1145 AMD_CG_SUPPORT_GFX_CP_LS | 1146 AMD_CG_SUPPORT_HDP_MGCG | 1147 AMD_CG_SUPPORT_HDP_LS | 1148 AMD_CG_SUPPORT_SDMA_MGCG | 1149 AMD_CG_SUPPORT_SDMA_LS | 1150 AMD_CG_SUPPORT_MC_MGCG | 1151 AMD_CG_SUPPORT_MC_LS | 1152 AMD_CG_SUPPORT_IH_CG | 1153 AMD_CG_SUPPORT_VCN_MGCG | 1154 AMD_CG_SUPPORT_JPEG_MGCG; 1155 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; 1156 adev->external_rev_id = adev->rev_id + 0x32; 1157 break; 1158 case IP_VERSION(9, 3, 0): 1159 adev->asic_funcs = &soc15_asic_funcs; 1160 1161 if (adev->apu_flags & AMD_APU_IS_RENOIR) 1162 adev->external_rev_id = adev->rev_id + 0x91; 1163 else 1164 adev->external_rev_id = adev->rev_id + 0xa1; 1165 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1166 AMD_CG_SUPPORT_GFX_MGLS | 1167 AMD_CG_SUPPORT_GFX_3D_CGCG | 1168 AMD_CG_SUPPORT_GFX_3D_CGLS | 1169 AMD_CG_SUPPORT_GFX_CGCG | 1170 AMD_CG_SUPPORT_GFX_CGLS | 1171 AMD_CG_SUPPORT_GFX_CP_LS | 1172 AMD_CG_SUPPORT_MC_MGCG | 1173 AMD_CG_SUPPORT_MC_LS | 1174 AMD_CG_SUPPORT_SDMA_MGCG | 1175 AMD_CG_SUPPORT_SDMA_LS | 1176 AMD_CG_SUPPORT_BIF_LS | 1177 AMD_CG_SUPPORT_HDP_LS | 1178 AMD_CG_SUPPORT_VCN_MGCG | 1179 AMD_CG_SUPPORT_JPEG_MGCG | 1180 AMD_CG_SUPPORT_IH_CG | 1181 AMD_CG_SUPPORT_ATHUB_LS | 1182 AMD_CG_SUPPORT_ATHUB_MGCG | 1183 AMD_CG_SUPPORT_DF_MGCG; 1184 adev->pg_flags = AMD_PG_SUPPORT_SDMA | 1185 AMD_PG_SUPPORT_VCN | 1186 AMD_PG_SUPPORT_JPEG | 1187 AMD_PG_SUPPORT_VCN_DPG; 1188 break; 1189 case IP_VERSION(9, 4, 2): 1190 adev->asic_funcs = &vega20_asic_funcs; 1191 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1192 AMD_CG_SUPPORT_GFX_MGLS | 1193 AMD_CG_SUPPORT_GFX_CP_LS | 1194 AMD_CG_SUPPORT_HDP_LS | 1195 AMD_CG_SUPPORT_SDMA_MGCG | 1196 AMD_CG_SUPPORT_SDMA_LS | 1197 AMD_CG_SUPPORT_IH_CG | 1198 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG; 1199 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 1200 adev->external_rev_id = adev->rev_id + 0x3c; 1201 break; 1202 case IP_VERSION(9, 4, 3): 1203 case IP_VERSION(9, 4, 4): 1204 case IP_VERSION(9, 5, 0): 1205 adev->asic_funcs = &aqua_vanjaram_asic_funcs; 1206 adev->cg_flags = 1207 AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | 1208 AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | 1209 AMD_CG_SUPPORT_GFX_FGCG | AMD_CG_SUPPORT_REPEATER_FGCG | 1210 AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG | 1211 AMD_CG_SUPPORT_IH_CG; 1212 adev->pg_flags = 1213 AMD_PG_SUPPORT_VCN | 1214 AMD_PG_SUPPORT_VCN_DPG | 1215 AMD_PG_SUPPORT_JPEG; 1216 /*TODO: need a new external_rev_id for GC 9.4.4? */ 1217 adev->external_rev_id = adev->rev_id + 0x46; 1218 break; 1219 default: 1220 /* FIXME: not supported yet */ 1221 return -EINVAL; 1222 } 1223 1224 if (amdgpu_sriov_vf(adev)) { 1225 amdgpu_virt_init_setting(adev); 1226 xgpu_ai_mailbox_set_irq_funcs(adev); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) 1233 { 1234 struct amdgpu_device *adev = ip_block->adev; 1235 1236 if (amdgpu_sriov_vf(adev)) 1237 xgpu_ai_mailbox_get_irq(adev); 1238 1239 /* Enable selfring doorbell aperture late because doorbell BAR 1240 * aperture will change if resize BAR successfully in gmc sw_init. 1241 */ 1242 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 1243 1244 return 0; 1245 } 1246 1247 static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) 1248 { 1249 struct amdgpu_device *adev = ip_block->adev; 1250 1251 if (amdgpu_sriov_vf(adev)) 1252 xgpu_ai_mailbox_add_irq_id(adev); 1253 1254 if (adev->df.funcs && 1255 adev->df.funcs->sw_init) 1256 adev->df.funcs->sw_init(adev); 1257 1258 return 0; 1259 } 1260 1261 static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) 1262 { 1263 struct amdgpu_device *adev = ip_block->adev; 1264 1265 if (adev->df.funcs && 1266 adev->df.funcs->sw_fini) 1267 adev->df.funcs->sw_fini(adev); 1268 return 0; 1269 } 1270 1271 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) 1272 { 1273 int i; 1274 1275 /* sdma doorbell range is programed by hypervisor */ 1276 if (!amdgpu_sriov_vf(adev)) { 1277 for (i = 0; i < adev->sdma.num_instances; i++) { 1278 adev->nbio.funcs->sdma_doorbell_range(adev, i, 1279 true, adev->doorbell_index.sdma_engine[i] << 1, 1280 adev->doorbell_index.sdma_doorbell_range); 1281 } 1282 } 1283 } 1284 1285 static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) 1286 { 1287 struct amdgpu_device *adev = ip_block->adev; 1288 1289 /* enable aspm */ 1290 soc15_program_aspm(adev); 1291 /* setup nbio registers */ 1292 adev->nbio.funcs->init_registers(adev); 1293 /* remap HDP registers to a hole in mmio space, 1294 * for the purpose of expose those registers 1295 * to process space 1296 */ 1297 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1298 adev->nbio.funcs->remap_hdp_registers(adev); 1299 1300 /* enable the doorbell aperture */ 1301 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 1302 1303 /* HW doorbell routing policy: doorbell writing not 1304 * in SDMA/IH/MM/ACV range will be routed to CP. So 1305 * we need to init SDMA doorbell range prior 1306 * to CP ip block init and ring test. IH already 1307 * happens before CP. 1308 */ 1309 soc15_sdma_doorbell_range_init(adev); 1310 1311 return 0; 1312 } 1313 1314 static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) 1315 { 1316 struct amdgpu_device *adev = ip_block->adev; 1317 1318 /* Disable the doorbell aperture and selfring doorbell aperture 1319 * separately in hw_fini because soc15_enable_doorbell_aperture 1320 * has been removed and there is no need to delay disabling 1321 * selfring doorbell. 1322 */ 1323 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 1324 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 1325 1326 if (amdgpu_sriov_vf(adev)) 1327 xgpu_ai_mailbox_put_irq(adev); 1328 1329 /* 1330 * For minimal init, late_init is not called, hence RAS irqs are not 1331 * enabled. 1332 */ 1333 if ((!amdgpu_sriov_vf(adev)) && 1334 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && 1335 adev->nbio.ras_if && 1336 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { 1337 if (adev->nbio.ras && 1338 adev->nbio.ras->init_ras_controller_interrupt) 1339 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); 1340 if (adev->nbio.ras && 1341 adev->nbio.ras->init_ras_err_event_athub_interrupt) 1342 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) 1349 { 1350 return soc15_common_hw_fini(ip_block); 1351 } 1352 1353 static int soc15_common_resume(struct amdgpu_ip_block *ip_block) 1354 { 1355 struct amdgpu_device *adev = ip_block->adev; 1356 1357 if (soc15_need_reset_on_resume(adev)) { 1358 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); 1359 soc15_asic_reset(adev); 1360 } 1361 return soc15_common_hw_init(ip_block); 1362 } 1363 1364 static bool soc15_common_is_idle(void *handle) 1365 { 1366 return true; 1367 } 1368 1369 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) 1370 { 1371 uint32_t def, data; 1372 1373 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1374 1375 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) 1376 data &= ~(0x01000000 | 1377 0x02000000 | 1378 0x04000000 | 1379 0x08000000 | 1380 0x10000000 | 1381 0x20000000 | 1382 0x40000000 | 1383 0x80000000); 1384 else 1385 data |= (0x01000000 | 1386 0x02000000 | 1387 0x04000000 | 1388 0x08000000 | 1389 0x10000000 | 1390 0x20000000 | 1391 0x40000000 | 1392 0x80000000); 1393 1394 if (def != data) 1395 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data); 1396 } 1397 1398 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) 1399 { 1400 uint32_t def, data; 1401 1402 def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1403 1404 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) 1405 data |= 1; 1406 else 1407 data &= ~1; 1408 1409 if (def != data) 1410 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data); 1411 } 1412 1413 static int soc15_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1414 enum amd_clockgating_state state) 1415 { 1416 struct amdgpu_device *adev = ip_block->adev; 1417 1418 if (amdgpu_sriov_vf(adev)) 1419 return 0; 1420 1421 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1422 case IP_VERSION(6, 1, 0): 1423 case IP_VERSION(6, 2, 0): 1424 case IP_VERSION(7, 4, 0): 1425 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1426 state == AMD_CG_STATE_GATE); 1427 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1428 state == AMD_CG_STATE_GATE); 1429 adev->hdp.funcs->update_clock_gating(adev, 1430 state == AMD_CG_STATE_GATE); 1431 soc15_update_drm_clock_gating(adev, 1432 state == AMD_CG_STATE_GATE); 1433 soc15_update_drm_light_sleep(adev, 1434 state == AMD_CG_STATE_GATE); 1435 adev->smuio.funcs->update_rom_clock_gating(adev, 1436 state == AMD_CG_STATE_GATE); 1437 adev->df.funcs->update_medium_grain_clock_gating(adev, 1438 state == AMD_CG_STATE_GATE); 1439 break; 1440 case IP_VERSION(7, 0, 0): 1441 case IP_VERSION(7, 0, 1): 1442 case IP_VERSION(2, 5, 0): 1443 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1444 state == AMD_CG_STATE_GATE); 1445 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1446 state == AMD_CG_STATE_GATE); 1447 adev->hdp.funcs->update_clock_gating(adev, 1448 state == AMD_CG_STATE_GATE); 1449 soc15_update_drm_clock_gating(adev, 1450 state == AMD_CG_STATE_GATE); 1451 soc15_update_drm_light_sleep(adev, 1452 state == AMD_CG_STATE_GATE); 1453 break; 1454 case IP_VERSION(7, 4, 1): 1455 case IP_VERSION(7, 4, 4): 1456 adev->hdp.funcs->update_clock_gating(adev, 1457 state == AMD_CG_STATE_GATE); 1458 break; 1459 default: 1460 break; 1461 } 1462 return 0; 1463 } 1464 1465 static void soc15_common_get_clockgating_state(void *handle, u64 *flags) 1466 { 1467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1468 int data; 1469 1470 if (amdgpu_sriov_vf(adev)) 1471 *flags = 0; 1472 1473 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) 1474 adev->nbio.funcs->get_clockgating_state(adev, flags); 1475 1476 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) 1477 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1478 1479 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && 1480 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && 1481 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && 1482 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { 1483 /* AMD_CG_SUPPORT_DRM_MGCG */ 1484 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); 1485 if (!(data & 0x01000000)) 1486 *flags |= AMD_CG_SUPPORT_DRM_MGCG; 1487 1488 /* AMD_CG_SUPPORT_DRM_LS */ 1489 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL)); 1490 if (data & 0x1) 1491 *flags |= AMD_CG_SUPPORT_DRM_LS; 1492 } 1493 1494 /* AMD_CG_SUPPORT_ROM_MGCG */ 1495 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) 1496 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1497 1498 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) 1499 adev->df.funcs->get_clockgating_state(adev, flags); 1500 } 1501 1502 static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1503 enum amd_powergating_state state) 1504 { 1505 /* todo */ 1506 return 0; 1507 } 1508 1509 static const struct amd_ip_funcs soc15_common_ip_funcs = { 1510 .name = "soc15_common", 1511 .early_init = soc15_common_early_init, 1512 .late_init = soc15_common_late_init, 1513 .sw_init = soc15_common_sw_init, 1514 .sw_fini = soc15_common_sw_fini, 1515 .hw_init = soc15_common_hw_init, 1516 .hw_fini = soc15_common_hw_fini, 1517 .suspend = soc15_common_suspend, 1518 .resume = soc15_common_resume, 1519 .is_idle = soc15_common_is_idle, 1520 .set_clockgating_state = soc15_common_set_clockgating_state, 1521 .set_powergating_state = soc15_common_set_powergating_state, 1522 .get_clockgating_state= soc15_common_get_clockgating_state, 1523 }; 1524