1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "smuio_v15_0_8.h" 25 #include "smuio/smuio_15_0_8_offset.h" 26 #include "smuio/smuio_15_0_8_sh_mask.h" 27 28 #define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK 0x00000001L 29 #define SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK 0x00000008L 30 #define SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK 0x00000001L 31 32 static u32 smuio_v15_0_8_get_rom_index_offset(struct amdgpu_device *adev) 33 { 34 return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX); 35 } 36 37 static u32 smuio_v15_0_8_get_rom_data_offset(struct amdgpu_device *adev) 38 { 39 return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA); 40 } 41 42 static void smuio_v15_0_8_update_rom_clock_gating(struct amdgpu_device *adev, bool enable) 43 { 44 return; 45 } 46 47 static u64 smuio_v15_0_8_get_gpu_clock_counter(struct amdgpu_device *adev) 48 { 49 u64 clock; 50 u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; 51 52 preempt_disable(); 53 clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 54 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 55 /* the clock counter may be udpated during polling the counters */ 56 clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); 57 if (clock_counter_hi_pre != clock_counter_hi_after) 58 clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); 59 preempt_enable(); 60 61 clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); 62 63 return clock; 64 } 65 66 static void smuio_v15_0_8_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) 67 { 68 u32 data; 69 70 /* CGTT_ROM_CLK_CTRL0 is not available for APU */ 71 if (adev->flags & AMD_IS_APU) 72 return; 73 74 data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); 75 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) 76 *flags |= AMD_CG_SUPPORT_ROM_MGCG; 77 } 78 79 /** 80 * smuio_v15_0_8_get_die_id - query die id from FCH. 81 * 82 * @adev: amdgpu device pointer 83 * 84 * Returns die id 85 */ 86 static u32 smuio_v15_0_8_get_die_id(struct amdgpu_device *adev) 87 { 88 u32 data, die_id; 89 90 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 91 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); 92 93 return die_id; 94 } 95 96 /** 97 * smuio_v15_0_8_get_socket_id - query socket id from FCH 98 * 99 * @adev: amdgpu device pointer 100 * 101 * Returns socket id 102 */ 103 static u32 smuio_v15_0_8_get_socket_id(struct amdgpu_device *adev) 104 { 105 u32 data, socket_id; 106 107 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 108 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); 109 110 return socket_id; 111 } 112 113 /** 114 * smuio_v15_0_8_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s. 115 * 116 * @adev: amdgpu device pointer 117 * 118 * Returns true on success or false otherwise. 119 */ 120 static bool smuio_v15_0_8_is_host_gpu_xgmi_supported(struct amdgpu_device *adev) 121 { 122 u32 data; 123 124 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 125 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); 126 /* data[4:0] 127 * bit 0 == 0 host-gpu interface is PCIE 128 * bit 0 == 1 host-gpu interface is Alternate Protocal 129 * for AMD, this is XGMI 130 */ 131 data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK; 132 133 return data ? true : false; 134 } 135 136 #if 0 137 /* 138 * smuio_v15_0_8_is_connected_with_ethernet_switch - detect systems connected with ethernet switch 139 * 140 * @adev: amdgpu device pointer 141 * 142 * Returns true on success or false otherwise. 143 */ 144 static bool smuio_v15_0_8_is_connected_with_ethernet_switch(struct amdgpu_device *adev) 145 { 146 u32 data; 147 148 if (!(adev->flags & AMD_IS_APU)) 149 return false; 150 151 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 152 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); 153 /* data[4:0] 154 * bit 3 == 0 systems connected with ethernet switch 155 */ 156 data &= SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK; 157 158 return data ? false : true; 159 } 160 #endif 161 162 static enum amdgpu_pkg_type smuio_v15_0_8_get_pkg_type(struct amdgpu_device *adev) 163 { 164 enum amdgpu_pkg_type pkg_type; 165 u32 data; 166 167 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 168 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); 169 170 /* data [3:0] 171 bit 2 and bit 3 identifies the pkg type */ 172 switch (data & 0xC) { 173 case 0x0: 174 pkg_type = AMDGPU_PKG_TYPE_BB; 175 break; 176 case 0x8: 177 pkg_type = AMDGPU_PKG_TYPE_CEM; 178 break; 179 default: 180 pkg_type = AMDGPU_PKG_TYPE_UNKNOWN; 181 break; 182 } 183 184 return pkg_type; 185 } 186 187 #if 0 188 static bool smuio_v15_0_8_is_custom_hbm_supported(struct amdgpu_device *adev) 189 { 190 u32 data; 191 192 data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); 193 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); 194 195 /* data [3:0] 196 * bit 0 identifies custom HBM module */ 197 data &= SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK; 198 199 return data ? true : false; 200 } 201 #endif 202 203 const struct amdgpu_smuio_funcs smuio_v15_0_8_funcs = { 204 .get_rom_index_offset = smuio_v15_0_8_get_rom_index_offset, 205 .get_rom_data_offset = smuio_v15_0_8_get_rom_data_offset, 206 .get_gpu_clock_counter = smuio_v15_0_8_get_gpu_clock_counter, 207 .get_die_id = smuio_v15_0_8_get_die_id, 208 .get_socket_id = smuio_v15_0_8_get_socket_id, 209 .is_host_gpu_xgmi_supported = smuio_v15_0_8_is_host_gpu_xgmi_supported, 210 .update_rom_clock_gating = smuio_v15_0_8_update_rom_clock_gating, 211 .get_clock_gating_state = smuio_v15_0_8_get_clock_gating_state, 212 .get_pkg_type = smuio_v15_0_8_get_pkg_type, 213 }; 214