1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smuio/smuio_11_0_0_offset.h" 25 #include "smuio/smuio_11_0_0_sh_mask.h" 26 27 #include "smu_v11_0_i2c.h" 28 #include "amdgpu.h" 29 #include "soc15_common.h" 30 #include <drm/drm_fixed.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_amdkfd.h" 33 #include <linux/i2c.h> 34 #include <linux/pci.h> 35 36 /* error codes */ 37 #define I2C_OK 0 38 #define I2C_NAK_7B_ADDR_NOACK 1 39 #define I2C_NAK_TXDATA_NOACK 2 40 #define I2C_TIMEOUT 4 41 #define I2C_SW_TIMEOUT 8 42 #define I2C_ABORT 0x10 43 44 /* I2C transaction flags */ 45 #define I2C_NO_STOP 1 46 #define I2C_RESTART 2 47 48 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) 49 50 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) 51 { 52 struct amdgpu_device *adev = to_amdgpu_device(control); 53 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); 54 55 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); 56 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); 57 } 58 59 60 static void smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) 61 { 62 struct amdgpu_device *adev = to_amdgpu_device(control); 63 64 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); 65 } 66 67 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) 68 { 69 struct amdgpu_device *adev = to_amdgpu_device(control); 70 /* do */ 71 { 72 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); 73 74 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */ 75 } 76 77 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) 78 { 79 struct amdgpu_device *adev = to_amdgpu_device(control); 80 uint32_t reg = 0; 81 82 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); 83 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); 84 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); 85 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); 86 /* Standard mode */ 87 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 2); 88 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); 89 90 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); 91 } 92 93 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) 94 { 95 struct amdgpu_device *adev = to_amdgpu_device(control); 96 97 /* 98 * Standard mode speed, These values are taken from SMUIO MAS, 99 * but are different from what is given is 100 * Synopsys spec. The values here are based on assumption 101 * that refclock is 100MHz 102 * 103 * Configuration for standard mode; Speed = 100kbps 104 * Scale linearly, for now only support standard speed clock 105 * This will work only with 100M ref clock 106 * 107 * TBD:Change the calculation to take into account ref clock values also. 108 */ 109 110 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2); 111 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120); 112 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130); 113 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20); 114 } 115 116 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, uint8_t address) 117 { 118 struct amdgpu_device *adev = to_amdgpu_device(control); 119 120 /* Convert fromr 8-bit to 7-bit address */ 121 address >>= 1; 122 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, (address & 0xFF)); 123 } 124 125 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) 126 { 127 struct amdgpu_device *adev = to_amdgpu_device(control); 128 uint32_t ret = I2C_OK; 129 uint32_t reg, reg_c_tx_abrt_source; 130 131 /*Check if transmission is completed */ 132 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 133 134 do { 135 if (time_after(jiffies, timeout_counter)) { 136 ret |= I2C_SW_TIMEOUT; 137 break; 138 } 139 140 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 141 142 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); 143 144 if (ret != I2C_OK) 145 return ret; 146 147 /* This only checks if NAK is received and transaction got aborted */ 148 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); 149 150 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { 151 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 152 DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source); 153 154 /* Check for stop due to NACK */ 155 if (REG_GET_FIELD(reg_c_tx_abrt_source, 156 CKSVII2C_IC_TX_ABRT_SOURCE, 157 ABRT_TXDATA_NOACK) == 1) { 158 159 ret |= I2C_NAK_TXDATA_NOACK; 160 161 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, 162 CKSVII2C_IC_TX_ABRT_SOURCE, 163 ABRT_7B_ADDR_NOACK) == 1) { 164 165 ret |= I2C_NAK_7B_ADDR_NOACK; 166 } else { 167 ret |= I2C_ABORT; 168 } 169 170 smu_v11_0_i2c_clear_status(control); 171 } 172 173 return ret; 174 } 175 176 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) 177 { 178 struct amdgpu_device *adev = to_amdgpu_device(control); 179 uint32_t ret = I2C_OK; 180 uint32_t reg_ic_status, reg_c_tx_abrt_source; 181 182 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 183 184 /* If slave is not present */ 185 if (REG_GET_FIELD(reg_c_tx_abrt_source, 186 CKSVII2C_IC_TX_ABRT_SOURCE, 187 ABRT_7B_ADDR_NOACK) == 1) { 188 ret |= I2C_NAK_7B_ADDR_NOACK; 189 190 smu_v11_0_i2c_clear_status(control); 191 } else { /* wait till some data is there in RXFIFO */ 192 /* Poll for some byte in RXFIFO */ 193 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 194 195 do { 196 if (time_after(jiffies, timeout_counter)) { 197 ret |= I2C_SW_TIMEOUT; 198 break; 199 } 200 201 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 202 203 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); 204 } 205 206 return ret; 207 } 208 209 210 211 212 /** 213 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device. 214 * 215 * @control: I2C adapter reference 216 * @address: The I2C address of the slave device. 217 * @data: The data to transmit over the bus. 218 * @numbytes: The amount of data to transmit. 219 * @i2c_flag: Flags for transmission 220 * 221 * Returns 0 on success or error. 222 */ 223 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, 224 uint8_t address, uint8_t *data, 225 uint32_t numbytes, uint32_t i2c_flag) 226 { 227 struct amdgpu_device *adev = to_amdgpu_device(control); 228 uint32_t bytes_sent, reg, ret = 0; 229 unsigned long timeout_counter; 230 231 bytes_sent = 0; 232 233 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ", 234 (uint16_t)address, numbytes); 235 236 if (drm_debug_enabled(DRM_UT_DRIVER)) { 237 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 238 16, 1, data, numbytes, false); 239 } 240 241 /* Set the I2C slave address */ 242 smu_v11_0_i2c_set_address(control, address); 243 /* Enable I2C */ 244 smu_v11_0_i2c_enable(control, true); 245 246 /* Clear status bits */ 247 smu_v11_0_i2c_clear_status(control); 248 249 250 timeout_counter = jiffies + msecs_to_jiffies(20); 251 252 while (numbytes > 0) { 253 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 254 if (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { 255 do { 256 reg = 0; 257 /* 258 * Prepare transaction, no need to set RESTART. I2C engine will send 259 * START as soon as it sees data in TXFIFO 260 */ 261 if (bytes_sent == 0) 262 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, 263 (i2c_flag & I2C_RESTART) ? 1 : 0); 264 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, data[bytes_sent]); 265 266 /* determine if we need to send STOP bit or not */ 267 if (numbytes == 1) 268 /* Final transaction, so send stop unless I2C_NO_STOP */ 269 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, 270 (i2c_flag & I2C_NO_STOP) ? 0 : 1); 271 /* Write */ 272 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0); 273 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 274 275 /* Record that the bytes were transmitted */ 276 bytes_sent++; 277 numbytes--; 278 279 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 280 281 } while (numbytes && REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)); 282 } 283 284 /* 285 * We waited too long for the transmission FIFO to become not-full. 286 * Exit the loop with error. 287 */ 288 if (time_after(jiffies, timeout_counter)) { 289 ret |= I2C_SW_TIMEOUT; 290 goto Err; 291 } 292 } 293 294 ret = smu_v11_0_i2c_poll_tx_status(control); 295 296 Err: 297 /* Any error, no point in proceeding */ 298 if (ret != I2C_OK) { 299 if (ret & I2C_SW_TIMEOUT) 300 DRM_ERROR("TIMEOUT ERROR !!!"); 301 302 if (ret & I2C_NAK_7B_ADDR_NOACK) 303 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 304 305 306 if (ret & I2C_NAK_TXDATA_NOACK) 307 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 308 } 309 310 return ret; 311 } 312 313 314 /** 315 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device. 316 * 317 * @control: I2C adapter reference 318 * @address: The I2C address of the slave device. 319 * @data: Placeholder to store received data. 320 * @numbytes: The amount of data to transmit. 321 * @i2c_flag: Flags for transmission 322 * 323 * Returns 0 on success or error. 324 */ 325 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, 326 uint8_t address, uint8_t *data, 327 uint32_t numbytes, uint8_t i2c_flag) 328 { 329 struct amdgpu_device *adev = to_amdgpu_device(control); 330 uint32_t bytes_received, ret = I2C_OK; 331 332 bytes_received = 0; 333 334 /* Set the I2C slave address */ 335 smu_v11_0_i2c_set_address(control, address); 336 337 /* Enable I2C */ 338 smu_v11_0_i2c_enable(control, true); 339 340 while (numbytes > 0) { 341 uint32_t reg = 0; 342 343 smu_v11_0_i2c_clear_status(control); 344 345 346 /* Prepare transaction */ 347 348 /* Each time we disable I2C, so this is not a restart */ 349 if (bytes_received == 0) 350 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, RESTART, 351 (i2c_flag & I2C_RESTART) ? 1 : 0); 352 353 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0); 354 /* Read */ 355 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1); 356 357 /* Transmitting last byte */ 358 if (numbytes == 1) 359 /* Final transaction, so send stop if requested */ 360 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, STOP, 361 (i2c_flag & I2C_NO_STOP) ? 0 : 1); 362 363 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 364 365 ret = smu_v11_0_i2c_poll_rx_status(control); 366 367 /* Any error, no point in proceeding */ 368 if (ret != I2C_OK) { 369 if (ret & I2C_SW_TIMEOUT) 370 DRM_ERROR("TIMEOUT ERROR !!!"); 371 372 if (ret & I2C_NAK_7B_ADDR_NOACK) 373 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 374 375 if (ret & I2C_NAK_TXDATA_NOACK) 376 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 377 378 break; 379 } 380 381 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); 382 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); 383 384 /* Record that the bytes were received */ 385 bytes_received++; 386 numbytes--; 387 } 388 389 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :", 390 (uint16_t)address, bytes_received); 391 392 if (drm_debug_enabled(DRM_UT_DRIVER)) { 393 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 394 16, 1, data, bytes_received, false); 395 } 396 397 return ret; 398 } 399 400 static void smu_v11_0_i2c_abort(struct i2c_adapter *control) 401 { 402 struct amdgpu_device *adev = to_amdgpu_device(control); 403 uint32_t reg = 0; 404 405 /* Enable I2C engine; */ 406 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1); 407 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 408 409 /* Abort previous transaction */ 410 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1); 411 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 412 413 DRM_DEBUG_DRIVER("I2C_Abort() Done."); 414 } 415 416 417 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control) 418 { 419 struct amdgpu_device *adev = to_amdgpu_device(control); 420 421 const uint32_t IDLE_TIMEOUT = 1024; 422 uint32_t timeout_count = 0; 423 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity; 424 425 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 426 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 427 428 429 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && 430 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { 431 /* 432 * Nobody is using I2C engine, but engine remains active because 433 * someone missed to send STOP 434 */ 435 smu_v11_0_i2c_abort(control); 436 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) { 437 /* Nobody is using I2C engine */ 438 return true; 439 } 440 441 /* Keep reading activity bit until it's cleared */ 442 do { 443 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY); 444 445 if (REG_GET_FIELD(reg_ic_clr_activity, 446 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0) 447 return true; 448 449 ++timeout_count; 450 451 } while (timeout_count < IDLE_TIMEOUT); 452 453 return false; 454 } 455 456 static void smu_v11_0_i2c_init(struct i2c_adapter *control) 457 { 458 /* Disable clock gating */ 459 smu_v11_0_i2c_set_clock_gating(control, false); 460 461 if (!smu_v11_0_i2c_activity_done(control)) 462 DRM_WARN("I2C busy !"); 463 464 /* Disable I2C */ 465 smu_v11_0_i2c_enable(control, false); 466 467 /* Configure I2C to operate as master and in standard mode */ 468 smu_v11_0_i2c_configure(control); 469 470 /* Initialize the clock to 50 kHz default */ 471 smu_v11_0_i2c_set_clock(control); 472 473 } 474 475 static void smu_v11_0_i2c_fini(struct i2c_adapter *control) 476 { 477 struct amdgpu_device *adev = to_amdgpu_device(control); 478 uint32_t reg_ic_enable_status, reg_ic_enable; 479 480 smu_v11_0_i2c_enable(control, false); 481 482 /* Double check if disabled, else force abort */ 483 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 484 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 485 486 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && 487 (REG_GET_FIELD(reg_ic_enable_status, 488 CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { 489 /* 490 * Nobody is using I2C engine, but engine remains active because 491 * someone missed to send STOP 492 */ 493 smu_v11_0_i2c_abort(control); 494 } 495 496 /* Restore clock gating */ 497 498 /* 499 * TODO Reenabling clock gating seems to break subsequent SMU operation 500 * on the I2C bus. My guess is that SMU doesn't disable clock gating like 501 * we do here before working with the bus. So for now just don't restore 502 * it but later work with SMU to see if they have this issue and can 503 * update their code appropriately 504 */ 505 /* smu_v11_0_i2c_set_clock_gating(control, true); */ 506 507 } 508 509 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) 510 { 511 struct amdgpu_device *adev = to_amdgpu_device(control); 512 513 /* Send PPSMC_MSG_RequestI2CBus */ 514 if (!amdgpu_dpm_smu_i2c_bus_access(adev, true)) 515 return true; 516 517 return false; 518 } 519 520 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control) 521 { 522 struct amdgpu_device *adev = to_amdgpu_device(control); 523 524 /* Send PPSMC_MSG_ReleaseI2CBus */ 525 if (!amdgpu_dpm_smu_i2c_bus_access(adev, false)) 526 return true; 527 528 return false; 529 } 530 531 /***************************** I2C GLUE ****************************/ 532 533 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control, 534 uint8_t address, 535 uint8_t *data, 536 uint32_t numbytes) 537 { 538 uint32_t ret = 0; 539 540 /* First 2 bytes are dummy write to set EEPROM address */ 541 ret = smu_v11_0_i2c_transmit(control, address, data, 2, I2C_NO_STOP); 542 if (ret != I2C_OK) 543 goto Fail; 544 545 /* Now read data starting with that address */ 546 ret = smu_v11_0_i2c_receive(control, address, data + 2, numbytes - 2, 547 I2C_RESTART); 548 549 Fail: 550 if (ret != I2C_OK) 551 DRM_ERROR("ReadData() - I2C error occurred :%x", ret); 552 553 return ret; 554 } 555 556 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control, 557 uint8_t address, 558 uint8_t *data, 559 uint32_t numbytes) 560 { 561 uint32_t ret; 562 563 ret = smu_v11_0_i2c_transmit(control, address, data, numbytes, 0); 564 565 if (ret != I2C_OK) 566 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret); 567 else 568 /* 569 * According to EEPROM spec there is a MAX of 10 ms required for 570 * EEPROM to flush internal RX buffer after STOP was issued at the 571 * end of write transaction. During this time the EEPROM will not be 572 * responsive to any more commands - so wait a bit more. 573 * 574 * TODO Improve to wait for first ACK for slave address after 575 * internal write cycle done. 576 */ 577 msleep(10); 578 579 return ret; 580 581 } 582 583 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 584 { 585 struct amdgpu_device *adev = to_amdgpu_device(i2c); 586 587 if (!smu_v11_0_i2c_bus_lock(i2c)) { 588 DRM_ERROR("Failed to lock the bus from SMU"); 589 return; 590 } 591 592 adev->pm.bus_locked = true; 593 } 594 595 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 596 { 597 WARN_ONCE(1, "This operation not supposed to run in atomic context!"); 598 return false; 599 } 600 601 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 602 { 603 struct amdgpu_device *adev = to_amdgpu_device(i2c); 604 605 if (!smu_v11_0_i2c_bus_unlock(i2c)) { 606 DRM_ERROR("Failed to unlock the bus from SMU"); 607 return; 608 } 609 610 adev->pm.bus_locked = false; 611 } 612 613 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { 614 .lock_bus = lock_bus, 615 .trylock_bus = trylock_bus, 616 .unlock_bus = unlock_bus, 617 }; 618 619 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, 620 struct i2c_msg *msgs, int num) 621 { 622 int i, ret; 623 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap); 624 625 if (!adev->pm.bus_locked) { 626 DRM_ERROR("I2C bus unlocked, stopping transaction!"); 627 return -EIO; 628 } 629 630 smu_v11_0_i2c_init(i2c_adap); 631 632 for (i = 0; i < num; i++) { 633 if (msgs[i].flags & I2C_M_RD) 634 ret = smu_v11_0_i2c_read_data(i2c_adap, 635 (uint8_t)msgs[i].addr, 636 msgs[i].buf, msgs[i].len); 637 else 638 ret = smu_v11_0_i2c_write_data(i2c_adap, 639 (uint8_t)msgs[i].addr, 640 msgs[i].buf, msgs[i].len); 641 642 if (ret != I2C_OK) { 643 num = -EIO; 644 break; 645 } 646 } 647 648 smu_v11_0_i2c_fini(i2c_adap); 649 return num; 650 } 651 652 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap) 653 { 654 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 655 } 656 657 658 static const struct i2c_algorithm smu_v11_0_i2c_algo = { 659 .master_xfer = smu_v11_0_i2c_xfer, 660 .functionality = smu_v11_0_i2c_func, 661 }; 662 663 int smu_v11_0_i2c_control_init(struct i2c_adapter *control) 664 { 665 struct amdgpu_device *adev = to_amdgpu_device(control); 666 int res; 667 668 control->owner = THIS_MODULE; 669 control->class = I2C_CLASS_SPD; 670 control->dev.parent = &adev->pdev->dev; 671 control->algo = &smu_v11_0_i2c_algo; 672 snprintf(control->name, sizeof(control->name), "AMDGPU SMU"); 673 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; 674 675 res = i2c_add_adapter(control); 676 if (res) 677 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 678 679 return res; 680 } 681 682 void smu_v11_0_i2c_control_fini(struct i2c_adapter *control) 683 { 684 i2c_del_adapter(control); 685 } 686 687 /* 688 * Keep this for future unit test if bugs arise 689 */ 690 #if 0 691 #define I2C_TARGET_ADDR 0xA0 692 693 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) 694 { 695 696 uint32_t ret = I2C_OK; 697 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef}; 698 699 700 DRM_INFO("Begin"); 701 702 if (!smu_v11_0_i2c_bus_lock(control)) { 703 DRM_ERROR("Failed to lock the bus!."); 704 return false; 705 } 706 707 smu_v11_0_i2c_init(control); 708 709 /* Write 0xde to address 0x0000 on the EEPROM */ 710 ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6); 711 712 ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6); 713 714 smu_v11_0_i2c_fini(control); 715 716 smu_v11_0_i2c_bus_unlock(control); 717 718 719 DRM_INFO("End"); 720 return true; 721 } 722 #endif 723