1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smuio/smuio_11_0_0_offset.h" 25 #include "smuio/smuio_11_0_0_sh_mask.h" 26 27 #include "smu_v11_0_i2c.h" 28 #include "amdgpu.h" 29 #include "amdgpu_dpm.h" 30 #include "soc15_common.h" 31 #include <drm/drm_fixed.h> 32 #include <drm/drm_drv.h> 33 #include "amdgpu_amdkfd.h" 34 #include <linux/i2c.h> 35 #include <linux/pci.h> 36 37 /* error codes */ 38 #define I2C_OK 0 39 #define I2C_NAK_7B_ADDR_NOACK 1 40 #define I2C_NAK_TXDATA_NOACK 2 41 #define I2C_TIMEOUT 4 42 #define I2C_SW_TIMEOUT 8 43 #define I2C_ABORT 0x10 44 45 #define I2C_X_RESTART BIT(31) 46 47 static void smu_v11_0_i2c_set_clock_gating(struct i2c_adapter *control, bool en) 48 { 49 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 50 struct amdgpu_device *adev = smu_i2c->adev; 51 uint32_t reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT); 52 53 reg = REG_SET_FIELD(reg, SMUIO_PWRMGT, i2c_clk_gate_en, en ? 1 : 0); 54 WREG32_SOC15(SMUIO, 0, mmSMUIO_PWRMGT, reg); 55 } 56 57 /* The T_I2C_POLL_US is defined as follows: 58 * 59 * "Define a timer interval (t_i2c_poll) equal to 10 times the 60 * signalling period for the highest I2C transfer speed used in the 61 * system and supported by DW_apb_i2c. For instance, if the highest 62 * I2C data transfer mode is 400 kb/s, then t_i2c_poll is 25 us." -- 63 * DesignWare DW_apb_i2c Databook, Version 1.21a, section 3.8.3.1, 64 * page 56, with grammar and syntax corrections. 65 * 66 * Vcc for our device is at 1.8V which puts it at 400 kHz, 67 * see Atmel AT24CM02 datasheet, section 8.3 DC Characteristics table, page 14. 68 * 69 * The procedure to disable the IP block is described in section 70 * 3.8.3 Disabling DW_apb_i2c on page 56. 71 */ 72 #define I2C_SPEED_MODE_FAST 2 73 #define T_I2C_POLL_US 25 74 #define I2C_MAX_T_POLL_COUNT 1000 75 76 static int smu_v11_0_i2c_enable(struct i2c_adapter *control, bool enable) 77 { 78 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 79 struct amdgpu_device *adev = smu_i2c->adev; 80 81 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, enable ? 1 : 0); 82 83 if (!enable) { 84 int ii; 85 86 for (ii = I2C_MAX_T_POLL_COUNT; ii > 0; ii--) { 87 u32 en_stat = RREG32_SOC15(SMUIO, 88 0, 89 mmCKSVII2C_IC_ENABLE_STATUS); 90 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN)) 91 udelay(T_I2C_POLL_US); 92 else 93 return I2C_OK; 94 } 95 96 return I2C_ABORT; 97 } 98 99 return I2C_OK; 100 } 101 102 static void smu_v11_0_i2c_clear_status(struct i2c_adapter *control) 103 { 104 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 105 struct amdgpu_device *adev = smu_i2c->adev; 106 /* do */ 107 { 108 RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_INTR); 109 110 } /* while (reg_CKSVII2C_ic_clr_intr == 0) */ 111 } 112 113 static void smu_v11_0_i2c_configure(struct i2c_adapter *control) 114 { 115 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 116 struct amdgpu_device *adev = smu_i2c->adev; 117 uint32_t reg = 0; 118 119 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_SLAVE_DISABLE, 1); 120 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_RESTART_EN, 1); 121 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_MASTER, 0); 122 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_10BITADDR_SLAVE, 0); 123 /* The values of IC_MAX_SPEED_MODE are, 124 * 1: standard mode, 0 - 100 Kb/s, 125 * 2: fast mode, <= 400 Kb/s, or fast mode plus, <= 1000 Kb/s, 126 * 3: high speed mode, <= 3.4 Mb/s. 127 */ 128 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MAX_SPEED_MODE, 129 I2C_SPEED_MODE_FAST); 130 reg = REG_SET_FIELD(reg, CKSVII2C_IC_CON, IC_MASTER_MODE, 1); 131 132 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CON, reg); 133 } 134 135 static void smu_v11_0_i2c_set_clock(struct i2c_adapter *control) 136 { 137 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 138 struct amdgpu_device *adev = smu_i2c->adev; 139 140 /* 141 * Standard mode speed, These values are taken from SMUIO MAS, 142 * but are different from what is given is 143 * Synopsys spec. The values here are based on assumption 144 * that refclock is 100MHz 145 * 146 * Configuration for standard mode; Speed = 100kbps 147 * Scale linearly, for now only support standard speed clock 148 * This will work only with 100M ref clock 149 * 150 * TBD:Change the calculation to take into account ref clock values also. 151 */ 152 153 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_FS_SPKLEN, 2); 154 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_HCNT, 120); 155 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SS_SCL_LCNT, 130); 156 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_SDA_HOLD, 20); 157 } 158 159 static void smu_v11_0_i2c_set_address(struct i2c_adapter *control, u16 address) 160 { 161 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 162 struct amdgpu_device *adev = smu_i2c->adev; 163 164 /* The IC_TAR::IC_TAR field is 10-bits wide. 165 * It takes a 7-bit or 10-bit addresses as an address, 166 * i.e. no read/write bit--no wire format, just the address. 167 */ 168 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TAR, address & 0x3FF); 169 } 170 171 static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) 172 { 173 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 174 struct amdgpu_device *adev = smu_i2c->adev; 175 uint32_t ret = I2C_OK; 176 uint32_t reg, reg_c_tx_abrt_source; 177 178 /*Check if transmission is completed */ 179 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 180 181 do { 182 if (time_after(jiffies, timeout_counter)) { 183 ret |= I2C_SW_TIMEOUT; 184 break; 185 } 186 187 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 188 189 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); 190 191 if (ret != I2C_OK) 192 return ret; 193 194 /* This only checks if NAK is received and transaction got aborted */ 195 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_INTR_STAT); 196 197 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { 198 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 199 drm_info(adev_to_drm(adev), 200 "TX was terminated, IC_TX_ABRT_SOURCE val is:%x", 201 reg_c_tx_abrt_source); 202 203 /* Check for stop due to NACK */ 204 if (REG_GET_FIELD(reg_c_tx_abrt_source, 205 CKSVII2C_IC_TX_ABRT_SOURCE, 206 ABRT_TXDATA_NOACK) == 1) { 207 208 ret |= I2C_NAK_TXDATA_NOACK; 209 210 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, 211 CKSVII2C_IC_TX_ABRT_SOURCE, 212 ABRT_7B_ADDR_NOACK) == 1) { 213 214 ret |= I2C_NAK_7B_ADDR_NOACK; 215 } else { 216 ret |= I2C_ABORT; 217 } 218 219 smu_v11_0_i2c_clear_status(control); 220 } 221 222 return ret; 223 } 224 225 static uint32_t smu_v11_0_i2c_poll_rx_status(struct i2c_adapter *control) 226 { 227 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 228 struct amdgpu_device *adev = smu_i2c->adev; 229 uint32_t ret = I2C_OK; 230 uint32_t reg_ic_status, reg_c_tx_abrt_source; 231 232 reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); 233 234 /* If slave is not present */ 235 if (REG_GET_FIELD(reg_c_tx_abrt_source, 236 CKSVII2C_IC_TX_ABRT_SOURCE, 237 ABRT_7B_ADDR_NOACK) == 1) { 238 ret |= I2C_NAK_7B_ADDR_NOACK; 239 240 smu_v11_0_i2c_clear_status(control); 241 } else { /* wait till some data is there in RXFIFO */ 242 /* Poll for some byte in RXFIFO */ 243 unsigned long timeout_counter = jiffies + msecs_to_jiffies(20); 244 245 do { 246 if (time_after(jiffies, timeout_counter)) { 247 ret |= I2C_SW_TIMEOUT; 248 break; 249 } 250 251 reg_ic_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 252 253 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); 254 } 255 256 return ret; 257 } 258 259 /** 260 * smu_v11_0_i2c_transmit - Send a block of data over the I2C bus to a slave device. 261 * 262 * @control: I2C adapter reference 263 * @address: The I2C address of the slave device. 264 * @data: The data to transmit over the bus. 265 * @numbytes: The amount of data to transmit. 266 * @i2c_flag: Flags for transmission 267 * 268 * Returns 0 on success or error. 269 */ 270 static uint32_t smu_v11_0_i2c_transmit(struct i2c_adapter *control, 271 u16 address, u8 *data, 272 u32 numbytes, u32 i2c_flag) 273 { 274 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 275 struct amdgpu_device *adev = smu_i2c->adev; 276 u32 bytes_sent, reg, ret = I2C_OK; 277 unsigned long timeout_counter; 278 279 bytes_sent = 0; 280 281 DRM_DEBUG_DRIVER("I2C_Transmit(), address = %x, bytes = %d , data: ", 282 address, numbytes); 283 284 if (drm_debug_enabled(DRM_UT_DRIVER)) { 285 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 286 16, 1, data, numbytes, false); 287 } 288 289 /* Set the I2C slave address */ 290 smu_v11_0_i2c_set_address(control, address); 291 /* Enable I2C */ 292 smu_v11_0_i2c_enable(control, true); 293 294 /* Clear status bits */ 295 smu_v11_0_i2c_clear_status(control); 296 297 timeout_counter = jiffies + msecs_to_jiffies(20); 298 299 while (numbytes > 0) { 300 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 301 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { 302 /* 303 * We waited for too long for the transmission 304 * FIFO to become not-full. Exit the loop 305 * with error. 306 */ 307 if (time_after(jiffies, timeout_counter)) { 308 ret |= I2C_SW_TIMEOUT; 309 goto Err; 310 } 311 } else { 312 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 313 data[bytes_sent]); 314 315 /* Final message, final byte, must generate a 316 * STOP to release the bus, i.e. don't hold 317 * SCL low. 318 */ 319 if (numbytes == 1 && i2c_flag & I2C_M_STOP) 320 reg = REG_SET_FIELD(reg, 321 CKSVII2C_IC_DATA_CMD, 322 STOP, 1); 323 324 if (bytes_sent == 0 && i2c_flag & I2C_X_RESTART) 325 reg = REG_SET_FIELD(reg, 326 CKSVII2C_IC_DATA_CMD, 327 RESTART, 1); 328 329 /* Write */ 330 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 0); 331 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 332 333 /* Record that the bytes were transmitted */ 334 bytes_sent++; 335 numbytes--; 336 } 337 } 338 339 ret = smu_v11_0_i2c_poll_tx_status(control); 340 Err: 341 /* Any error, no point in proceeding */ 342 if (ret != I2C_OK) { 343 if (ret & I2C_SW_TIMEOUT) 344 DRM_ERROR("TIMEOUT ERROR !!!"); 345 346 if (ret & I2C_NAK_7B_ADDR_NOACK) 347 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 348 349 350 if (ret & I2C_NAK_TXDATA_NOACK) 351 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 352 } 353 354 return ret; 355 } 356 357 358 /** 359 * smu_v11_0_i2c_receive - Receive a block of data over the I2C bus from a slave device. 360 * 361 * @control: I2C adapter reference 362 * @address: The I2C address of the slave device. 363 * @data: Placeholder to store received data. 364 * @numbytes: The amount of data to transmit. 365 * @i2c_flag: Flags for transmission 366 * 367 * Returns 0 on success or error. 368 */ 369 static uint32_t smu_v11_0_i2c_receive(struct i2c_adapter *control, 370 u16 address, u8 *data, 371 u32 numbytes, u32 i2c_flag) 372 { 373 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 374 struct amdgpu_device *adev = smu_i2c->adev; 375 uint32_t bytes_received, ret = I2C_OK; 376 377 bytes_received = 0; 378 379 /* Set the I2C slave address */ 380 smu_v11_0_i2c_set_address(control, address); 381 382 /* Enable I2C */ 383 smu_v11_0_i2c_enable(control, true); 384 385 while (numbytes > 0) { 386 uint32_t reg = 0; 387 388 smu_v11_0_i2c_clear_status(control); 389 390 /* Prepare transaction */ 391 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT, 0); 392 /* Read */ 393 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, CMD, 1); 394 395 /* Final message, final byte, must generate a STOP 396 * to release the bus, i.e. don't hold SCL low. 397 */ 398 if (numbytes == 1 && i2c_flag & I2C_M_STOP) 399 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, 400 STOP, 1); 401 402 if (bytes_received == 0 && i2c_flag & I2C_X_RESTART) 403 reg = REG_SET_FIELD(reg, CKSVII2C_IC_DATA_CMD, 404 RESTART, 1); 405 406 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD, reg); 407 408 ret = smu_v11_0_i2c_poll_rx_status(control); 409 410 /* Any error, no point in proceeding */ 411 if (ret != I2C_OK) { 412 if (ret & I2C_SW_TIMEOUT) 413 DRM_ERROR("TIMEOUT ERROR !!!"); 414 415 if (ret & I2C_NAK_7B_ADDR_NOACK) 416 DRM_ERROR("Received I2C_NAK_7B_ADDR_NOACK !!!"); 417 418 if (ret & I2C_NAK_TXDATA_NOACK) 419 DRM_ERROR("Received I2C_NAK_TXDATA_NOACK !!!"); 420 421 break; 422 } 423 424 reg = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_DATA_CMD); 425 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); 426 427 /* Record that the bytes were received */ 428 bytes_received++; 429 numbytes--; 430 } 431 432 DRM_DEBUG_DRIVER("I2C_Receive(), address = %x, bytes = %d, data :", 433 (uint16_t)address, bytes_received); 434 435 if (drm_debug_enabled(DRM_UT_DRIVER)) { 436 print_hex_dump(KERN_INFO, "data: ", DUMP_PREFIX_NONE, 437 16, 1, data, bytes_received, false); 438 } 439 440 return ret; 441 } 442 443 static void smu_v11_0_i2c_abort(struct i2c_adapter *control) 444 { 445 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 446 struct amdgpu_device *adev = smu_i2c->adev; 447 uint32_t reg = 0; 448 449 /* Enable I2C engine; */ 450 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1); 451 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 452 453 /* Abort previous transaction */ 454 reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ABORT, 1); 455 WREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE, reg); 456 457 DRM_DEBUG_DRIVER("I2C_Abort() Done."); 458 } 459 460 static bool smu_v11_0_i2c_activity_done(struct i2c_adapter *control) 461 { 462 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 463 struct amdgpu_device *adev = smu_i2c->adev; 464 465 const uint32_t IDLE_TIMEOUT = 1024; 466 uint32_t timeout_count = 0; 467 uint32_t reg_ic_enable, reg_ic_enable_status, reg_ic_clr_activity; 468 469 reg_ic_enable_status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 470 reg_ic_enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 471 472 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && 473 (REG_GET_FIELD(reg_ic_enable_status, CKSVII2C_IC_ENABLE_STATUS, IC_EN) == 1)) { 474 /* 475 * Nobody is using I2C engine, but engine remains active because 476 * someone missed to send STOP 477 */ 478 smu_v11_0_i2c_abort(control); 479 } else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) { 480 /* Nobody is using I2C engine */ 481 return true; 482 } 483 484 /* Keep reading activity bit until it's cleared */ 485 do { 486 reg_ic_clr_activity = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_CLR_ACTIVITY); 487 488 if (REG_GET_FIELD(reg_ic_clr_activity, 489 CKSVII2C_IC_CLR_ACTIVITY, CLR_ACTIVITY) == 0) 490 return true; 491 492 ++timeout_count; 493 494 } while (timeout_count < IDLE_TIMEOUT); 495 496 return false; 497 } 498 499 static void smu_v11_0_i2c_init(struct i2c_adapter *control) 500 { 501 int res; 502 503 /* Disable clock gating */ 504 smu_v11_0_i2c_set_clock_gating(control, false); 505 506 if (!smu_v11_0_i2c_activity_done(control)) 507 DRM_WARN("I2C busy !"); 508 509 /* Disable I2C */ 510 res = smu_v11_0_i2c_enable(control, false); 511 if (res != I2C_OK) 512 smu_v11_0_i2c_abort(control); 513 514 /* Configure I2C to operate as master and in standard mode */ 515 smu_v11_0_i2c_configure(control); 516 517 /* Initialize the clock to 50 kHz default */ 518 smu_v11_0_i2c_set_clock(control); 519 520 } 521 522 static void smu_v11_0_i2c_fini(struct i2c_adapter *control) 523 { 524 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 525 struct amdgpu_device *adev = smu_i2c->adev; 526 u32 status, enable, en_stat; 527 int res; 528 529 res = smu_v11_0_i2c_enable(control, false); 530 if (res != I2C_OK) { 531 status = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_STATUS); 532 enable = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE); 533 en_stat = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_ENABLE_STATUS); 534 535 /* Nobody is using the I2C engine, yet it remains 536 * active, possibly because someone missed to send 537 * STOP. 538 */ 539 DRM_DEBUG_DRIVER("Aborting from fini: status:0x%08x " 540 "enable:0x%08x enable_stat:0x%08x", 541 status, enable, en_stat); 542 smu_v11_0_i2c_abort(control); 543 } 544 545 /* Restore clock gating */ 546 547 /* 548 * TODO Reenabling clock gating seems to break subsequent SMU operation 549 * on the I2C bus. My guess is that SMU doesn't disable clock gating like 550 * we do here before working with the bus. So for now just don't restore 551 * it but later work with SMU to see if they have this issue and can 552 * update their code appropriately 553 */ 554 /* smu_v11_0_i2c_set_clock_gating(control, true); */ 555 556 } 557 558 static bool smu_v11_0_i2c_bus_lock(struct i2c_adapter *control) 559 { 560 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 561 struct amdgpu_device *adev = smu_i2c->adev; 562 563 /* Send PPSMC_MSG_RequestI2CBus */ 564 if (!amdgpu_dpm_smu_i2c_bus_access(adev, true)) 565 return true; 566 567 return false; 568 } 569 570 static bool smu_v11_0_i2c_bus_unlock(struct i2c_adapter *control) 571 { 572 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(control); 573 struct amdgpu_device *adev = smu_i2c->adev; 574 575 /* Send PPSMC_MSG_ReleaseI2CBus */ 576 if (!amdgpu_dpm_smu_i2c_bus_access(adev, false)) 577 return true; 578 579 return false; 580 } 581 582 /***************************** I2C GLUE ****************************/ 583 584 static uint32_t smu_v11_0_i2c_read_data(struct i2c_adapter *control, 585 struct i2c_msg *msg, uint32_t i2c_flag) 586 { 587 uint32_t ret; 588 589 ret = smu_v11_0_i2c_receive(control, msg->addr, msg->buf, msg->len, i2c_flag); 590 591 if (ret != I2C_OK) 592 DRM_ERROR("ReadData() - I2C error occurred :%x", ret); 593 594 return ret; 595 } 596 597 static uint32_t smu_v11_0_i2c_write_data(struct i2c_adapter *control, 598 struct i2c_msg *msg, uint32_t i2c_flag) 599 { 600 uint32_t ret; 601 602 ret = smu_v11_0_i2c_transmit(control, msg->addr, msg->buf, msg->len, i2c_flag); 603 604 if (ret != I2C_OK) 605 DRM_ERROR("WriteI2CData() - I2C error occurred :%x", ret); 606 607 return ret; 608 609 } 610 611 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 612 { 613 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c); 614 struct amdgpu_device *adev = smu_i2c->adev; 615 616 mutex_lock(&smu_i2c->mutex); 617 if (!smu_v11_0_i2c_bus_lock(i2c)) 618 DRM_ERROR("Failed to lock the bus from SMU"); 619 else 620 adev->pm.bus_locked = true; 621 } 622 623 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 624 { 625 WARN_ONCE(1, "This operation not supposed to run in atomic context!"); 626 return false; 627 } 628 629 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 630 { 631 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c); 632 struct amdgpu_device *adev = smu_i2c->adev; 633 634 if (!smu_v11_0_i2c_bus_unlock(i2c)) 635 DRM_ERROR("Failed to unlock the bus from SMU"); 636 else 637 adev->pm.bus_locked = false; 638 mutex_unlock(&smu_i2c->mutex); 639 } 640 641 static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { 642 .lock_bus = lock_bus, 643 .trylock_bus = trylock_bus, 644 .unlock_bus = unlock_bus, 645 }; 646 647 static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, 648 struct i2c_msg *msg, int num) 649 { 650 int i, ret; 651 u16 addr, dir; 652 653 smu_v11_0_i2c_init(i2c_adap); 654 655 /* From the client's point of view, this sequence of 656 * messages-- the array i2c_msg *msg, is a single transaction 657 * on the bus, starting with START and ending with STOP. 658 * 659 * The client is welcome to send any sequence of messages in 660 * this array, as processing under this function here is 661 * striving to be agnostic. 662 * 663 * Record the first address and direction we see. If either 664 * changes for a subsequent message, generate ReSTART. The 665 * DW_apb_i2c databook, v1.21a, specifies that ReSTART is 666 * generated when the direction changes, with the default IP 667 * block parameter settings, but it doesn't specify if ReSTART 668 * is generated when the address changes (possibly...). We 669 * don't rely on the default IP block parameter settings as 670 * the block is shared and they may change. 671 */ 672 if (num > 0) { 673 addr = msg[0].addr; 674 dir = msg[0].flags & I2C_M_RD; 675 } 676 677 for (i = 0; i < num; i++) { 678 u32 i2c_flag = 0; 679 680 if (msg[i].addr != addr || (msg[i].flags ^ dir) & I2C_M_RD) { 681 addr = msg[i].addr; 682 dir = msg[i].flags & I2C_M_RD; 683 i2c_flag |= I2C_X_RESTART; 684 } 685 686 if (i == num - 1) { 687 /* Set the STOP bit on the last message, so 688 * that the IP block generates a STOP after 689 * the last byte of the message. 690 */ 691 i2c_flag |= I2C_M_STOP; 692 } 693 694 if (msg[i].flags & I2C_M_RD) 695 ret = smu_v11_0_i2c_read_data(i2c_adap, 696 msg + i, 697 i2c_flag); 698 else 699 ret = smu_v11_0_i2c_write_data(i2c_adap, 700 msg + i, 701 i2c_flag); 702 703 if (ret != I2C_OK) { 704 num = -EIO; 705 break; 706 } 707 } 708 709 smu_v11_0_i2c_fini(i2c_adap); 710 return num; 711 } 712 713 static u32 smu_v11_0_i2c_func(struct i2c_adapter *adap) 714 { 715 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 716 } 717 718 static const struct i2c_algorithm smu_v11_0_i2c_algo = { 719 .master_xfer = smu_v11_0_i2c_xfer, 720 .functionality = smu_v11_0_i2c_func, 721 }; 722 723 static const struct i2c_adapter_quirks smu_v11_0_i2c_control_quirks = { 724 .flags = I2C_AQ_NO_ZERO_LEN, 725 }; 726 727 int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) 728 { 729 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[0]; 730 struct i2c_adapter *control = &smu_i2c->adapter; 731 int res; 732 733 smu_i2c->adev = adev; 734 smu_i2c->port = 0; 735 mutex_init(&smu_i2c->mutex); 736 control->owner = THIS_MODULE; 737 control->class = I2C_CLASS_HWMON; 738 control->dev.parent = &adev->pdev->dev; 739 control->algo = &smu_v11_0_i2c_algo; 740 snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); 741 control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; 742 control->quirks = &smu_v11_0_i2c_control_quirks; 743 i2c_set_adapdata(control, smu_i2c); 744 745 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 746 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter; 747 748 res = devm_i2c_add_adapter(adev->dev, control); 749 if (res) 750 DRM_ERROR("Failed to register hw i2c, err: %d\n", res); 751 752 return res; 753 } 754 755 void smu_v11_0_i2c_control_fini(struct amdgpu_device *adev) 756 { 757 adev->pm.ras_eeprom_i2c_bus = NULL; 758 adev->pm.fru_eeprom_i2c_bus = NULL; 759 } 760 761 /* 762 * Keep this for future unit test if bugs arise 763 */ 764 #if 0 765 #define I2C_TARGET_ADDR 0xA0 766 767 bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) 768 { 769 770 uint32_t ret = I2C_OK; 771 uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef}; 772 773 774 drm_info(adev_to_drm(adev), "Begin"); 775 776 if (!smu_v11_0_i2c_bus_lock(control)) { 777 DRM_ERROR("Failed to lock the bus!."); 778 return false; 779 } 780 781 smu_v11_0_i2c_init(control); 782 783 /* Write 0xde to address 0x0000 on the EEPROM */ 784 ret = smu_v11_0_i2c_write_data(control, I2C_TARGET_ADDR, data, 6); 785 786 ret = smu_v11_0_i2c_read_data(control, I2C_TARGET_ADDR, data, 6); 787 788 smu_v11_0_i2c_fini(control); 789 790 smu_v11_0_i2c_bus_unlock(control); 791 792 793 drm_info(adev_to_drm(adev), "End"); 794 return true; 795 } 796 #endif 797